1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 18 * 19 * devfn pci_slot<<3 + funno 20 * one pci bus can have 32 devices and each device can have 8 functions. 21 * 22 * In bonito north bridge, pci slot = IDSEL bit - 12. 23 * For example, PCI_IDSEL_VIA686B = 17, 24 * pci slot = 17-12=5 25 * 26 * so 27 * VT686B_FUN0's devfn = (5<<3)+0 28 * VT686B_FUN1's devfn = (5<<3)+1 29 * 30 * qemu also uses pci address for north bridge to access pci config register. 31 * bus_no [23:16] 32 * dev_no [15:11] 33 * fun_no [10:8] 34 * reg_no [7:2] 35 * 36 * so function bonito_sbridge_pciaddr for the translation from 37 * north bridge address to pci address. 38 */ 39 40 #include "qemu/osdep.h" 41 42 #include "hw/hw.h" 43 #include "hw/pci/pci.h" 44 #include "hw/i386/pc.h" 45 #include "hw/mips/mips.h" 46 #include "hw/pci/pci_host.h" 47 #include "sysemu/sysemu.h" 48 #include "exec/address-spaces.h" 49 50 //#define DEBUG_BONITO 51 52 #ifdef DEBUG_BONITO 53 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 54 #else 55 #define DPRINTF(fmt, ...) 56 #endif 57 58 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 59 #define BONITO_BOOT_BASE 0x1fc00000 60 #define BONITO_BOOT_SIZE 0x00100000 61 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 62 #define BONITO_FLASH_BASE 0x1c000000 63 #define BONITO_FLASH_SIZE 0x03000000 64 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 65 #define BONITO_SOCKET_BASE 0x1f800000 66 #define BONITO_SOCKET_SIZE 0x00400000 67 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 68 #define BONITO_REG_BASE 0x1fe00000 69 #define BONITO_REG_SIZE 0x00040000 70 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 71 #define BONITO_DEV_BASE 0x1ff00000 72 #define BONITO_DEV_SIZE 0x00100000 73 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 74 #define BONITO_PCILO_BASE 0x10000000 75 #define BONITO_PCILO_BASE_VA 0xb0000000 76 #define BONITO_PCILO_SIZE 0x0c000000 77 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 78 #define BONITO_PCILO0_BASE 0x10000000 79 #define BONITO_PCILO1_BASE 0x14000000 80 #define BONITO_PCILO2_BASE 0x18000000 81 #define BONITO_PCIHI_BASE 0x20000000 82 #define BONITO_PCIHI_SIZE 0x20000000 83 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 84 #define BONITO_PCIIO_BASE 0x1fd00000 85 #define BONITO_PCIIO_BASE_VA 0xbfd00000 86 #define BONITO_PCIIO_SIZE 0x00010000 87 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 88 #define BONITO_PCICFG_BASE 0x1fe80000 89 #define BONITO_PCICFG_SIZE 0x00080000 90 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 91 92 93 #define BONITO_PCICONFIGBASE 0x00 94 #define BONITO_REGBASE 0x100 95 96 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) 97 #define BONITO_PCICONFIG_SIZE (0x100) 98 99 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) 100 #define BONITO_INTERNAL_REG_SIZE (0x70) 101 102 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 103 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 104 105 106 107 /* 1. Bonito h/w Configuration */ 108 /* Power on register */ 109 110 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 111 #define BONITO_BONGENCFG_OFFSET 0x4 112 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ 113 114 /* 2. IO & IDE configuration */ 115 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 116 117 /* 3. IO & IDE configuration */ 118 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 119 120 /* 4. PCI address map control */ 121 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 122 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 123 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 124 125 /* 5. ICU & GPIO regs */ 126 /* GPIO Regs - r/w */ 127 #define BONITO_GPIODATA_OFFSET 0x1c 128 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 129 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 130 131 /* ICU Configuration Regs - r/w */ 132 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 133 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 134 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 135 136 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 137 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 138 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 139 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 140 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 141 142 /* PCI mail boxes */ 143 #define BONITO_PCIMAIL0_OFFSET 0x40 144 #define BONITO_PCIMAIL1_OFFSET 0x44 145 #define BONITO_PCIMAIL2_OFFSET 0x48 146 #define BONITO_PCIMAIL3_OFFSET 0x4c 147 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 148 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 149 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 150 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 151 152 /* 6. PCI cache */ 153 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 154 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 155 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 156 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 157 158 /* 7. other*/ 159 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 160 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 161 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 162 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 163 164 #define BONITO_REGS (0x70 >> 2) 165 166 /* PCI config for south bridge. type 0 */ 167 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 168 #define BONITO_PCICONF_IDSEL_OFFSET 11 169 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 170 #define BONITO_PCICONF_FUN_OFFSET 8 171 #define BONITO_PCICONF_REG_MASK 0xFC 172 #define BONITO_PCICONF_REG_OFFSET 0 173 174 175 /* idsel BIT = pci slot number +12 */ 176 #define PCI_SLOT_BASE 12 177 #define PCI_IDSEL_VIA686B_BIT (17) 178 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) 179 180 #define PCI_ADDR(busno,devno,funno,regno) \ 181 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) 182 183 typedef struct BonitoState BonitoState; 184 185 typedef struct PCIBonitoState 186 { 187 PCIDevice dev; 188 189 BonitoState *pcihost; 190 uint32_t regs[BONITO_REGS]; 191 192 struct bonldma { 193 uint32_t ldmactrl; 194 uint32_t ldmastat; 195 uint32_t ldmaaddr; 196 uint32_t ldmago; 197 } bonldma; 198 199 /* Based at 1fe00300, bonito Copier */ 200 struct boncop { 201 uint32_t copctrl; 202 uint32_t copstat; 203 uint32_t coppaddr; 204 uint32_t copgo; 205 } boncop; 206 207 /* Bonito registers */ 208 MemoryRegion iomem; 209 MemoryRegion iomem_ldma; 210 MemoryRegion iomem_cop; 211 MemoryRegion bonito_pciio; 212 MemoryRegion bonito_localio; 213 214 } PCIBonitoState; 215 216 struct BonitoState { 217 PCIHostState parent_obj; 218 qemu_irq *pic; 219 PCIBonitoState *pci_dev; 220 }; 221 222 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 223 #define BONITO_PCI_HOST_BRIDGE(obj) \ 224 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) 225 226 #define TYPE_PCI_BONITO "Bonito" 227 #define PCI_BONITO(obj) \ 228 OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) 229 230 static void bonito_writel(void *opaque, hwaddr addr, 231 uint64_t val, unsigned size) 232 { 233 PCIBonitoState *s = opaque; 234 uint32_t saddr; 235 int reset = 0; 236 237 saddr = addr >> 2; 238 239 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); 240 switch (saddr) { 241 case BONITO_BONPONCFG: 242 case BONITO_IODEVCFG: 243 case BONITO_SDCFG: 244 case BONITO_PCIMAP: 245 case BONITO_PCIMEMBASECFG: 246 case BONITO_PCIMAP_CFG: 247 case BONITO_GPIODATA: 248 case BONITO_GPIOIE: 249 case BONITO_INTEDGE: 250 case BONITO_INTSTEER: 251 case BONITO_INTPOL: 252 case BONITO_PCIMAIL0: 253 case BONITO_PCIMAIL1: 254 case BONITO_PCIMAIL2: 255 case BONITO_PCIMAIL3: 256 case BONITO_PCICACHECTRL: 257 case BONITO_PCICACHETAG: 258 case BONITO_PCIBADADDR: 259 case BONITO_PCIMSTAT: 260 case BONITO_TIMECFG: 261 case BONITO_CPUCFG: 262 case BONITO_DQCFG: 263 case BONITO_MEMSIZE: 264 s->regs[saddr] = val; 265 break; 266 case BONITO_BONGENCFG: 267 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 268 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 269 } 270 s->regs[saddr] = val; 271 if (reset) { 272 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 273 } 274 break; 275 case BONITO_INTENSET: 276 s->regs[BONITO_INTENSET] = val; 277 s->regs[BONITO_INTEN] |= val; 278 break; 279 case BONITO_INTENCLR: 280 s->regs[BONITO_INTENCLR] = val; 281 s->regs[BONITO_INTEN] &= ~val; 282 break; 283 case BONITO_INTEN: 284 case BONITO_INTISR: 285 DPRINTF("write to readonly bonito register %x\n", saddr); 286 break; 287 default: 288 DPRINTF("write to unknown bonito register %x\n", saddr); 289 break; 290 } 291 } 292 293 static uint64_t bonito_readl(void *opaque, hwaddr addr, 294 unsigned size) 295 { 296 PCIBonitoState *s = opaque; 297 uint32_t saddr; 298 299 saddr = addr >> 2; 300 301 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 302 switch (saddr) { 303 case BONITO_INTISR: 304 return s->regs[saddr]; 305 default: 306 return s->regs[saddr]; 307 } 308 } 309 310 static const MemoryRegionOps bonito_ops = { 311 .read = bonito_readl, 312 .write = bonito_writel, 313 .endianness = DEVICE_NATIVE_ENDIAN, 314 .valid = { 315 .min_access_size = 4, 316 .max_access_size = 4, 317 }, 318 }; 319 320 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 321 uint64_t val, unsigned size) 322 { 323 PCIBonitoState *s = opaque; 324 PCIDevice *d = PCI_DEVICE(s); 325 326 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 327 d->config_write(d, addr, val, 4); 328 } 329 330 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 331 unsigned size) 332 { 333 334 PCIBonitoState *s = opaque; 335 PCIDevice *d = PCI_DEVICE(s); 336 337 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 338 return d->config_read(d, addr, 4); 339 } 340 341 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 342 343 static const MemoryRegionOps bonito_pciconf_ops = { 344 .read = bonito_pciconf_readl, 345 .write = bonito_pciconf_writel, 346 .endianness = DEVICE_NATIVE_ENDIAN, 347 .valid = { 348 .min_access_size = 4, 349 .max_access_size = 4, 350 }, 351 }; 352 353 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 354 unsigned size) 355 { 356 uint32_t val; 357 PCIBonitoState *s = opaque; 358 359 if (addr >= sizeof(s->bonldma)) { 360 return 0; 361 } 362 363 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; 364 365 return val; 366 } 367 368 static void bonito_ldma_writel(void *opaque, hwaddr addr, 369 uint64_t val, unsigned size) 370 { 371 PCIBonitoState *s = opaque; 372 373 if (addr >= sizeof(s->bonldma)) { 374 return; 375 } 376 377 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; 378 } 379 380 static const MemoryRegionOps bonito_ldma_ops = { 381 .read = bonito_ldma_readl, 382 .write = bonito_ldma_writel, 383 .endianness = DEVICE_NATIVE_ENDIAN, 384 .valid = { 385 .min_access_size = 4, 386 .max_access_size = 4, 387 }, 388 }; 389 390 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 391 unsigned size) 392 { 393 uint32_t val; 394 PCIBonitoState *s = opaque; 395 396 if (addr >= sizeof(s->boncop)) { 397 return 0; 398 } 399 400 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; 401 402 return val; 403 } 404 405 static void bonito_cop_writel(void *opaque, hwaddr addr, 406 uint64_t val, unsigned size) 407 { 408 PCIBonitoState *s = opaque; 409 410 if (addr >= sizeof(s->boncop)) { 411 return; 412 } 413 414 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; 415 } 416 417 static const MemoryRegionOps bonito_cop_ops = { 418 .read = bonito_cop_readl, 419 .write = bonito_cop_writel, 420 .endianness = DEVICE_NATIVE_ENDIAN, 421 .valid = { 422 .min_access_size = 4, 423 .max_access_size = 4, 424 }, 425 }; 426 427 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 428 { 429 PCIBonitoState *s = opaque; 430 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 431 uint32_t cfgaddr; 432 uint32_t idsel; 433 uint32_t devno; 434 uint32_t funno; 435 uint32_t regno; 436 uint32_t pciaddr; 437 438 /* support type0 pci config */ 439 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 440 return 0xffffffff; 441 } 442 443 cfgaddr = addr & 0xffff; 444 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 445 446 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; 447 devno = ctz32(idsel); 448 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 449 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 450 451 if (idsel == 0) { 452 fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx 453 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); 454 exit(1); 455 } 456 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 457 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 458 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 459 460 return pciaddr; 461 } 462 463 static void bonito_spciconf_writeb(void *opaque, hwaddr addr, 464 uint32_t val) 465 { 466 PCIBonitoState *s = opaque; 467 PCIDevice *d = PCI_DEVICE(s); 468 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 469 uint32_t pciaddr; 470 uint16_t status; 471 472 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); 473 pciaddr = bonito_sbridge_pciaddr(s, addr); 474 475 if (pciaddr == 0xffffffff) { 476 return; 477 } 478 479 /* set the pci address in s->config_reg */ 480 phb->config_reg = (pciaddr) | (1u << 31); 481 pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1); 482 483 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 484 status = pci_get_word(d->config + PCI_STATUS); 485 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 486 pci_set_word(d->config + PCI_STATUS, status); 487 } 488 489 static void bonito_spciconf_writew(void *opaque, hwaddr addr, 490 uint32_t val) 491 { 492 PCIBonitoState *s = opaque; 493 PCIDevice *d = PCI_DEVICE(s); 494 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 495 uint32_t pciaddr; 496 uint16_t status; 497 498 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); 499 assert((addr & 0x1) == 0); 500 501 pciaddr = bonito_sbridge_pciaddr(s, addr); 502 503 if (pciaddr == 0xffffffff) { 504 return; 505 } 506 507 /* set the pci address in s->config_reg */ 508 phb->config_reg = (pciaddr) | (1u << 31); 509 pci_data_write(phb->bus, phb->config_reg, val, 2); 510 511 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 512 status = pci_get_word(d->config + PCI_STATUS); 513 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 514 pci_set_word(d->config + PCI_STATUS, status); 515 } 516 517 static void bonito_spciconf_writel(void *opaque, hwaddr addr, 518 uint32_t val) 519 { 520 PCIBonitoState *s = opaque; 521 PCIDevice *d = PCI_DEVICE(s); 522 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 523 uint32_t pciaddr; 524 uint16_t status; 525 526 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 527 assert((addr & 0x3) == 0); 528 529 pciaddr = bonito_sbridge_pciaddr(s, addr); 530 531 if (pciaddr == 0xffffffff) { 532 return; 533 } 534 535 /* set the pci address in s->config_reg */ 536 phb->config_reg = (pciaddr) | (1u << 31); 537 pci_data_write(phb->bus, phb->config_reg, val, 4); 538 539 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 540 status = pci_get_word(d->config + PCI_STATUS); 541 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 542 pci_set_word(d->config + PCI_STATUS, status); 543 } 544 545 static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr) 546 { 547 PCIBonitoState *s = opaque; 548 PCIDevice *d = PCI_DEVICE(s); 549 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 550 uint32_t pciaddr; 551 uint16_t status; 552 553 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); 554 pciaddr = bonito_sbridge_pciaddr(s, addr); 555 556 if (pciaddr == 0xffffffff) { 557 return 0xff; 558 } 559 560 /* set the pci address in s->config_reg */ 561 phb->config_reg = (pciaddr) | (1u << 31); 562 563 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 564 status = pci_get_word(d->config + PCI_STATUS); 565 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 566 pci_set_word(d->config + PCI_STATUS, status); 567 568 return pci_data_read(phb->bus, phb->config_reg, 1); 569 } 570 571 static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr) 572 { 573 PCIBonitoState *s = opaque; 574 PCIDevice *d = PCI_DEVICE(s); 575 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 576 uint32_t pciaddr; 577 uint16_t status; 578 579 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); 580 assert((addr & 0x1) == 0); 581 582 pciaddr = bonito_sbridge_pciaddr(s, addr); 583 584 if (pciaddr == 0xffffffff) { 585 return 0xffff; 586 } 587 588 /* set the pci address in s->config_reg */ 589 phb->config_reg = (pciaddr) | (1u << 31); 590 591 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 592 status = pci_get_word(d->config + PCI_STATUS); 593 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 594 pci_set_word(d->config + PCI_STATUS, status); 595 596 return pci_data_read(phb->bus, phb->config_reg, 2); 597 } 598 599 static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr) 600 { 601 PCIBonitoState *s = opaque; 602 PCIDevice *d = PCI_DEVICE(s); 603 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 604 uint32_t pciaddr; 605 uint16_t status; 606 607 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); 608 assert((addr & 0x3) == 0); 609 610 pciaddr = bonito_sbridge_pciaddr(s, addr); 611 612 if (pciaddr == 0xffffffff) { 613 return 0xffffffff; 614 } 615 616 /* set the pci address in s->config_reg */ 617 phb->config_reg = (pciaddr) | (1u << 31); 618 619 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 620 status = pci_get_word(d->config + PCI_STATUS); 621 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 622 pci_set_word(d->config + PCI_STATUS, status); 623 624 return pci_data_read(phb->bus, phb->config_reg, 4); 625 } 626 627 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 628 static const MemoryRegionOps bonito_spciconf_ops = { 629 .old_mmio = { 630 .read = { 631 bonito_spciconf_readb, 632 bonito_spciconf_readw, 633 bonito_spciconf_readl, 634 }, 635 .write = { 636 bonito_spciconf_writeb, 637 bonito_spciconf_writew, 638 bonito_spciconf_writel, 639 }, 640 }, 641 .endianness = DEVICE_NATIVE_ENDIAN, 642 }; 643 644 #define BONITO_IRQ_BASE 32 645 646 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 647 { 648 BonitoState *s = opaque; 649 qemu_irq *pic = s->pic; 650 PCIBonitoState *bonito_state = s->pci_dev; 651 int internal_irq = irq_num - BONITO_IRQ_BASE; 652 653 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 654 qemu_irq_pulse(*pic); 655 } else { /* level triggered */ 656 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 657 qemu_irq_raise(*pic); 658 } else { 659 qemu_irq_lower(*pic); 660 } 661 } 662 } 663 664 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 665 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) 666 { 667 int slot; 668 669 slot = (pci_dev->devfn >> 3); 670 671 switch (slot) { 672 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 673 return irq_num % 4 + BONITO_IRQ_BASE; 674 case 6: /* FULONG2E_ATI_SLOT, VGA */ 675 return 4 + BONITO_IRQ_BASE; 676 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 677 return 5 + BONITO_IRQ_BASE; 678 case 8 ... 12: /* PCI slot 1 to 4 */ 679 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 680 default: /* Unknown device, don't do any translation */ 681 return irq_num; 682 } 683 } 684 685 static void bonito_reset(void *opaque) 686 { 687 PCIBonitoState *s = opaque; 688 689 /* set the default value of north bridge registers */ 690 691 s->regs[BONITO_BONPONCFG] = 0xc40; 692 s->regs[BONITO_BONGENCFG] = 0x1384; 693 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 694 s->regs[BONITO_SDCFG] = 0x255e0091; 695 696 s->regs[BONITO_GPIODATA] = 0x1ff; 697 s->regs[BONITO_GPIOIE] = 0x1ff; 698 s->regs[BONITO_DQCFG] = 0x8; 699 s->regs[BONITO_MEMSIZE] = 0x10000000; 700 s->regs[BONITO_PCIMAP] = 0x6140; 701 } 702 703 static const VMStateDescription vmstate_bonito = { 704 .name = "Bonito", 705 .version_id = 1, 706 .minimum_version_id = 1, 707 .fields = (VMStateField[]) { 708 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 709 VMSTATE_END_OF_LIST() 710 } 711 }; 712 713 static int bonito_pcihost_initfn(SysBusDevice *dev) 714 { 715 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 716 717 phb->bus = pci_register_bus(DEVICE(dev), "pci", 718 pci_bonito_set_irq, pci_bonito_map_irq, dev, 719 get_system_memory(), get_system_io(), 720 0x28, 32, TYPE_PCI_BUS); 721 722 return 0; 723 } 724 725 static void bonito_realize(PCIDevice *dev, Error **errp) 726 { 727 PCIBonitoState *s = PCI_BONITO(dev); 728 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 729 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 730 731 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ 732 pci_config_set_prog_interface(dev->config, 0x00); 733 734 /* set the north bridge register mapping */ 735 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, 736 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 737 sysbus_init_mmio(sysbus, &s->iomem); 738 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 739 740 /* set the north bridge pci configure mapping */ 741 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, 742 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 743 sysbus_init_mmio(sysbus, &phb->conf_mem); 744 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 745 746 /* set the south bridge pci configure mapping */ 747 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, 748 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 749 sysbus_init_mmio(sysbus, &phb->data_mem); 750 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 751 752 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, 753 "ldma", 0x100); 754 sysbus_init_mmio(sysbus, &s->iomem_ldma); 755 sysbus_mmio_map(sysbus, 3, 0xbfe00200); 756 757 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, 758 "cop", 0x100); 759 sysbus_init_mmio(sysbus, &s->iomem_cop); 760 sysbus_mmio_map(sysbus, 4, 0xbfe00300); 761 762 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 763 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", 764 get_system_io(), 0, BONITO_PCIIO_SIZE); 765 sysbus_init_mmio(sysbus, &s->bonito_pciio); 766 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); 767 768 /* add pci local io mapping */ 769 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio", 770 get_system_io(), 0, BONITO_DEV_SIZE); 771 sysbus_init_mmio(sysbus, &s->bonito_localio); 772 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); 773 774 /* set the default value of north bridge pci config */ 775 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 776 pci_set_word(dev->config + PCI_STATUS, 0x0000); 777 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 778 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 779 780 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 781 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 782 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 783 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 784 785 qemu_register_reset(bonito_reset, s); 786 } 787 788 PCIBus *bonito_init(qemu_irq *pic) 789 { 790 DeviceState *dev; 791 BonitoState *pcihost; 792 PCIHostState *phb; 793 PCIBonitoState *s; 794 PCIDevice *d; 795 796 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 797 phb = PCI_HOST_BRIDGE(dev); 798 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 799 pcihost->pic = pic; 800 qdev_init_nofail(dev); 801 802 /* set the pcihost pointer before bonito_initfn is called */ 803 d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 804 s = PCI_BONITO(d); 805 s->pcihost = pcihost; 806 pcihost->pci_dev = s; 807 qdev_init_nofail(DEVICE(d)); 808 809 return phb->bus; 810 } 811 812 static void bonito_class_init(ObjectClass *klass, void *data) 813 { 814 DeviceClass *dc = DEVICE_CLASS(klass); 815 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 816 817 k->realize = bonito_realize; 818 k->vendor_id = 0xdf53; 819 k->device_id = 0x00d5; 820 k->revision = 0x01; 821 k->class_id = PCI_CLASS_BRIDGE_HOST; 822 dc->desc = "Host bridge"; 823 dc->vmsd = &vmstate_bonito; 824 /* 825 * PCI-facing part of the host bridge, not usable without the 826 * host-facing part, which can't be device_add'ed, yet. 827 */ 828 dc->user_creatable = false; 829 } 830 831 static const TypeInfo bonito_info = { 832 .name = TYPE_PCI_BONITO, 833 .parent = TYPE_PCI_DEVICE, 834 .instance_size = sizeof(PCIBonitoState), 835 .class_init = bonito_class_init, 836 }; 837 838 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 839 { 840 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 841 842 k->init = bonito_pcihost_initfn; 843 } 844 845 static const TypeInfo bonito_pcihost_info = { 846 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 847 .parent = TYPE_PCI_HOST_BRIDGE, 848 .instance_size = sizeof(BonitoState), 849 .class_init = bonito_pcihost_class_init, 850 }; 851 852 static void bonito_register_types(void) 853 { 854 type_register_static(&bonito_pcihost_info); 855 type_register_static(&bonito_info); 856 } 857 858 type_init(bonito_register_types) 859