1a7db759eSPhilippe Mathieu-Daudé /*
2a7db759eSPhilippe Mathieu-Daudé * QEMU GT64120 PCI host
3a7db759eSPhilippe Mathieu-Daudé *
4a7db759eSPhilippe Mathieu-Daudé * Copyright (c) 2006,2007 Aurelien Jarno
5a7db759eSPhilippe Mathieu-Daudé *
6a7db759eSPhilippe Mathieu-Daudé * Permission is hereby granted, free of charge, to any person obtaining a copy
7a7db759eSPhilippe Mathieu-Daudé * of this software and associated documentation files (the "Software"), to deal
8a7db759eSPhilippe Mathieu-Daudé * in the Software without restriction, including without limitation the rights
9a7db759eSPhilippe Mathieu-Daudé * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10a7db759eSPhilippe Mathieu-Daudé * copies of the Software, and to permit persons to whom the Software is
11a7db759eSPhilippe Mathieu-Daudé * furnished to do so, subject to the following conditions:
12a7db759eSPhilippe Mathieu-Daudé *
13a7db759eSPhilippe Mathieu-Daudé * The above copyright notice and this permission notice shall be included in
14a7db759eSPhilippe Mathieu-Daudé * all copies or substantial portions of the Software.
15a7db759eSPhilippe Mathieu-Daudé *
16a7db759eSPhilippe Mathieu-Daudé * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17a7db759eSPhilippe Mathieu-Daudé * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18a7db759eSPhilippe Mathieu-Daudé * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19a7db759eSPhilippe Mathieu-Daudé * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20a7db759eSPhilippe Mathieu-Daudé * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21a7db759eSPhilippe Mathieu-Daudé * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22a7db759eSPhilippe Mathieu-Daudé * THE SOFTWARE.
23a7db759eSPhilippe Mathieu-Daudé */
24a7db759eSPhilippe Mathieu-Daudé
25a7db759eSPhilippe Mathieu-Daudé #include "qemu/osdep.h"
26a7db759eSPhilippe Mathieu-Daudé #include "qapi/error.h"
27a7db759eSPhilippe Mathieu-Daudé #include "qemu/units.h"
28a7db759eSPhilippe Mathieu-Daudé #include "qemu/log.h"
29a7db759eSPhilippe Mathieu-Daudé #include "hw/qdev-properties.h"
30a7db759eSPhilippe Mathieu-Daudé #include "hw/registerfields.h"
31a7db759eSPhilippe Mathieu-Daudé #include "hw/pci/pci_device.h"
32a7db759eSPhilippe Mathieu-Daudé #include "hw/pci/pci_host.h"
33a7db759eSPhilippe Mathieu-Daudé #include "hw/misc/empty_slot.h"
34a7db759eSPhilippe Mathieu-Daudé #include "migration/vmstate.h"
35a7db759eSPhilippe Mathieu-Daudé #include "hw/intc/i8259.h"
36a7db759eSPhilippe Mathieu-Daudé #include "hw/irq.h"
37a7db759eSPhilippe Mathieu-Daudé #include "trace.h"
38a7db759eSPhilippe Mathieu-Daudé #include "qom/object.h"
39a7db759eSPhilippe Mathieu-Daudé
40a7db759eSPhilippe Mathieu-Daudé #define GT_REGS (0x1000 >> 2)
41a7db759eSPhilippe Mathieu-Daudé
42a7db759eSPhilippe Mathieu-Daudé /* CPU Configuration */
43a7db759eSPhilippe Mathieu-Daudé #define GT_CPU (0x000 >> 2)
44a7db759eSPhilippe Mathieu-Daudé #define GT_MULTI (0x120 >> 2)
45a7db759eSPhilippe Mathieu-Daudé
46a7db759eSPhilippe Mathieu-Daudé REG32(GT_CPU, 0x000)
47a7db759eSPhilippe Mathieu-Daudé FIELD(GT_CPU, Endianness, 12, 1)
48a7db759eSPhilippe Mathieu-Daudé
49a7db759eSPhilippe Mathieu-Daudé /* CPU Address Decode */
50a7db759eSPhilippe Mathieu-Daudé #define GT_SCS10LD (0x008 >> 2)
51a7db759eSPhilippe Mathieu-Daudé #define GT_SCS10HD (0x010 >> 2)
52a7db759eSPhilippe Mathieu-Daudé #define GT_SCS32LD (0x018 >> 2)
53a7db759eSPhilippe Mathieu-Daudé #define GT_SCS32HD (0x020 >> 2)
54a7db759eSPhilippe Mathieu-Daudé #define GT_CS20LD (0x028 >> 2)
55a7db759eSPhilippe Mathieu-Daudé #define GT_CS20HD (0x030 >> 2)
56a7db759eSPhilippe Mathieu-Daudé #define GT_CS3BOOTLD (0x038 >> 2)
57a7db759eSPhilippe Mathieu-Daudé #define GT_CS3BOOTHD (0x040 >> 2)
58a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0IOLD (0x048 >> 2)
59a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0IOHD (0x050 >> 2)
60a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M0LD (0x058 >> 2)
61a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M0HD (0x060 >> 2)
62a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M1LD (0x080 >> 2)
63a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M1HD (0x088 >> 2)
64a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1IOLD (0x090 >> 2)
65a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1IOHD (0x098 >> 2)
66a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M0LD (0x0a0 >> 2)
67a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M0HD (0x0a8 >> 2)
68a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M1LD (0x0b0 >> 2)
69a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M1HD (0x0b8 >> 2)
70a7db759eSPhilippe Mathieu-Daudé #define GT_ISD (0x068 >> 2)
71a7db759eSPhilippe Mathieu-Daudé
72a7db759eSPhilippe Mathieu-Daudé #define GT_SCS10AR (0x0d0 >> 2)
73a7db759eSPhilippe Mathieu-Daudé #define GT_SCS32AR (0x0d8 >> 2)
74a7db759eSPhilippe Mathieu-Daudé #define GT_CS20R (0x0e0 >> 2)
75a7db759eSPhilippe Mathieu-Daudé #define GT_CS3BOOTR (0x0e8 >> 2)
76a7db759eSPhilippe Mathieu-Daudé
77a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0IOREMAP (0x0f0 >> 2)
78a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M0REMAP (0x0f8 >> 2)
79a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0M1REMAP (0x100 >> 2)
80a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1IOREMAP (0x108 >> 2)
81a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M0REMAP (0x110 >> 2)
82a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1M1REMAP (0x118 >> 2)
83a7db759eSPhilippe Mathieu-Daudé
84a7db759eSPhilippe Mathieu-Daudé /* CPU Error Report */
85a7db759eSPhilippe Mathieu-Daudé #define GT_CPUERR_ADDRLO (0x070 >> 2)
86a7db759eSPhilippe Mathieu-Daudé #define GT_CPUERR_ADDRHI (0x078 >> 2)
87a7db759eSPhilippe Mathieu-Daudé #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
88a7db759eSPhilippe Mathieu-Daudé #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
89a7db759eSPhilippe Mathieu-Daudé #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
90a7db759eSPhilippe Mathieu-Daudé
91a7db759eSPhilippe Mathieu-Daudé /* CPU Sync Barrier */
92a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0SYNC (0x0c0 >> 2)
93a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1SYNC (0x0c8 >> 2)
94a7db759eSPhilippe Mathieu-Daudé
95a7db759eSPhilippe Mathieu-Daudé /* SDRAM and Device Address Decode */
96a7db759eSPhilippe Mathieu-Daudé #define GT_SCS0LD (0x400 >> 2)
97a7db759eSPhilippe Mathieu-Daudé #define GT_SCS0HD (0x404 >> 2)
98a7db759eSPhilippe Mathieu-Daudé #define GT_SCS1LD (0x408 >> 2)
99a7db759eSPhilippe Mathieu-Daudé #define GT_SCS1HD (0x40c >> 2)
100a7db759eSPhilippe Mathieu-Daudé #define GT_SCS2LD (0x410 >> 2)
101a7db759eSPhilippe Mathieu-Daudé #define GT_SCS2HD (0x414 >> 2)
102a7db759eSPhilippe Mathieu-Daudé #define GT_SCS3LD (0x418 >> 2)
103a7db759eSPhilippe Mathieu-Daudé #define GT_SCS3HD (0x41c >> 2)
104a7db759eSPhilippe Mathieu-Daudé #define GT_CS0LD (0x420 >> 2)
105a7db759eSPhilippe Mathieu-Daudé #define GT_CS0HD (0x424 >> 2)
106a7db759eSPhilippe Mathieu-Daudé #define GT_CS1LD (0x428 >> 2)
107a7db759eSPhilippe Mathieu-Daudé #define GT_CS1HD (0x42c >> 2)
108a7db759eSPhilippe Mathieu-Daudé #define GT_CS2LD (0x430 >> 2)
109a7db759eSPhilippe Mathieu-Daudé #define GT_CS2HD (0x434 >> 2)
110a7db759eSPhilippe Mathieu-Daudé #define GT_CS3LD (0x438 >> 2)
111a7db759eSPhilippe Mathieu-Daudé #define GT_CS3HD (0x43c >> 2)
112a7db759eSPhilippe Mathieu-Daudé #define GT_BOOTLD (0x440 >> 2)
113a7db759eSPhilippe Mathieu-Daudé #define GT_BOOTHD (0x444 >> 2)
114a7db759eSPhilippe Mathieu-Daudé #define GT_ADERR (0x470 >> 2)
115a7db759eSPhilippe Mathieu-Daudé
116a7db759eSPhilippe Mathieu-Daudé /* SDRAM Configuration */
117a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_CFG (0x448 >> 2)
118a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_OPMODE (0x474 >> 2)
119a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_BM (0x478 >> 2)
120a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
121a7db759eSPhilippe Mathieu-Daudé
122a7db759eSPhilippe Mathieu-Daudé /* SDRAM Parameters */
123a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_B0 (0x44c >> 2)
124a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_B1 (0x450 >> 2)
125a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_B2 (0x454 >> 2)
126a7db759eSPhilippe Mathieu-Daudé #define GT_SDRAM_B3 (0x458 >> 2)
127a7db759eSPhilippe Mathieu-Daudé
128a7db759eSPhilippe Mathieu-Daudé /* Device Parameters */
129a7db759eSPhilippe Mathieu-Daudé #define GT_DEV_B0 (0x45c >> 2)
130a7db759eSPhilippe Mathieu-Daudé #define GT_DEV_B1 (0x460 >> 2)
131a7db759eSPhilippe Mathieu-Daudé #define GT_DEV_B2 (0x464 >> 2)
132a7db759eSPhilippe Mathieu-Daudé #define GT_DEV_B3 (0x468 >> 2)
133a7db759eSPhilippe Mathieu-Daudé #define GT_DEV_BOOT (0x46c >> 2)
134a7db759eSPhilippe Mathieu-Daudé
135a7db759eSPhilippe Mathieu-Daudé /* ECC */
136a7db759eSPhilippe Mathieu-Daudé #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
137a7db759eSPhilippe Mathieu-Daudé #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
138a7db759eSPhilippe Mathieu-Daudé #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
139a7db759eSPhilippe Mathieu-Daudé #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
140a7db759eSPhilippe Mathieu-Daudé #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
141a7db759eSPhilippe Mathieu-Daudé
142a7db759eSPhilippe Mathieu-Daudé /* DMA Record */
143a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_CNT (0x800 >> 2)
144a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_CNT (0x804 >> 2)
145a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_CNT (0x808 >> 2)
146a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_CNT (0x80c >> 2)
147a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_SA (0x810 >> 2)
148a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_SA (0x814 >> 2)
149a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_SA (0x818 >> 2)
150a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_SA (0x81c >> 2)
151a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_DA (0x820 >> 2)
152a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_DA (0x824 >> 2)
153a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_DA (0x828 >> 2)
154a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_DA (0x82c >> 2)
155a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_NEXT (0x830 >> 2)
156a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_NEXT (0x834 >> 2)
157a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_NEXT (0x838 >> 2)
158a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_NEXT (0x83c >> 2)
159a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_CUR (0x870 >> 2)
160a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_CUR (0x874 >> 2)
161a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_CUR (0x878 >> 2)
162a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_CUR (0x87c >> 2)
163a7db759eSPhilippe Mathieu-Daudé
164a7db759eSPhilippe Mathieu-Daudé /* DMA Channel Control */
165a7db759eSPhilippe Mathieu-Daudé #define GT_DMA0_CTRL (0x840 >> 2)
166a7db759eSPhilippe Mathieu-Daudé #define GT_DMA1_CTRL (0x844 >> 2)
167a7db759eSPhilippe Mathieu-Daudé #define GT_DMA2_CTRL (0x848 >> 2)
168a7db759eSPhilippe Mathieu-Daudé #define GT_DMA3_CTRL (0x84c >> 2)
169a7db759eSPhilippe Mathieu-Daudé
170a7db759eSPhilippe Mathieu-Daudé /* DMA Arbiter */
171a7db759eSPhilippe Mathieu-Daudé #define GT_DMA_ARB (0x860 >> 2)
172a7db759eSPhilippe Mathieu-Daudé
173a7db759eSPhilippe Mathieu-Daudé /* Timer/Counter */
174a7db759eSPhilippe Mathieu-Daudé #define GT_TC0 (0x850 >> 2)
175a7db759eSPhilippe Mathieu-Daudé #define GT_TC1 (0x854 >> 2)
176a7db759eSPhilippe Mathieu-Daudé #define GT_TC2 (0x858 >> 2)
177a7db759eSPhilippe Mathieu-Daudé #define GT_TC3 (0x85c >> 2)
178a7db759eSPhilippe Mathieu-Daudé #define GT_TC_CONTROL (0x864 >> 2)
179a7db759eSPhilippe Mathieu-Daudé
180a7db759eSPhilippe Mathieu-Daudé /* PCI Internal */
181a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_CMD (0xc00 >> 2)
182a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_TOR (0xc04 >> 2)
183a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
184a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
185a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_BS_CS20 (0xc10 >> 2)
186a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
187a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_IACK (0xc30 >> 2)
188a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_IACK (0xc34 >> 2)
189a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_BARE (0xc3c >> 2)
190a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_PREFMBR (0xc40 >> 2)
191a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
192a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
193a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_CS20_BAR (0xc50 >> 2)
194a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
195a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
196a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
197a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
198a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_CMD (0xc80 >> 2)
199a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_TOR (0xc84 >> 2)
200a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
201a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
202a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_BS_CS20 (0xc90 >> 2)
203a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
204a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_BARE (0xcbc >> 2)
205a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_PREFMBR (0xcc0 >> 2)
206a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
207a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SCS32_BAR (0xccc >> 2)
208a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
209a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
210a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
211a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
212a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
213a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_CFGADDR (0xcf0 >> 2)
214a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_CFGDATA (0xcf4 >> 2)
215a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_CFGADDR (0xcf8 >> 2)
216a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_CFGDATA (0xcfc >> 2)
217a7db759eSPhilippe Mathieu-Daudé
218a7db759eSPhilippe Mathieu-Daudé REG32(GT_PCI0_CMD, 0xc00)
219a7db759eSPhilippe Mathieu-Daudé FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
220a7db759eSPhilippe Mathieu-Daudé FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
221a7db759eSPhilippe Mathieu-Daudé #define R_GT_PCI0_CMD_ByteSwap_MASK \
222a7db759eSPhilippe Mathieu-Daudé (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
223a7db759eSPhilippe Mathieu-Daudé REG32(GT_PCI1_CMD, 0xc80)
224a7db759eSPhilippe Mathieu-Daudé FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
225a7db759eSPhilippe Mathieu-Daudé FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
226a7db759eSPhilippe Mathieu-Daudé #define R_GT_PCI1_CMD_ByteSwap_MASK \
227a7db759eSPhilippe Mathieu-Daudé (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
228a7db759eSPhilippe Mathieu-Daudé
229a7db759eSPhilippe Mathieu-Daudé /* Interrupts */
230a7db759eSPhilippe Mathieu-Daudé #define GT_INTRCAUSE (0xc18 >> 2)
231a7db759eSPhilippe Mathieu-Daudé #define GT_INTRMASK (0xc1c >> 2)
232a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_ICMASK (0xc24 >> 2)
233a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_SERR0MASK (0xc28 >> 2)
234a7db759eSPhilippe Mathieu-Daudé #define GT_CPU_INTSEL (0xc70 >> 2)
235a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_INTSEL (0xc74 >> 2)
236a7db759eSPhilippe Mathieu-Daudé #define GT_HINTRCAUSE (0xc98 >> 2)
237a7db759eSPhilippe Mathieu-Daudé #define GT_HINTRMASK (0xc9c >> 2)
238a7db759eSPhilippe Mathieu-Daudé #define GT_PCI0_HICMASK (0xca4 >> 2)
239a7db759eSPhilippe Mathieu-Daudé #define GT_PCI1_SERR1MASK (0xca8 >> 2)
240a7db759eSPhilippe Mathieu-Daudé
241a7db759eSPhilippe Mathieu-Daudé #define PCI_MAPPING_ENTRY(regname) \
242a7db759eSPhilippe Mathieu-Daudé hwaddr regname ##_start; \
243a7db759eSPhilippe Mathieu-Daudé hwaddr regname ##_length; \
244a7db759eSPhilippe Mathieu-Daudé MemoryRegion regname ##_mem
245a7db759eSPhilippe Mathieu-Daudé
246a7db759eSPhilippe Mathieu-Daudé #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
247a7db759eSPhilippe Mathieu-Daudé
248a7db759eSPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
249a7db759eSPhilippe Mathieu-Daudé
250a7db759eSPhilippe Mathieu-Daudé struct GT64120State {
251a7db759eSPhilippe Mathieu-Daudé PCIHostState parent_obj;
252a7db759eSPhilippe Mathieu-Daudé
253a7db759eSPhilippe Mathieu-Daudé uint32_t regs[GT_REGS];
254a7db759eSPhilippe Mathieu-Daudé PCI_MAPPING_ENTRY(PCI0IO);
255a7db759eSPhilippe Mathieu-Daudé PCI_MAPPING_ENTRY(PCI0M0);
256a7db759eSPhilippe Mathieu-Daudé PCI_MAPPING_ENTRY(PCI0M1);
257a7db759eSPhilippe Mathieu-Daudé PCI_MAPPING_ENTRY(ISD);
258a7db759eSPhilippe Mathieu-Daudé MemoryRegion pci0_mem;
259a7db759eSPhilippe Mathieu-Daudé AddressSpace pci0_mem_as;
260a7db759eSPhilippe Mathieu-Daudé
261a7db759eSPhilippe Mathieu-Daudé /* properties */
262a7db759eSPhilippe Mathieu-Daudé bool cpu_little_endian;
263a7db759eSPhilippe Mathieu-Daudé };
264a7db759eSPhilippe Mathieu-Daudé
265a7db759eSPhilippe Mathieu-Daudé /* Adjust range to avoid touching space which isn't mappable via PCI */
266a7db759eSPhilippe Mathieu-Daudé /*
267a7db759eSPhilippe Mathieu-Daudé * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
268a7db759eSPhilippe Mathieu-Daudé * 0x1fc00000 - 0x1fd00000
269a7db759eSPhilippe Mathieu-Daudé */
check_reserved_space(hwaddr * start,hwaddr * length)270a7db759eSPhilippe Mathieu-Daudé static void check_reserved_space(hwaddr *start, hwaddr *length)
271a7db759eSPhilippe Mathieu-Daudé {
272a7db759eSPhilippe Mathieu-Daudé hwaddr begin = *start;
273a7db759eSPhilippe Mathieu-Daudé hwaddr end = *start + *length;
274a7db759eSPhilippe Mathieu-Daudé
275a7db759eSPhilippe Mathieu-Daudé if (end >= 0x1e000000LL && end < 0x1f100000LL) {
276a7db759eSPhilippe Mathieu-Daudé end = 0x1e000000LL;
277a7db759eSPhilippe Mathieu-Daudé }
278a7db759eSPhilippe Mathieu-Daudé if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
279a7db759eSPhilippe Mathieu-Daudé begin = 0x1f100000LL;
280a7db759eSPhilippe Mathieu-Daudé }
281a7db759eSPhilippe Mathieu-Daudé if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
282a7db759eSPhilippe Mathieu-Daudé end = 0x1fc00000LL;
283a7db759eSPhilippe Mathieu-Daudé }
284a7db759eSPhilippe Mathieu-Daudé if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
285a7db759eSPhilippe Mathieu-Daudé begin = 0x1fd00000LL;
286a7db759eSPhilippe Mathieu-Daudé }
287a7db759eSPhilippe Mathieu-Daudé /* XXX: This is broken when a reserved range splits the requested range */
288a7db759eSPhilippe Mathieu-Daudé if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
289a7db759eSPhilippe Mathieu-Daudé end = 0x1e000000LL;
290a7db759eSPhilippe Mathieu-Daudé }
291a7db759eSPhilippe Mathieu-Daudé if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
292a7db759eSPhilippe Mathieu-Daudé end = 0x1fc00000LL;
293a7db759eSPhilippe Mathieu-Daudé }
294a7db759eSPhilippe Mathieu-Daudé
295a7db759eSPhilippe Mathieu-Daudé *start = begin;
296a7db759eSPhilippe Mathieu-Daudé *length = end - begin;
297a7db759eSPhilippe Mathieu-Daudé }
298a7db759eSPhilippe Mathieu-Daudé
gt64120_isd_mapping(GT64120State * s)299a7db759eSPhilippe Mathieu-Daudé static void gt64120_isd_mapping(GT64120State *s)
300a7db759eSPhilippe Mathieu-Daudé {
301a7db759eSPhilippe Mathieu-Daudé /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
302a7db759eSPhilippe Mathieu-Daudé hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
303a7db759eSPhilippe Mathieu-Daudé hwaddr length = 0x1000;
304a7db759eSPhilippe Mathieu-Daudé
305a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_begin();
306a7db759eSPhilippe Mathieu-Daudé
307a7db759eSPhilippe Mathieu-Daudé if (s->ISD_length) {
308a7db759eSPhilippe Mathieu-Daudé memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
309a7db759eSPhilippe Mathieu-Daudé }
310a7db759eSPhilippe Mathieu-Daudé check_reserved_space(&start, &length);
311a7db759eSPhilippe Mathieu-Daudé length = 0x1000;
312a7db759eSPhilippe Mathieu-Daudé /* Map new address */
313a7db759eSPhilippe Mathieu-Daudé trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
314a7db759eSPhilippe Mathieu-Daudé s->ISD_start = start;
315a7db759eSPhilippe Mathieu-Daudé s->ISD_length = length;
316a7db759eSPhilippe Mathieu-Daudé memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
317a7db759eSPhilippe Mathieu-Daudé
318a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_commit();
319a7db759eSPhilippe Mathieu-Daudé }
320a7db759eSPhilippe Mathieu-Daudé
gt64120_update_pci_cfgdata_mapping(GT64120State * s)321a7db759eSPhilippe Mathieu-Daudé static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
322a7db759eSPhilippe Mathieu-Daudé {
323a7db759eSPhilippe Mathieu-Daudé /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
324a7db759eSPhilippe Mathieu-Daudé static const MemoryRegionOps *pci_host_data_ops[] = {
325a7db759eSPhilippe Mathieu-Daudé &pci_host_data_be_ops, &pci_host_data_le_ops
326a7db759eSPhilippe Mathieu-Daudé };
327a7db759eSPhilippe Mathieu-Daudé PCIHostState *phb = PCI_HOST_BRIDGE(s);
328a7db759eSPhilippe Mathieu-Daudé
329a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_begin();
330a7db759eSPhilippe Mathieu-Daudé
331a7db759eSPhilippe Mathieu-Daudé /*
332a7db759eSPhilippe Mathieu-Daudé * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
333a7db759eSPhilippe Mathieu-Daudé * Command Register determines how data transactions from the CPU to/from
334f1c0cff8SMichael Tokarev * PCI are handled along with the setting of the Endianness bit in the CPU
335a7db759eSPhilippe Mathieu-Daudé * Configuration Register. See:
336f1c0cff8SMichael Tokarev * - Table 16: 32-bit PCI Transaction Endianness
337a7db759eSPhilippe Mathieu-Daudé * - Table 158: PCI_0 Command, Offset: 0xc00
338a7db759eSPhilippe Mathieu-Daudé */
339a7db759eSPhilippe Mathieu-Daudé
340a7db759eSPhilippe Mathieu-Daudé if (memory_region_is_mapped(&phb->data_mem)) {
341a7db759eSPhilippe Mathieu-Daudé memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
342a7db759eSPhilippe Mathieu-Daudé object_unparent(OBJECT(&phb->data_mem));
343a7db759eSPhilippe Mathieu-Daudé }
344a7db759eSPhilippe Mathieu-Daudé memory_region_init_io(&phb->data_mem, OBJECT(phb),
345a7db759eSPhilippe Mathieu-Daudé pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1],
346a7db759eSPhilippe Mathieu-Daudé s, "pci-conf-data", 4);
347a7db759eSPhilippe Mathieu-Daudé memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
348a7db759eSPhilippe Mathieu-Daudé &phb->data_mem, 1);
349a7db759eSPhilippe Mathieu-Daudé
350a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_commit();
351a7db759eSPhilippe Mathieu-Daudé }
352a7db759eSPhilippe Mathieu-Daudé
gt64120_pci_mapping(GT64120State * s)353a7db759eSPhilippe Mathieu-Daudé static void gt64120_pci_mapping(GT64120State *s)
354a7db759eSPhilippe Mathieu-Daudé {
355a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_begin();
356a7db759eSPhilippe Mathieu-Daudé
357a7db759eSPhilippe Mathieu-Daudé /* Update PCI0IO mapping */
358a7db759eSPhilippe Mathieu-Daudé if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
359a7db759eSPhilippe Mathieu-Daudé /* Unmap old IO address */
360a7db759eSPhilippe Mathieu-Daudé if (s->PCI0IO_length) {
361a7db759eSPhilippe Mathieu-Daudé memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
362a7db759eSPhilippe Mathieu-Daudé object_unparent(OBJECT(&s->PCI0IO_mem));
363a7db759eSPhilippe Mathieu-Daudé }
364a7db759eSPhilippe Mathieu-Daudé /* Map new IO address */
365a7db759eSPhilippe Mathieu-Daudé s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
366a7db759eSPhilippe Mathieu-Daudé s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
367a7db759eSPhilippe Mathieu-Daudé (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
368a7db759eSPhilippe Mathieu-Daudé if (s->PCI0IO_length) {
369a7db759eSPhilippe Mathieu-Daudé memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
370a7db759eSPhilippe Mathieu-Daudé get_system_io(), 0, s->PCI0IO_length);
371a7db759eSPhilippe Mathieu-Daudé memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
372a7db759eSPhilippe Mathieu-Daudé &s->PCI0IO_mem);
373a7db759eSPhilippe Mathieu-Daudé }
374a7db759eSPhilippe Mathieu-Daudé }
375a7db759eSPhilippe Mathieu-Daudé
376a7db759eSPhilippe Mathieu-Daudé /* Update PCI0M0 mapping */
377a7db759eSPhilippe Mathieu-Daudé if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
378a7db759eSPhilippe Mathieu-Daudé /* Unmap old MEM address */
379a7db759eSPhilippe Mathieu-Daudé if (s->PCI0M0_length) {
380a7db759eSPhilippe Mathieu-Daudé memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
381a7db759eSPhilippe Mathieu-Daudé object_unparent(OBJECT(&s->PCI0M0_mem));
382a7db759eSPhilippe Mathieu-Daudé }
383a7db759eSPhilippe Mathieu-Daudé /* Map new mem address */
384a7db759eSPhilippe Mathieu-Daudé s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
385a7db759eSPhilippe Mathieu-Daudé s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
386a7db759eSPhilippe Mathieu-Daudé (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
387a7db759eSPhilippe Mathieu-Daudé if (s->PCI0M0_length) {
388a7db759eSPhilippe Mathieu-Daudé memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
389a7db759eSPhilippe Mathieu-Daudé &s->pci0_mem, s->PCI0M0_start,
390a7db759eSPhilippe Mathieu-Daudé s->PCI0M0_length);
391a7db759eSPhilippe Mathieu-Daudé memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
392a7db759eSPhilippe Mathieu-Daudé &s->PCI0M0_mem);
393a7db759eSPhilippe Mathieu-Daudé }
394a7db759eSPhilippe Mathieu-Daudé }
395a7db759eSPhilippe Mathieu-Daudé
396a7db759eSPhilippe Mathieu-Daudé /* Update PCI0M1 mapping */
397a7db759eSPhilippe Mathieu-Daudé if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
398a7db759eSPhilippe Mathieu-Daudé /* Unmap old MEM address */
399a7db759eSPhilippe Mathieu-Daudé if (s->PCI0M1_length) {
400a7db759eSPhilippe Mathieu-Daudé memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
401a7db759eSPhilippe Mathieu-Daudé object_unparent(OBJECT(&s->PCI0M1_mem));
402a7db759eSPhilippe Mathieu-Daudé }
403a7db759eSPhilippe Mathieu-Daudé /* Map new mem address */
404a7db759eSPhilippe Mathieu-Daudé s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
405a7db759eSPhilippe Mathieu-Daudé s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
406a7db759eSPhilippe Mathieu-Daudé (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
407a7db759eSPhilippe Mathieu-Daudé if (s->PCI0M1_length) {
408a7db759eSPhilippe Mathieu-Daudé memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
409a7db759eSPhilippe Mathieu-Daudé &s->pci0_mem, s->PCI0M1_start,
410a7db759eSPhilippe Mathieu-Daudé s->PCI0M1_length);
411a7db759eSPhilippe Mathieu-Daudé memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
412a7db759eSPhilippe Mathieu-Daudé &s->PCI0M1_mem);
413a7db759eSPhilippe Mathieu-Daudé }
414a7db759eSPhilippe Mathieu-Daudé }
415a7db759eSPhilippe Mathieu-Daudé
416a7db759eSPhilippe Mathieu-Daudé memory_region_transaction_commit();
417a7db759eSPhilippe Mathieu-Daudé }
418a7db759eSPhilippe Mathieu-Daudé
gt64120_post_load(void * opaque,int version_id)419a7db759eSPhilippe Mathieu-Daudé static int gt64120_post_load(void *opaque, int version_id)
420a7db759eSPhilippe Mathieu-Daudé {
421a7db759eSPhilippe Mathieu-Daudé GT64120State *s = opaque;
422a7db759eSPhilippe Mathieu-Daudé
423a7db759eSPhilippe Mathieu-Daudé gt64120_isd_mapping(s);
424a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
425a7db759eSPhilippe Mathieu-Daudé
426a7db759eSPhilippe Mathieu-Daudé return 0;
427a7db759eSPhilippe Mathieu-Daudé }
428a7db759eSPhilippe Mathieu-Daudé
429a7db759eSPhilippe Mathieu-Daudé static const VMStateDescription vmstate_gt64120 = {
430a7db759eSPhilippe Mathieu-Daudé .name = "gt64120",
431a7db759eSPhilippe Mathieu-Daudé .version_id = 1,
432a7db759eSPhilippe Mathieu-Daudé .minimum_version_id = 1,
433a7db759eSPhilippe Mathieu-Daudé .post_load = gt64120_post_load,
434*e2bd53a3SRichard Henderson .fields = (const VMStateField[]) {
435a7db759eSPhilippe Mathieu-Daudé VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
436a7db759eSPhilippe Mathieu-Daudé VMSTATE_END_OF_LIST()
437a7db759eSPhilippe Mathieu-Daudé }
438a7db759eSPhilippe Mathieu-Daudé };
439a7db759eSPhilippe Mathieu-Daudé
gt64120_writel(void * opaque,hwaddr addr,uint64_t val,unsigned size)440a7db759eSPhilippe Mathieu-Daudé static void gt64120_writel(void *opaque, hwaddr addr,
441a7db759eSPhilippe Mathieu-Daudé uint64_t val, unsigned size)
442a7db759eSPhilippe Mathieu-Daudé {
443a7db759eSPhilippe Mathieu-Daudé GT64120State *s = opaque;
444a7db759eSPhilippe Mathieu-Daudé uint32_t saddr = addr >> 2;
445a7db759eSPhilippe Mathieu-Daudé
446a7db759eSPhilippe Mathieu-Daudé trace_gt64120_write(addr, val);
447a7db759eSPhilippe Mathieu-Daudé if (!(s->regs[GT_CPU] & 0x00001000)) {
448a7db759eSPhilippe Mathieu-Daudé val = bswap32(val);
449a7db759eSPhilippe Mathieu-Daudé }
450a7db759eSPhilippe Mathieu-Daudé
451a7db759eSPhilippe Mathieu-Daudé switch (saddr) {
452a7db759eSPhilippe Mathieu-Daudé
453a7db759eSPhilippe Mathieu-Daudé /* CPU Configuration */
454a7db759eSPhilippe Mathieu-Daudé case GT_CPU:
455a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPU] = val;
456a7db759eSPhilippe Mathieu-Daudé break;
457a7db759eSPhilippe Mathieu-Daudé case GT_MULTI:
458a7db759eSPhilippe Mathieu-Daudé /* Read-only register as only one GT64xxx is present on the CPU bus */
459a7db759eSPhilippe Mathieu-Daudé break;
460a7db759eSPhilippe Mathieu-Daudé
461a7db759eSPhilippe Mathieu-Daudé /* CPU Address Decode */
462a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOLD:
463a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0IOLD] = val & 0x00007fff;
464a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
465a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
466a7db759eSPhilippe Mathieu-Daudé break;
467a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0LD:
468a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M0LD] = val & 0x00007fff;
469a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
470a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
471a7db759eSPhilippe Mathieu-Daudé break;
472a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1LD:
473a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M1LD] = val & 0x00007fff;
474a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
475a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
476a7db759eSPhilippe Mathieu-Daudé break;
477a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOLD:
478a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1IOLD] = val & 0x00007fff;
479a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
480a7db759eSPhilippe Mathieu-Daudé break;
481a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0LD:
482a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M0LD] = val & 0x00007fff;
483a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
484a7db759eSPhilippe Mathieu-Daudé break;
485a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1LD:
486a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M1LD] = val & 0x00007fff;
487a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
488a7db759eSPhilippe Mathieu-Daudé break;
489a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0HD:
490a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1HD:
491a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOHD:
492a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x0000007f;
493a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
494a7db759eSPhilippe Mathieu-Daudé break;
495a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOHD:
496a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0HD:
497a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1HD:
498a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x0000007f;
499a7db759eSPhilippe Mathieu-Daudé break;
500a7db759eSPhilippe Mathieu-Daudé case GT_ISD:
501a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x00007fff;
502a7db759eSPhilippe Mathieu-Daudé gt64120_isd_mapping(s);
503a7db759eSPhilippe Mathieu-Daudé break;
504a7db759eSPhilippe Mathieu-Daudé
505a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOREMAP:
506a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0REMAP:
507a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1REMAP:
508a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOREMAP:
509a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0REMAP:
510a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1REMAP:
511a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x000007ff;
512a7db759eSPhilippe Mathieu-Daudé break;
513a7db759eSPhilippe Mathieu-Daudé
514a7db759eSPhilippe Mathieu-Daudé /* CPU Error Report */
515a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_ADDRLO:
516a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_ADDRHI:
517a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_DATALO:
518a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_DATAHI:
519a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_PARITY:
520a7db759eSPhilippe Mathieu-Daudé /* Read-only registers, do nothing */
521a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
522a7db759eSPhilippe Mathieu-Daudé "gt64120: Read-only register write "
523a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
524a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
525a7db759eSPhilippe Mathieu-Daudé break;
526a7db759eSPhilippe Mathieu-Daudé
527a7db759eSPhilippe Mathieu-Daudé /* CPU Sync Barrier */
528a7db759eSPhilippe Mathieu-Daudé case GT_PCI0SYNC:
529a7db759eSPhilippe Mathieu-Daudé case GT_PCI1SYNC:
530a7db759eSPhilippe Mathieu-Daudé /* Read-only registers, do nothing */
531a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
532a7db759eSPhilippe Mathieu-Daudé "gt64120: Read-only register write "
533a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
534a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
535a7db759eSPhilippe Mathieu-Daudé break;
536a7db759eSPhilippe Mathieu-Daudé
537a7db759eSPhilippe Mathieu-Daudé /* SDRAM and Device Address Decode */
538a7db759eSPhilippe Mathieu-Daudé case GT_SCS0LD:
539a7db759eSPhilippe Mathieu-Daudé case GT_SCS0HD:
540a7db759eSPhilippe Mathieu-Daudé case GT_SCS1LD:
541a7db759eSPhilippe Mathieu-Daudé case GT_SCS1HD:
542a7db759eSPhilippe Mathieu-Daudé case GT_SCS2LD:
543a7db759eSPhilippe Mathieu-Daudé case GT_SCS2HD:
544a7db759eSPhilippe Mathieu-Daudé case GT_SCS3LD:
545a7db759eSPhilippe Mathieu-Daudé case GT_SCS3HD:
546a7db759eSPhilippe Mathieu-Daudé case GT_CS0LD:
547a7db759eSPhilippe Mathieu-Daudé case GT_CS0HD:
548a7db759eSPhilippe Mathieu-Daudé case GT_CS1LD:
549a7db759eSPhilippe Mathieu-Daudé case GT_CS1HD:
550a7db759eSPhilippe Mathieu-Daudé case GT_CS2LD:
551a7db759eSPhilippe Mathieu-Daudé case GT_CS2HD:
552a7db759eSPhilippe Mathieu-Daudé case GT_CS3LD:
553a7db759eSPhilippe Mathieu-Daudé case GT_CS3HD:
554a7db759eSPhilippe Mathieu-Daudé case GT_BOOTLD:
555a7db759eSPhilippe Mathieu-Daudé case GT_BOOTHD:
556a7db759eSPhilippe Mathieu-Daudé case GT_ADERR:
557a7db759eSPhilippe Mathieu-Daudé /* SDRAM Configuration */
558a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_CFG:
559a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_OPMODE:
560a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_BM:
561a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_ADDRDECODE:
562a7db759eSPhilippe Mathieu-Daudé /* Accept and ignore SDRAM interleave configuration */
563a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val;
564a7db759eSPhilippe Mathieu-Daudé break;
565a7db759eSPhilippe Mathieu-Daudé
566a7db759eSPhilippe Mathieu-Daudé /* Device Parameters */
567a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B0:
568a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B1:
569a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B2:
570a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B3:
571a7db759eSPhilippe Mathieu-Daudé case GT_DEV_BOOT:
572a7db759eSPhilippe Mathieu-Daudé /* Not implemented */
573a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP,
574a7db759eSPhilippe Mathieu-Daudé "gt64120: Unimplemented device register write "
575a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
576a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
577a7db759eSPhilippe Mathieu-Daudé break;
578a7db759eSPhilippe Mathieu-Daudé
579a7db759eSPhilippe Mathieu-Daudé /* ECC */
580a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRDATALO:
581a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRDATAHI:
582a7db759eSPhilippe Mathieu-Daudé case GT_ECC_MEM:
583a7db759eSPhilippe Mathieu-Daudé case GT_ECC_CALC:
584a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRADDR:
585a7db759eSPhilippe Mathieu-Daudé /* Read-only registers, do nothing */
586a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
587a7db759eSPhilippe Mathieu-Daudé "gt64120: Read-only register write "
588a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
589a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
590a7db759eSPhilippe Mathieu-Daudé break;
591a7db759eSPhilippe Mathieu-Daudé
592a7db759eSPhilippe Mathieu-Daudé /* DMA Record */
593a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CNT:
594a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CNT:
595a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CNT:
596a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CNT:
597a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_SA:
598a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_SA:
599a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_SA:
600a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_SA:
601a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_DA:
602a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_DA:
603a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_DA:
604a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_DA:
605a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_NEXT:
606a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_NEXT:
607a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_NEXT:
608a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_NEXT:
609a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CUR:
610a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CUR:
611a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CUR:
612a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CUR:
613a7db759eSPhilippe Mathieu-Daudé
614a7db759eSPhilippe Mathieu-Daudé /* DMA Channel Control */
615a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CTRL:
616a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CTRL:
617a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CTRL:
618a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CTRL:
619a7db759eSPhilippe Mathieu-Daudé
620a7db759eSPhilippe Mathieu-Daudé /* DMA Arbiter */
621a7db759eSPhilippe Mathieu-Daudé case GT_DMA_ARB:
622a7db759eSPhilippe Mathieu-Daudé /* Not implemented */
623a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP,
624a7db759eSPhilippe Mathieu-Daudé "gt64120: Unimplemented DMA register write "
625a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
626a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
627a7db759eSPhilippe Mathieu-Daudé break;
628a7db759eSPhilippe Mathieu-Daudé
629a7db759eSPhilippe Mathieu-Daudé /* Timer/Counter */
630a7db759eSPhilippe Mathieu-Daudé case GT_TC0:
631a7db759eSPhilippe Mathieu-Daudé case GT_TC1:
632a7db759eSPhilippe Mathieu-Daudé case GT_TC2:
633a7db759eSPhilippe Mathieu-Daudé case GT_TC3:
634a7db759eSPhilippe Mathieu-Daudé case GT_TC_CONTROL:
635a7db759eSPhilippe Mathieu-Daudé /* Not implemented */
636a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP,
637a7db759eSPhilippe Mathieu-Daudé "gt64120: Unimplemented timer register write "
638a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
639a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
640a7db759eSPhilippe Mathieu-Daudé break;
641a7db759eSPhilippe Mathieu-Daudé
642a7db759eSPhilippe Mathieu-Daudé /* PCI Internal */
643a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CMD:
644a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CMD:
645a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x0401fc0f;
646a7db759eSPhilippe Mathieu-Daudé gt64120_update_pci_cfgdata_mapping(s);
647a7db759eSPhilippe Mathieu-Daudé break;
648a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_TOR:
649a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_SCS10:
650a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_SCS32:
651a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_CS20:
652a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_CS3BT:
653a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_IACK:
654a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_IACK:
655a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BARE:
656a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_PREFMBR:
657a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS10_BAR:
658a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS32_BAR:
659a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CS20_BAR:
660a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CS3BT_BAR:
661a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SSCS10_BAR:
662a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SSCS32_BAR:
663a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS3BT_BAR:
664a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_TOR:
665a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_SCS10:
666a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_SCS32:
667a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_CS20:
668a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_CS3BT:
669a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BARE:
670a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_PREFMBR:
671a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS10_BAR:
672a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS32_BAR:
673a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CS20_BAR:
674a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CS3BT_BAR:
675a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SSCS10_BAR:
676a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SSCS32_BAR:
677a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS3BT_BAR:
678a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CFGADDR:
679a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CFGDATA:
680a7db759eSPhilippe Mathieu-Daudé /* not implemented */
681a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP,
682a7db759eSPhilippe Mathieu-Daudé "gt64120: Unimplemented PCI register write "
683a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
684a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
685a7db759eSPhilippe Mathieu-Daudé break;
686a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CFGADDR:
687a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CFGDATA:
688a7db759eSPhilippe Mathieu-Daudé /* Mapped via in gt64120_pci_mapping() */
689a7db759eSPhilippe Mathieu-Daudé g_assert_not_reached();
690a7db759eSPhilippe Mathieu-Daudé break;
691a7db759eSPhilippe Mathieu-Daudé
692a7db759eSPhilippe Mathieu-Daudé /* Interrupts */
693a7db759eSPhilippe Mathieu-Daudé case GT_INTRCAUSE:
694a7db759eSPhilippe Mathieu-Daudé /* not really implemented */
695a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
696a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
697a7db759eSPhilippe Mathieu-Daudé trace_gt64120_write_intreg("INTRCAUSE", size, val);
698a7db759eSPhilippe Mathieu-Daudé break;
699a7db759eSPhilippe Mathieu-Daudé case GT_INTRMASK:
700a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x3c3ffffe;
701a7db759eSPhilippe Mathieu-Daudé trace_gt64120_write_intreg("INTRMASK", size, val);
702a7db759eSPhilippe Mathieu-Daudé break;
703a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_ICMASK:
704a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x03fffffe;
705a7db759eSPhilippe Mathieu-Daudé trace_gt64120_write_intreg("ICMASK", size, val);
706a7db759eSPhilippe Mathieu-Daudé break;
707a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SERR0MASK:
708a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val & 0x0000003f;
709a7db759eSPhilippe Mathieu-Daudé trace_gt64120_write_intreg("SERR0MASK", size, val);
710a7db759eSPhilippe Mathieu-Daudé break;
711a7db759eSPhilippe Mathieu-Daudé
712a7db759eSPhilippe Mathieu-Daudé /* Reserved when only PCI_0 is configured. */
713a7db759eSPhilippe Mathieu-Daudé case GT_HINTRCAUSE:
714a7db759eSPhilippe Mathieu-Daudé case GT_CPU_INTSEL:
715a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_INTSEL:
716a7db759eSPhilippe Mathieu-Daudé case GT_HINTRMASK:
717a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_HICMASK:
718a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SERR1MASK:
719a7db759eSPhilippe Mathieu-Daudé /* not implemented */
720a7db759eSPhilippe Mathieu-Daudé break;
721a7db759eSPhilippe Mathieu-Daudé
722a7db759eSPhilippe Mathieu-Daudé /* SDRAM Parameters */
723a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B0:
724a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B1:
725a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B2:
726a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B3:
727a7db759eSPhilippe Mathieu-Daudé /*
728a7db759eSPhilippe Mathieu-Daudé * We don't simulate electrical parameters of the SDRAM.
729a7db759eSPhilippe Mathieu-Daudé * Accept, but ignore the values.
730a7db759eSPhilippe Mathieu-Daudé */
731a7db759eSPhilippe Mathieu-Daudé s->regs[saddr] = val;
732a7db759eSPhilippe Mathieu-Daudé break;
733a7db759eSPhilippe Mathieu-Daudé
734a7db759eSPhilippe Mathieu-Daudé default:
735a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
736a7db759eSPhilippe Mathieu-Daudé "gt64120: Illegal register write "
737a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
738a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
739a7db759eSPhilippe Mathieu-Daudé break;
740a7db759eSPhilippe Mathieu-Daudé }
741a7db759eSPhilippe Mathieu-Daudé }
742a7db759eSPhilippe Mathieu-Daudé
gt64120_readl(void * opaque,hwaddr addr,unsigned size)743a7db759eSPhilippe Mathieu-Daudé static uint64_t gt64120_readl(void *opaque,
744a7db759eSPhilippe Mathieu-Daudé hwaddr addr, unsigned size)
745a7db759eSPhilippe Mathieu-Daudé {
746a7db759eSPhilippe Mathieu-Daudé GT64120State *s = opaque;
747a7db759eSPhilippe Mathieu-Daudé uint32_t val;
748a7db759eSPhilippe Mathieu-Daudé uint32_t saddr = addr >> 2;
749a7db759eSPhilippe Mathieu-Daudé
750a7db759eSPhilippe Mathieu-Daudé switch (saddr) {
751a7db759eSPhilippe Mathieu-Daudé
752a7db759eSPhilippe Mathieu-Daudé /* CPU Configuration */
753a7db759eSPhilippe Mathieu-Daudé case GT_MULTI:
754a7db759eSPhilippe Mathieu-Daudé /*
755a7db759eSPhilippe Mathieu-Daudé * Only one GT64xxx is present on the CPU bus, return
756a7db759eSPhilippe Mathieu-Daudé * the initial value.
757a7db759eSPhilippe Mathieu-Daudé */
758a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
759a7db759eSPhilippe Mathieu-Daudé break;
760a7db759eSPhilippe Mathieu-Daudé
761a7db759eSPhilippe Mathieu-Daudé /* CPU Error Report */
762a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_ADDRLO:
763a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_ADDRHI:
764a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_DATALO:
765a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_DATAHI:
766a7db759eSPhilippe Mathieu-Daudé case GT_CPUERR_PARITY:
767a7db759eSPhilippe Mathieu-Daudé /* Emulated memory has no error, always return the initial values. */
768a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
769a7db759eSPhilippe Mathieu-Daudé break;
770a7db759eSPhilippe Mathieu-Daudé
771a7db759eSPhilippe Mathieu-Daudé /* CPU Sync Barrier */
772a7db759eSPhilippe Mathieu-Daudé case GT_PCI0SYNC:
773a7db759eSPhilippe Mathieu-Daudé case GT_PCI1SYNC:
774a7db759eSPhilippe Mathieu-Daudé /*
775a7db759eSPhilippe Mathieu-Daudé * Reading those register should empty all FIFO on the PCI
776a7db759eSPhilippe Mathieu-Daudé * bus, which are not emulated. The return value should be
777a7db759eSPhilippe Mathieu-Daudé * a random value that should be ignored.
778a7db759eSPhilippe Mathieu-Daudé */
779a7db759eSPhilippe Mathieu-Daudé val = 0xc000ffee;
780a7db759eSPhilippe Mathieu-Daudé break;
781a7db759eSPhilippe Mathieu-Daudé
782a7db759eSPhilippe Mathieu-Daudé /* ECC */
783a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRDATALO:
784a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRDATAHI:
785a7db759eSPhilippe Mathieu-Daudé case GT_ECC_MEM:
786a7db759eSPhilippe Mathieu-Daudé case GT_ECC_CALC:
787a7db759eSPhilippe Mathieu-Daudé case GT_ECC_ERRADDR:
788a7db759eSPhilippe Mathieu-Daudé /* Emulated memory has no error, always return the initial values. */
789a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
790a7db759eSPhilippe Mathieu-Daudé break;
791a7db759eSPhilippe Mathieu-Daudé
792a7db759eSPhilippe Mathieu-Daudé case GT_CPU:
793a7db759eSPhilippe Mathieu-Daudé case GT_SCS10LD:
794a7db759eSPhilippe Mathieu-Daudé case GT_SCS10HD:
795a7db759eSPhilippe Mathieu-Daudé case GT_SCS32LD:
796a7db759eSPhilippe Mathieu-Daudé case GT_SCS32HD:
797a7db759eSPhilippe Mathieu-Daudé case GT_CS20LD:
798a7db759eSPhilippe Mathieu-Daudé case GT_CS20HD:
799a7db759eSPhilippe Mathieu-Daudé case GT_CS3BOOTLD:
800a7db759eSPhilippe Mathieu-Daudé case GT_CS3BOOTHD:
801a7db759eSPhilippe Mathieu-Daudé case GT_SCS10AR:
802a7db759eSPhilippe Mathieu-Daudé case GT_SCS32AR:
803a7db759eSPhilippe Mathieu-Daudé case GT_CS20R:
804a7db759eSPhilippe Mathieu-Daudé case GT_CS3BOOTR:
805a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOLD:
806a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0LD:
807a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1LD:
808a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOLD:
809a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0LD:
810a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1LD:
811a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOHD:
812a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0HD:
813a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1HD:
814a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOHD:
815a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0HD:
816a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1HD:
817a7db759eSPhilippe Mathieu-Daudé case GT_PCI0IOREMAP:
818a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M0REMAP:
819a7db759eSPhilippe Mathieu-Daudé case GT_PCI0M1REMAP:
820a7db759eSPhilippe Mathieu-Daudé case GT_PCI1IOREMAP:
821a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M0REMAP:
822a7db759eSPhilippe Mathieu-Daudé case GT_PCI1M1REMAP:
823a7db759eSPhilippe Mathieu-Daudé case GT_ISD:
824a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
825a7db759eSPhilippe Mathieu-Daudé break;
826a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_IACK:
827a7db759eSPhilippe Mathieu-Daudé /* Read the IRQ number */
828a7db759eSPhilippe Mathieu-Daudé val = pic_read_irq(isa_pic);
829a7db759eSPhilippe Mathieu-Daudé break;
830a7db759eSPhilippe Mathieu-Daudé
831a7db759eSPhilippe Mathieu-Daudé /* SDRAM and Device Address Decode */
832a7db759eSPhilippe Mathieu-Daudé case GT_SCS0LD:
833a7db759eSPhilippe Mathieu-Daudé case GT_SCS0HD:
834a7db759eSPhilippe Mathieu-Daudé case GT_SCS1LD:
835a7db759eSPhilippe Mathieu-Daudé case GT_SCS1HD:
836a7db759eSPhilippe Mathieu-Daudé case GT_SCS2LD:
837a7db759eSPhilippe Mathieu-Daudé case GT_SCS2HD:
838a7db759eSPhilippe Mathieu-Daudé case GT_SCS3LD:
839a7db759eSPhilippe Mathieu-Daudé case GT_SCS3HD:
840a7db759eSPhilippe Mathieu-Daudé case GT_CS0LD:
841a7db759eSPhilippe Mathieu-Daudé case GT_CS0HD:
842a7db759eSPhilippe Mathieu-Daudé case GT_CS1LD:
843a7db759eSPhilippe Mathieu-Daudé case GT_CS1HD:
844a7db759eSPhilippe Mathieu-Daudé case GT_CS2LD:
845a7db759eSPhilippe Mathieu-Daudé case GT_CS2HD:
846a7db759eSPhilippe Mathieu-Daudé case GT_CS3LD:
847a7db759eSPhilippe Mathieu-Daudé case GT_CS3HD:
848a7db759eSPhilippe Mathieu-Daudé case GT_BOOTLD:
849a7db759eSPhilippe Mathieu-Daudé case GT_BOOTHD:
850a7db759eSPhilippe Mathieu-Daudé case GT_ADERR:
851a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
852a7db759eSPhilippe Mathieu-Daudé break;
853a7db759eSPhilippe Mathieu-Daudé
854a7db759eSPhilippe Mathieu-Daudé /* SDRAM Configuration */
855a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_CFG:
856a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_OPMODE:
857a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_BM:
858a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_ADDRDECODE:
859a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
860a7db759eSPhilippe Mathieu-Daudé break;
861a7db759eSPhilippe Mathieu-Daudé
862a7db759eSPhilippe Mathieu-Daudé /* SDRAM Parameters */
863a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B0:
864a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B1:
865a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B2:
866a7db759eSPhilippe Mathieu-Daudé case GT_SDRAM_B3:
867a7db759eSPhilippe Mathieu-Daudé /*
868a7db759eSPhilippe Mathieu-Daudé * We don't simulate electrical parameters of the SDRAM.
869a7db759eSPhilippe Mathieu-Daudé * Just return the last written value.
870a7db759eSPhilippe Mathieu-Daudé */
871a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
872a7db759eSPhilippe Mathieu-Daudé break;
873a7db759eSPhilippe Mathieu-Daudé
874a7db759eSPhilippe Mathieu-Daudé /* Device Parameters */
875a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B0:
876a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B1:
877a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B2:
878a7db759eSPhilippe Mathieu-Daudé case GT_DEV_B3:
879a7db759eSPhilippe Mathieu-Daudé case GT_DEV_BOOT:
880a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
881a7db759eSPhilippe Mathieu-Daudé break;
882a7db759eSPhilippe Mathieu-Daudé
883a7db759eSPhilippe Mathieu-Daudé /* DMA Record */
884a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CNT:
885a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CNT:
886a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CNT:
887a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CNT:
888a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_SA:
889a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_SA:
890a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_SA:
891a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_SA:
892a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_DA:
893a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_DA:
894a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_DA:
895a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_DA:
896a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_NEXT:
897a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_NEXT:
898a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_NEXT:
899a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_NEXT:
900a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CUR:
901a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CUR:
902a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CUR:
903a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CUR:
904a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
905a7db759eSPhilippe Mathieu-Daudé break;
906a7db759eSPhilippe Mathieu-Daudé
907a7db759eSPhilippe Mathieu-Daudé /* DMA Channel Control */
908a7db759eSPhilippe Mathieu-Daudé case GT_DMA0_CTRL:
909a7db759eSPhilippe Mathieu-Daudé case GT_DMA1_CTRL:
910a7db759eSPhilippe Mathieu-Daudé case GT_DMA2_CTRL:
911a7db759eSPhilippe Mathieu-Daudé case GT_DMA3_CTRL:
912a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
913a7db759eSPhilippe Mathieu-Daudé break;
914a7db759eSPhilippe Mathieu-Daudé
915a7db759eSPhilippe Mathieu-Daudé /* DMA Arbiter */
916a7db759eSPhilippe Mathieu-Daudé case GT_DMA_ARB:
917a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
918a7db759eSPhilippe Mathieu-Daudé break;
919a7db759eSPhilippe Mathieu-Daudé
920a7db759eSPhilippe Mathieu-Daudé /* Timer/Counter */
921a7db759eSPhilippe Mathieu-Daudé case GT_TC0:
922a7db759eSPhilippe Mathieu-Daudé case GT_TC1:
923a7db759eSPhilippe Mathieu-Daudé case GT_TC2:
924a7db759eSPhilippe Mathieu-Daudé case GT_TC3:
925a7db759eSPhilippe Mathieu-Daudé case GT_TC_CONTROL:
926a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
927a7db759eSPhilippe Mathieu-Daudé break;
928a7db759eSPhilippe Mathieu-Daudé
929a7db759eSPhilippe Mathieu-Daudé /* PCI Internal */
930a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CFGADDR:
931a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CFGDATA:
932a7db759eSPhilippe Mathieu-Daudé /* Mapped via in gt64120_pci_mapping() */
933a7db759eSPhilippe Mathieu-Daudé g_assert_not_reached();
934a7db759eSPhilippe Mathieu-Daudé break;
935a7db759eSPhilippe Mathieu-Daudé
936a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CMD:
937a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_TOR:
938a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_SCS10:
939a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_SCS32:
940a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_CS20:
941a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BS_CS3BT:
942a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_IACK:
943a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_BARE:
944a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_PREFMBR:
945a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS10_BAR:
946a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS32_BAR:
947a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CS20_BAR:
948a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_CS3BT_BAR:
949a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SSCS10_BAR:
950a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SSCS32_BAR:
951a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SCS3BT_BAR:
952a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CMD:
953a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_TOR:
954a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_SCS10:
955a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_SCS32:
956a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_CS20:
957a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BS_CS3BT:
958a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_BARE:
959a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_PREFMBR:
960a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS10_BAR:
961a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS32_BAR:
962a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CS20_BAR:
963a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CS3BT_BAR:
964a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SSCS10_BAR:
965a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SSCS32_BAR:
966a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SCS3BT_BAR:
967a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CFGADDR:
968a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_CFGDATA:
969a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
970a7db759eSPhilippe Mathieu-Daudé break;
971a7db759eSPhilippe Mathieu-Daudé
972a7db759eSPhilippe Mathieu-Daudé /* Interrupts */
973a7db759eSPhilippe Mathieu-Daudé case GT_INTRCAUSE:
974a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
975a7db759eSPhilippe Mathieu-Daudé trace_gt64120_read_intreg("INTRCAUSE", size, val);
976a7db759eSPhilippe Mathieu-Daudé break;
977a7db759eSPhilippe Mathieu-Daudé case GT_INTRMASK:
978a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
979a7db759eSPhilippe Mathieu-Daudé trace_gt64120_read_intreg("INTRMASK", size, val);
980a7db759eSPhilippe Mathieu-Daudé break;
981a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_ICMASK:
982a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
983a7db759eSPhilippe Mathieu-Daudé trace_gt64120_read_intreg("ICMASK", size, val);
984a7db759eSPhilippe Mathieu-Daudé break;
985a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_SERR0MASK:
986a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
987a7db759eSPhilippe Mathieu-Daudé trace_gt64120_read_intreg("SERR0MASK", size, val);
988a7db759eSPhilippe Mathieu-Daudé break;
989a7db759eSPhilippe Mathieu-Daudé
990a7db759eSPhilippe Mathieu-Daudé /* Reserved when only PCI_0 is configured. */
991a7db759eSPhilippe Mathieu-Daudé case GT_HINTRCAUSE:
992a7db759eSPhilippe Mathieu-Daudé case GT_CPU_INTSEL:
993a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_INTSEL:
994a7db759eSPhilippe Mathieu-Daudé case GT_HINTRMASK:
995a7db759eSPhilippe Mathieu-Daudé case GT_PCI0_HICMASK:
996a7db759eSPhilippe Mathieu-Daudé case GT_PCI1_SERR1MASK:
997a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
998a7db759eSPhilippe Mathieu-Daudé break;
999a7db759eSPhilippe Mathieu-Daudé
1000a7db759eSPhilippe Mathieu-Daudé default:
1001a7db759eSPhilippe Mathieu-Daudé val = s->regs[saddr];
1002a7db759eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR,
1003a7db759eSPhilippe Mathieu-Daudé "gt64120: Illegal register read "
1004a7db759eSPhilippe Mathieu-Daudé "reg:0x%03x size:%u value:0x%0*x\n",
1005a7db759eSPhilippe Mathieu-Daudé saddr << 2, size, size << 1, val);
1006a7db759eSPhilippe Mathieu-Daudé break;
1007a7db759eSPhilippe Mathieu-Daudé }
1008a7db759eSPhilippe Mathieu-Daudé
1009a7db759eSPhilippe Mathieu-Daudé if (!(s->regs[GT_CPU] & 0x00001000)) {
1010a7db759eSPhilippe Mathieu-Daudé val = bswap32(val);
1011a7db759eSPhilippe Mathieu-Daudé }
1012a7db759eSPhilippe Mathieu-Daudé trace_gt64120_read(addr, val);
1013a7db759eSPhilippe Mathieu-Daudé
1014a7db759eSPhilippe Mathieu-Daudé return val;
1015a7db759eSPhilippe Mathieu-Daudé }
1016a7db759eSPhilippe Mathieu-Daudé
1017a7db759eSPhilippe Mathieu-Daudé static const MemoryRegionOps isd_mem_ops = {
1018a7db759eSPhilippe Mathieu-Daudé .read = gt64120_readl,
1019a7db759eSPhilippe Mathieu-Daudé .write = gt64120_writel,
1020a7db759eSPhilippe Mathieu-Daudé .endianness = DEVICE_NATIVE_ENDIAN,
1021a7db759eSPhilippe Mathieu-Daudé .impl = {
1022a7db759eSPhilippe Mathieu-Daudé .min_access_size = 4,
1023a7db759eSPhilippe Mathieu-Daudé .max_access_size = 4,
1024a7db759eSPhilippe Mathieu-Daudé },
1025a7db759eSPhilippe Mathieu-Daudé };
1026a7db759eSPhilippe Mathieu-Daudé
gt64120_reset(DeviceState * dev)1027a7db759eSPhilippe Mathieu-Daudé static void gt64120_reset(DeviceState *dev)
1028a7db759eSPhilippe Mathieu-Daudé {
1029a7db759eSPhilippe Mathieu-Daudé GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1030a7db759eSPhilippe Mathieu-Daudé
1031a7db759eSPhilippe Mathieu-Daudé /* FIXME: Malta specific hw assumptions ahead */
1032a7db759eSPhilippe Mathieu-Daudé
1033a7db759eSPhilippe Mathieu-Daudé /* CPU Configuration */
1034a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
1035a7db759eSPhilippe Mathieu-Daudé s->regs[GT_MULTI] = 0x00000003;
1036a7db759eSPhilippe Mathieu-Daudé
1037a7db759eSPhilippe Mathieu-Daudé /* CPU Address decode */
1038a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS10LD] = 0x00000000;
1039a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS10HD] = 0x00000007;
1040a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS32LD] = 0x00000008;
1041a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS32HD] = 0x0000000f;
1042a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS20LD] = 0x000000e0;
1043a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS20HD] = 0x00000070;
1044a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS3BOOTLD] = 0x000000f8;
1045a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS3BOOTHD] = 0x0000007f;
1046a7db759eSPhilippe Mathieu-Daudé
1047a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0IOLD] = 0x00000080;
1048a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0IOHD] = 0x0000000f;
1049a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M0LD] = 0x00000090;
1050a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M0HD] = 0x0000001f;
1051a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ISD] = 0x000000a0;
1052a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M1LD] = 0x00000790;
1053a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M1HD] = 0x0000001f;
1054a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1IOLD] = 0x00000100;
1055a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1IOHD] = 0x0000000f;
1056a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M0LD] = 0x00000110;
1057a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M0HD] = 0x0000001f;
1058a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M1LD] = 0x00000120;
1059a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M1HD] = 0x0000002f;
1060a7db759eSPhilippe Mathieu-Daudé
1061a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS10AR] = 0x00000000;
1062a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS32AR] = 0x00000008;
1063a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS20R] = 0x000000e0;
1064a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS3BOOTR] = 0x000000f8;
1065a7db759eSPhilippe Mathieu-Daudé
1066a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0IOREMAP] = 0x00000080;
1067a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M0REMAP] = 0x00000090;
1068a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0M1REMAP] = 0x00000790;
1069a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1IOREMAP] = 0x00000100;
1070a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M0REMAP] = 0x00000110;
1071a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1M1REMAP] = 0x00000120;
1072a7db759eSPhilippe Mathieu-Daudé
1073a7db759eSPhilippe Mathieu-Daudé /* CPU Error Report */
1074a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1075a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1076a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1077a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1078a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1079a7db759eSPhilippe Mathieu-Daudé
1080a7db759eSPhilippe Mathieu-Daudé /* CPU Sync Barrier */
1081a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0SYNC] = 0x00000000;
1082a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1SYNC] = 0x00000000;
1083a7db759eSPhilippe Mathieu-Daudé
1084a7db759eSPhilippe Mathieu-Daudé /* SDRAM and Device Address Decode */
1085a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS0LD] = 0x00000000;
1086a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS0HD] = 0x00000007;
1087a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS1LD] = 0x00000008;
1088a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS1HD] = 0x0000000f;
1089a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS2LD] = 0x00000010;
1090a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS2HD] = 0x00000017;
1091a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS3LD] = 0x00000018;
1092a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SCS3HD] = 0x0000001f;
1093a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS0LD] = 0x000000c0;
1094a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS0HD] = 0x000000c7;
1095a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS1LD] = 0x000000c8;
1096a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS1HD] = 0x000000cf;
1097a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS2LD] = 0x000000d0;
1098a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS2HD] = 0x000000df;
1099a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS3LD] = 0x000000f0;
1100a7db759eSPhilippe Mathieu-Daudé s->regs[GT_CS3HD] = 0x000000fb;
1101a7db759eSPhilippe Mathieu-Daudé s->regs[GT_BOOTLD] = 0x000000fc;
1102a7db759eSPhilippe Mathieu-Daudé s->regs[GT_BOOTHD] = 0x000000ff;
1103a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ADERR] = 0xffffffff;
1104a7db759eSPhilippe Mathieu-Daudé
1105a7db759eSPhilippe Mathieu-Daudé /* SDRAM Configuration */
1106a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_CFG] = 0x00000200;
1107a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1108a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_BM] = 0x00000007;
1109a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1110a7db759eSPhilippe Mathieu-Daudé
1111a7db759eSPhilippe Mathieu-Daudé /* SDRAM Parameters */
1112a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_B0] = 0x00000005;
1113a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_B1] = 0x00000005;
1114a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_B2] = 0x00000005;
1115a7db759eSPhilippe Mathieu-Daudé s->regs[GT_SDRAM_B3] = 0x00000005;
1116a7db759eSPhilippe Mathieu-Daudé
1117a7db759eSPhilippe Mathieu-Daudé /* ECC */
1118a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1119a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1120a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ECC_MEM] = 0x00000000;
1121a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ECC_CALC] = 0x00000000;
1122a7db759eSPhilippe Mathieu-Daudé s->regs[GT_ECC_ERRADDR] = 0x00000000;
1123a7db759eSPhilippe Mathieu-Daudé
1124a7db759eSPhilippe Mathieu-Daudé /* Device Parameters */
1125a7db759eSPhilippe Mathieu-Daudé s->regs[GT_DEV_B0] = 0x386fffff;
1126a7db759eSPhilippe Mathieu-Daudé s->regs[GT_DEV_B1] = 0x386fffff;
1127a7db759eSPhilippe Mathieu-Daudé s->regs[GT_DEV_B2] = 0x386fffff;
1128a7db759eSPhilippe Mathieu-Daudé s->regs[GT_DEV_B3] = 0x386fffff;
1129a7db759eSPhilippe Mathieu-Daudé s->regs[GT_DEV_BOOT] = 0x146fffff;
1130a7db759eSPhilippe Mathieu-Daudé
1131a7db759eSPhilippe Mathieu-Daudé /* DMA registers are all zeroed at reset */
1132a7db759eSPhilippe Mathieu-Daudé
1133a7db759eSPhilippe Mathieu-Daudé /* Timer/Counter */
1134a7db759eSPhilippe Mathieu-Daudé s->regs[GT_TC0] = 0xffffffff;
1135a7db759eSPhilippe Mathieu-Daudé s->regs[GT_TC1] = 0x00ffffff;
1136a7db759eSPhilippe Mathieu-Daudé s->regs[GT_TC2] = 0x00ffffff;
1137a7db759eSPhilippe Mathieu-Daudé s->regs[GT_TC3] = 0x00ffffff;
1138a7db759eSPhilippe Mathieu-Daudé s->regs[GT_TC_CONTROL] = 0x00000000;
1139a7db759eSPhilippe Mathieu-Daudé
1140a7db759eSPhilippe Mathieu-Daudé /* PCI Internal */
1141a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
1142a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_TOR] = 0x0000070f;
1143a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1144a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1145a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1146a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1147a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_IACK] = 0x00000000;
1148a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_IACK] = 0x00000000;
1149a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_BARE] = 0x0000000f;
1150a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1151a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1152a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1153a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1154a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1155a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1156a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1157a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1158a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
1159a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_TOR] = 0x0000070f;
1160a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1161a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1162a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1163a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1164a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_BARE] = 0x0000000f;
1165a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1166a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1167a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1168a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1169a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1170a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1171a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1172a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1173a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1174a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1175a7db759eSPhilippe Mathieu-Daudé s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1176a7db759eSPhilippe Mathieu-Daudé
1177a7db759eSPhilippe Mathieu-Daudé /* Interrupt registers are all zeroed at reset */
1178a7db759eSPhilippe Mathieu-Daudé
1179a7db759eSPhilippe Mathieu-Daudé gt64120_isd_mapping(s);
1180a7db759eSPhilippe Mathieu-Daudé gt64120_pci_mapping(s);
1181a7db759eSPhilippe Mathieu-Daudé gt64120_update_pci_cfgdata_mapping(s);
1182a7db759eSPhilippe Mathieu-Daudé }
1183a7db759eSPhilippe Mathieu-Daudé
gt64120_realize(DeviceState * dev,Error ** errp)1184a7db759eSPhilippe Mathieu-Daudé static void gt64120_realize(DeviceState *dev, Error **errp)
1185a7db759eSPhilippe Mathieu-Daudé {
1186a7db759eSPhilippe Mathieu-Daudé GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1187a7db759eSPhilippe Mathieu-Daudé PCIHostState *phb = PCI_HOST_BRIDGE(dev);
1188a7db759eSPhilippe Mathieu-Daudé
1189a7db759eSPhilippe Mathieu-Daudé memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1190a7db759eSPhilippe Mathieu-Daudé "gt64120-isd", 0x1000);
1191a7db759eSPhilippe Mathieu-Daudé memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1192a7db759eSPhilippe Mathieu-Daudé address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
1193a7db759eSPhilippe Mathieu-Daudé phb->bus = pci_root_bus_new(dev, "pci",
1194a7db759eSPhilippe Mathieu-Daudé &s->pci0_mem,
1195a7db759eSPhilippe Mathieu-Daudé get_system_io(),
1196a7db759eSPhilippe Mathieu-Daudé PCI_DEVFN(18, 0), TYPE_PCI_BUS);
1197a7db759eSPhilippe Mathieu-Daudé
1198a7db759eSPhilippe Mathieu-Daudé pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
11993d85c7c1SJiaxun Yang memory_region_init_io(&phb->conf_mem, OBJECT(phb),
12003d85c7c1SJiaxun Yang &pci_host_conf_le_ops,
12013d85c7c1SJiaxun Yang s, "pci-conf-idx", 4);
12023d85c7c1SJiaxun Yang memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
12033d85c7c1SJiaxun Yang &phb->conf_mem, 1);
12043d85c7c1SJiaxun Yang
1205a7db759eSPhilippe Mathieu-Daudé
1206a7db759eSPhilippe Mathieu-Daudé /*
1207a7db759eSPhilippe Mathieu-Daudé * The whole address space decoded by the GT-64120A doesn't generate
1208a7db759eSPhilippe Mathieu-Daudé * exception when accessing invalid memory. Create an empty slot to
1209a7db759eSPhilippe Mathieu-Daudé * emulate this feature.
1210a7db759eSPhilippe Mathieu-Daudé */
1211a7db759eSPhilippe Mathieu-Daudé empty_slot_init("GT64120", 0, 0x20000000);
1212a7db759eSPhilippe Mathieu-Daudé }
1213a7db759eSPhilippe Mathieu-Daudé
gt64120_pci_realize(PCIDevice * d,Error ** errp)1214a7db759eSPhilippe Mathieu-Daudé static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1215a7db759eSPhilippe Mathieu-Daudé {
1216a7db759eSPhilippe Mathieu-Daudé /* FIXME: Malta specific hw assumptions ahead */
1217a7db759eSPhilippe Mathieu-Daudé pci_set_word(d->config + PCI_COMMAND, 0);
1218a7db759eSPhilippe Mathieu-Daudé pci_set_word(d->config + PCI_STATUS,
1219a7db759eSPhilippe Mathieu-Daudé PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1220a7db759eSPhilippe Mathieu-Daudé pci_config_set_prog_interface(d->config, 0);
1221a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1222a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1223a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1224a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1225a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1226a7db759eSPhilippe Mathieu-Daudé pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1227a7db759eSPhilippe Mathieu-Daudé pci_set_byte(d->config + 0x3d, 0x01);
1228a7db759eSPhilippe Mathieu-Daudé }
1229a7db759eSPhilippe Mathieu-Daudé
gt64120_pci_class_init(ObjectClass * klass,void * data)1230a7db759eSPhilippe Mathieu-Daudé static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1231a7db759eSPhilippe Mathieu-Daudé {
1232a7db759eSPhilippe Mathieu-Daudé PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1233a7db759eSPhilippe Mathieu-Daudé DeviceClass *dc = DEVICE_CLASS(klass);
1234a7db759eSPhilippe Mathieu-Daudé
1235a7db759eSPhilippe Mathieu-Daudé k->realize = gt64120_pci_realize;
1236a7db759eSPhilippe Mathieu-Daudé k->vendor_id = PCI_VENDOR_ID_MARVELL;
1237a7db759eSPhilippe Mathieu-Daudé k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1238a7db759eSPhilippe Mathieu-Daudé k->revision = 0x10;
1239a7db759eSPhilippe Mathieu-Daudé k->class_id = PCI_CLASS_BRIDGE_HOST;
1240a7db759eSPhilippe Mathieu-Daudé /*
1241a7db759eSPhilippe Mathieu-Daudé * PCI-facing part of the host bridge, not usable without the
1242a7db759eSPhilippe Mathieu-Daudé * host-facing part, which can't be device_add'ed, yet.
1243a7db759eSPhilippe Mathieu-Daudé */
1244a7db759eSPhilippe Mathieu-Daudé dc->user_creatable = false;
1245a7db759eSPhilippe Mathieu-Daudé }
1246a7db759eSPhilippe Mathieu-Daudé
1247a7db759eSPhilippe Mathieu-Daudé static const TypeInfo gt64120_pci_info = {
1248a7db759eSPhilippe Mathieu-Daudé .name = "gt64120_pci",
1249a7db759eSPhilippe Mathieu-Daudé .parent = TYPE_PCI_DEVICE,
1250a7db759eSPhilippe Mathieu-Daudé .instance_size = sizeof(PCIDevice),
1251a7db759eSPhilippe Mathieu-Daudé .class_init = gt64120_pci_class_init,
1252a7db759eSPhilippe Mathieu-Daudé .interfaces = (InterfaceInfo[]) {
1253a7db759eSPhilippe Mathieu-Daudé { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1254a7db759eSPhilippe Mathieu-Daudé { },
1255a7db759eSPhilippe Mathieu-Daudé },
1256a7db759eSPhilippe Mathieu-Daudé };
1257a7db759eSPhilippe Mathieu-Daudé
1258a7db759eSPhilippe Mathieu-Daudé static Property gt64120_properties[] = {
1259a7db759eSPhilippe Mathieu-Daudé DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
1260a7db759eSPhilippe Mathieu-Daudé cpu_little_endian, false),
1261a7db759eSPhilippe Mathieu-Daudé DEFINE_PROP_END_OF_LIST(),
1262a7db759eSPhilippe Mathieu-Daudé };
1263a7db759eSPhilippe Mathieu-Daudé
gt64120_class_init(ObjectClass * klass,void * data)1264a7db759eSPhilippe Mathieu-Daudé static void gt64120_class_init(ObjectClass *klass, void *data)
1265a7db759eSPhilippe Mathieu-Daudé {
1266a7db759eSPhilippe Mathieu-Daudé DeviceClass *dc = DEVICE_CLASS(klass);
1267a7db759eSPhilippe Mathieu-Daudé
1268a7db759eSPhilippe Mathieu-Daudé set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1269a7db759eSPhilippe Mathieu-Daudé device_class_set_props(dc, gt64120_properties);
1270a7db759eSPhilippe Mathieu-Daudé dc->realize = gt64120_realize;
1271a7db759eSPhilippe Mathieu-Daudé dc->reset = gt64120_reset;
1272a7db759eSPhilippe Mathieu-Daudé dc->vmsd = &vmstate_gt64120;
1273a7db759eSPhilippe Mathieu-Daudé }
1274a7db759eSPhilippe Mathieu-Daudé
1275a7db759eSPhilippe Mathieu-Daudé static const TypeInfo gt64120_info = {
1276a7db759eSPhilippe Mathieu-Daudé .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1277a7db759eSPhilippe Mathieu-Daudé .parent = TYPE_PCI_HOST_BRIDGE,
1278a7db759eSPhilippe Mathieu-Daudé .instance_size = sizeof(GT64120State),
1279a7db759eSPhilippe Mathieu-Daudé .class_init = gt64120_class_init,
1280a7db759eSPhilippe Mathieu-Daudé };
1281a7db759eSPhilippe Mathieu-Daudé
gt64120_pci_register_types(void)1282a7db759eSPhilippe Mathieu-Daudé static void gt64120_pci_register_types(void)
1283a7db759eSPhilippe Mathieu-Daudé {
1284a7db759eSPhilippe Mathieu-Daudé type_register_static(>64120_info);
1285a7db759eSPhilippe Mathieu-Daudé type_register_static(>64120_pci_info);
1286a7db759eSPhilippe Mathieu-Daudé }
1287a7db759eSPhilippe Mathieu-Daudé
1288a7db759eSPhilippe Mathieu-Daudé type_init(gt64120_pci_register_types)
1289