1 /* 2 * QEMU GT64120 PCI host 3 * 4 * Copyright (c) 2006,2007 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/units.h" 28 #include "qemu/log.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/registerfields.h" 31 #include "hw/pci/pci_device.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/misc/empty_slot.h" 34 #include "migration/vmstate.h" 35 #include "hw/intc/i8259.h" 36 #include "hw/irq.h" 37 #include "trace.h" 38 #include "qom/object.h" 39 40 #define GT_REGS (0x1000 >> 2) 41 42 /* CPU Configuration */ 43 #define GT_CPU (0x000 >> 2) 44 #define GT_MULTI (0x120 >> 2) 45 46 REG32(GT_CPU, 0x000) 47 FIELD(GT_CPU, Endianness, 12, 1) 48 49 /* CPU Address Decode */ 50 #define GT_SCS10LD (0x008 >> 2) 51 #define GT_SCS10HD (0x010 >> 2) 52 #define GT_SCS32LD (0x018 >> 2) 53 #define GT_SCS32HD (0x020 >> 2) 54 #define GT_CS20LD (0x028 >> 2) 55 #define GT_CS20HD (0x030 >> 2) 56 #define GT_CS3BOOTLD (0x038 >> 2) 57 #define GT_CS3BOOTHD (0x040 >> 2) 58 #define GT_PCI0IOLD (0x048 >> 2) 59 #define GT_PCI0IOHD (0x050 >> 2) 60 #define GT_PCI0M0LD (0x058 >> 2) 61 #define GT_PCI0M0HD (0x060 >> 2) 62 #define GT_PCI0M1LD (0x080 >> 2) 63 #define GT_PCI0M1HD (0x088 >> 2) 64 #define GT_PCI1IOLD (0x090 >> 2) 65 #define GT_PCI1IOHD (0x098 >> 2) 66 #define GT_PCI1M0LD (0x0a0 >> 2) 67 #define GT_PCI1M0HD (0x0a8 >> 2) 68 #define GT_PCI1M1LD (0x0b0 >> 2) 69 #define GT_PCI1M1HD (0x0b8 >> 2) 70 #define GT_ISD (0x068 >> 2) 71 72 #define GT_SCS10AR (0x0d0 >> 2) 73 #define GT_SCS32AR (0x0d8 >> 2) 74 #define GT_CS20R (0x0e0 >> 2) 75 #define GT_CS3BOOTR (0x0e8 >> 2) 76 77 #define GT_PCI0IOREMAP (0x0f0 >> 2) 78 #define GT_PCI0M0REMAP (0x0f8 >> 2) 79 #define GT_PCI0M1REMAP (0x100 >> 2) 80 #define GT_PCI1IOREMAP (0x108 >> 2) 81 #define GT_PCI1M0REMAP (0x110 >> 2) 82 #define GT_PCI1M1REMAP (0x118 >> 2) 83 84 /* CPU Error Report */ 85 #define GT_CPUERR_ADDRLO (0x070 >> 2) 86 #define GT_CPUERR_ADDRHI (0x078 >> 2) 87 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ 88 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ 89 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ 90 91 /* CPU Sync Barrier */ 92 #define GT_PCI0SYNC (0x0c0 >> 2) 93 #define GT_PCI1SYNC (0x0c8 >> 2) 94 95 /* SDRAM and Device Address Decode */ 96 #define GT_SCS0LD (0x400 >> 2) 97 #define GT_SCS0HD (0x404 >> 2) 98 #define GT_SCS1LD (0x408 >> 2) 99 #define GT_SCS1HD (0x40c >> 2) 100 #define GT_SCS2LD (0x410 >> 2) 101 #define GT_SCS2HD (0x414 >> 2) 102 #define GT_SCS3LD (0x418 >> 2) 103 #define GT_SCS3HD (0x41c >> 2) 104 #define GT_CS0LD (0x420 >> 2) 105 #define GT_CS0HD (0x424 >> 2) 106 #define GT_CS1LD (0x428 >> 2) 107 #define GT_CS1HD (0x42c >> 2) 108 #define GT_CS2LD (0x430 >> 2) 109 #define GT_CS2HD (0x434 >> 2) 110 #define GT_CS3LD (0x438 >> 2) 111 #define GT_CS3HD (0x43c >> 2) 112 #define GT_BOOTLD (0x440 >> 2) 113 #define GT_BOOTHD (0x444 >> 2) 114 #define GT_ADERR (0x470 >> 2) 115 116 /* SDRAM Configuration */ 117 #define GT_SDRAM_CFG (0x448 >> 2) 118 #define GT_SDRAM_OPMODE (0x474 >> 2) 119 #define GT_SDRAM_BM (0x478 >> 2) 120 #define GT_SDRAM_ADDRDECODE (0x47c >> 2) 121 122 /* SDRAM Parameters */ 123 #define GT_SDRAM_B0 (0x44c >> 2) 124 #define GT_SDRAM_B1 (0x450 >> 2) 125 #define GT_SDRAM_B2 (0x454 >> 2) 126 #define GT_SDRAM_B3 (0x458 >> 2) 127 128 /* Device Parameters */ 129 #define GT_DEV_B0 (0x45c >> 2) 130 #define GT_DEV_B1 (0x460 >> 2) 131 #define GT_DEV_B2 (0x464 >> 2) 132 #define GT_DEV_B3 (0x468 >> 2) 133 #define GT_DEV_BOOT (0x46c >> 2) 134 135 /* ECC */ 136 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ 137 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ 138 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ 139 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ 140 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ 141 142 /* DMA Record */ 143 #define GT_DMA0_CNT (0x800 >> 2) 144 #define GT_DMA1_CNT (0x804 >> 2) 145 #define GT_DMA2_CNT (0x808 >> 2) 146 #define GT_DMA3_CNT (0x80c >> 2) 147 #define GT_DMA0_SA (0x810 >> 2) 148 #define GT_DMA1_SA (0x814 >> 2) 149 #define GT_DMA2_SA (0x818 >> 2) 150 #define GT_DMA3_SA (0x81c >> 2) 151 #define GT_DMA0_DA (0x820 >> 2) 152 #define GT_DMA1_DA (0x824 >> 2) 153 #define GT_DMA2_DA (0x828 >> 2) 154 #define GT_DMA3_DA (0x82c >> 2) 155 #define GT_DMA0_NEXT (0x830 >> 2) 156 #define GT_DMA1_NEXT (0x834 >> 2) 157 #define GT_DMA2_NEXT (0x838 >> 2) 158 #define GT_DMA3_NEXT (0x83c >> 2) 159 #define GT_DMA0_CUR (0x870 >> 2) 160 #define GT_DMA1_CUR (0x874 >> 2) 161 #define GT_DMA2_CUR (0x878 >> 2) 162 #define GT_DMA3_CUR (0x87c >> 2) 163 164 /* DMA Channel Control */ 165 #define GT_DMA0_CTRL (0x840 >> 2) 166 #define GT_DMA1_CTRL (0x844 >> 2) 167 #define GT_DMA2_CTRL (0x848 >> 2) 168 #define GT_DMA3_CTRL (0x84c >> 2) 169 170 /* DMA Arbiter */ 171 #define GT_DMA_ARB (0x860 >> 2) 172 173 /* Timer/Counter */ 174 #define GT_TC0 (0x850 >> 2) 175 #define GT_TC1 (0x854 >> 2) 176 #define GT_TC2 (0x858 >> 2) 177 #define GT_TC3 (0x85c >> 2) 178 #define GT_TC_CONTROL (0x864 >> 2) 179 180 /* PCI Internal */ 181 #define GT_PCI0_CMD (0xc00 >> 2) 182 #define GT_PCI0_TOR (0xc04 >> 2) 183 #define GT_PCI0_BS_SCS10 (0xc08 >> 2) 184 #define GT_PCI0_BS_SCS32 (0xc0c >> 2) 185 #define GT_PCI0_BS_CS20 (0xc10 >> 2) 186 #define GT_PCI0_BS_CS3BT (0xc14 >> 2) 187 #define GT_PCI1_IACK (0xc30 >> 2) 188 #define GT_PCI0_IACK (0xc34 >> 2) 189 #define GT_PCI0_BARE (0xc3c >> 2) 190 #define GT_PCI0_PREFMBR (0xc40 >> 2) 191 #define GT_PCI0_SCS10_BAR (0xc48 >> 2) 192 #define GT_PCI0_SCS32_BAR (0xc4c >> 2) 193 #define GT_PCI0_CS20_BAR (0xc50 >> 2) 194 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) 195 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) 196 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) 197 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) 198 #define GT_PCI1_CMD (0xc80 >> 2) 199 #define GT_PCI1_TOR (0xc84 >> 2) 200 #define GT_PCI1_BS_SCS10 (0xc88 >> 2) 201 #define GT_PCI1_BS_SCS32 (0xc8c >> 2) 202 #define GT_PCI1_BS_CS20 (0xc90 >> 2) 203 #define GT_PCI1_BS_CS3BT (0xc94 >> 2) 204 #define GT_PCI1_BARE (0xcbc >> 2) 205 #define GT_PCI1_PREFMBR (0xcc0 >> 2) 206 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) 207 #define GT_PCI1_SCS32_BAR (0xccc >> 2) 208 #define GT_PCI1_CS20_BAR (0xcd0 >> 2) 209 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) 210 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) 211 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) 212 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) 213 #define GT_PCI1_CFGADDR (0xcf0 >> 2) 214 #define GT_PCI1_CFGDATA (0xcf4 >> 2) 215 #define GT_PCI0_CFGADDR (0xcf8 >> 2) 216 #define GT_PCI0_CFGDATA (0xcfc >> 2) 217 218 REG32(GT_PCI0_CMD, 0xc00) 219 FIELD(GT_PCI0_CMD, MByteSwap, 0, 1) 220 FIELD(GT_PCI0_CMD, SByteSwap, 16, 1) 221 #define R_GT_PCI0_CMD_ByteSwap_MASK \ 222 (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK) 223 REG32(GT_PCI1_CMD, 0xc80) 224 FIELD(GT_PCI1_CMD, MByteSwap, 0, 1) 225 FIELD(GT_PCI1_CMD, SByteSwap, 16, 1) 226 #define R_GT_PCI1_CMD_ByteSwap_MASK \ 227 (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK) 228 229 /* Interrupts */ 230 #define GT_INTRCAUSE (0xc18 >> 2) 231 #define GT_INTRMASK (0xc1c >> 2) 232 #define GT_PCI0_ICMASK (0xc24 >> 2) 233 #define GT_PCI0_SERR0MASK (0xc28 >> 2) 234 #define GT_CPU_INTSEL (0xc70 >> 2) 235 #define GT_PCI0_INTSEL (0xc74 >> 2) 236 #define GT_HINTRCAUSE (0xc98 >> 2) 237 #define GT_HINTRMASK (0xc9c >> 2) 238 #define GT_PCI0_HICMASK (0xca4 >> 2) 239 #define GT_PCI1_SERR1MASK (0xca8 >> 2) 240 241 #define PCI_MAPPING_ENTRY(regname) \ 242 hwaddr regname ##_start; \ 243 hwaddr regname ##_length; \ 244 MemoryRegion regname ##_mem 245 246 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" 247 248 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE) 249 250 struct GT64120State { 251 PCIHostState parent_obj; 252 253 uint32_t regs[GT_REGS]; 254 PCI_MAPPING_ENTRY(PCI0IO); 255 PCI_MAPPING_ENTRY(PCI0M0); 256 PCI_MAPPING_ENTRY(PCI0M1); 257 PCI_MAPPING_ENTRY(ISD); 258 MemoryRegion pci0_mem; 259 AddressSpace pci0_mem_as; 260 261 /* properties */ 262 bool cpu_little_endian; 263 }; 264 265 /* Adjust range to avoid touching space which isn't mappable via PCI */ 266 /* 267 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 268 * 0x1fc00000 - 0x1fd00000 269 */ 270 static void check_reserved_space(hwaddr *start, hwaddr *length) 271 { 272 hwaddr begin = *start; 273 hwaddr end = *start + *length; 274 275 if (end >= 0x1e000000LL && end < 0x1f100000LL) { 276 end = 0x1e000000LL; 277 } 278 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { 279 begin = 0x1f100000LL; 280 } 281 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { 282 end = 0x1fc00000LL; 283 } 284 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { 285 begin = 0x1fd00000LL; 286 } 287 /* XXX: This is broken when a reserved range splits the requested range */ 288 if (end >= 0x1f100000LL && begin < 0x1e000000LL) { 289 end = 0x1e000000LL; 290 } 291 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { 292 end = 0x1fc00000LL; 293 } 294 295 *start = begin; 296 *length = end - begin; 297 } 298 299 static void gt64120_isd_mapping(GT64120State *s) 300 { 301 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ 302 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; 303 hwaddr length = 0x1000; 304 305 memory_region_transaction_begin(); 306 307 if (s->ISD_length) { 308 memory_region_del_subregion(get_system_memory(), &s->ISD_mem); 309 } 310 check_reserved_space(&start, &length); 311 length = 0x1000; 312 /* Map new address */ 313 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); 314 s->ISD_start = start; 315 s->ISD_length = length; 316 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); 317 318 memory_region_transaction_commit(); 319 } 320 321 static void gt64120_update_pci_cfgdata_mapping(GT64120State *s) 322 { 323 /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */ 324 static const MemoryRegionOps *pci_host_conf_ops[] = { 325 &pci_host_conf_be_ops, &pci_host_conf_le_ops 326 }; 327 static const MemoryRegionOps *pci_host_data_ops[] = { 328 &pci_host_data_be_ops, &pci_host_data_le_ops 329 }; 330 PCIHostState *phb = PCI_HOST_BRIDGE(s); 331 332 memory_region_transaction_begin(); 333 334 /* 335 * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal 336 * Command Register determines how data transactions from the CPU to/from 337 * PCI are handled along with the setting of the Endianess bit in the CPU 338 * Configuration Register. See: 339 * - Table 16: 32-bit PCI Transaction Endianess 340 * - Table 158: PCI_0 Command, Offset: 0xc00 341 */ 342 if (memory_region_is_mapped(&phb->conf_mem)) { 343 memory_region_del_subregion(&s->ISD_mem, &phb->conf_mem); 344 object_unparent(OBJECT(&phb->conf_mem)); 345 } 346 memory_region_init_io(&phb->conf_mem, OBJECT(phb), 347 pci_host_conf_ops[s->regs[GT_PCI0_CMD] & 1], 348 s, "pci-conf-idx", 4); 349 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2, 350 &phb->conf_mem, 1); 351 352 if (memory_region_is_mapped(&phb->data_mem)) { 353 memory_region_del_subregion(&s->ISD_mem, &phb->data_mem); 354 object_unparent(OBJECT(&phb->data_mem)); 355 } 356 memory_region_init_io(&phb->data_mem, OBJECT(phb), 357 pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1], 358 s, "pci-conf-data", 4); 359 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2, 360 &phb->data_mem, 1); 361 362 memory_region_transaction_commit(); 363 } 364 365 static void gt64120_pci_mapping(GT64120State *s) 366 { 367 memory_region_transaction_begin(); 368 369 /* Update PCI0IO mapping */ 370 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { 371 /* Unmap old IO address */ 372 if (s->PCI0IO_length) { 373 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); 374 object_unparent(OBJECT(&s->PCI0IO_mem)); 375 } 376 /* Map new IO address */ 377 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; 378 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - 379 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; 380 if (s->PCI0IO_length) { 381 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", 382 get_system_io(), 0, s->PCI0IO_length); 383 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, 384 &s->PCI0IO_mem); 385 } 386 } 387 388 /* Update PCI0M0 mapping */ 389 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { 390 /* Unmap old MEM address */ 391 if (s->PCI0M0_length) { 392 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem); 393 object_unparent(OBJECT(&s->PCI0M0_mem)); 394 } 395 /* Map new mem address */ 396 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21; 397 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) - 398 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; 399 if (s->PCI0M0_length) { 400 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0", 401 &s->pci0_mem, s->PCI0M0_start, 402 s->PCI0M0_length); 403 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start, 404 &s->PCI0M0_mem); 405 } 406 } 407 408 /* Update PCI0M1 mapping */ 409 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { 410 /* Unmap old MEM address */ 411 if (s->PCI0M1_length) { 412 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem); 413 object_unparent(OBJECT(&s->PCI0M1_mem)); 414 } 415 /* Map new mem address */ 416 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21; 417 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) - 418 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; 419 if (s->PCI0M1_length) { 420 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1", 421 &s->pci0_mem, s->PCI0M1_start, 422 s->PCI0M1_length); 423 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start, 424 &s->PCI0M1_mem); 425 } 426 } 427 428 memory_region_transaction_commit(); 429 } 430 431 static int gt64120_post_load(void *opaque, int version_id) 432 { 433 GT64120State *s = opaque; 434 435 gt64120_isd_mapping(s); 436 gt64120_pci_mapping(s); 437 438 return 0; 439 } 440 441 static const VMStateDescription vmstate_gt64120 = { 442 .name = "gt64120", 443 .version_id = 1, 444 .minimum_version_id = 1, 445 .post_load = gt64120_post_load, 446 .fields = (VMStateField[]) { 447 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS), 448 VMSTATE_END_OF_LIST() 449 } 450 }; 451 452 static void gt64120_writel(void *opaque, hwaddr addr, 453 uint64_t val, unsigned size) 454 { 455 GT64120State *s = opaque; 456 uint32_t saddr = addr >> 2; 457 458 trace_gt64120_write(addr, val); 459 if (!(s->regs[GT_CPU] & 0x00001000)) { 460 val = bswap32(val); 461 } 462 463 switch (saddr) { 464 465 /* CPU Configuration */ 466 case GT_CPU: 467 s->regs[GT_CPU] = val; 468 break; 469 case GT_MULTI: 470 /* Read-only register as only one GT64xxx is present on the CPU bus */ 471 break; 472 473 /* CPU Address Decode */ 474 case GT_PCI0IOLD: 475 s->regs[GT_PCI0IOLD] = val & 0x00007fff; 476 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; 477 gt64120_pci_mapping(s); 478 break; 479 case GT_PCI0M0LD: 480 s->regs[GT_PCI0M0LD] = val & 0x00007fff; 481 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; 482 gt64120_pci_mapping(s); 483 break; 484 case GT_PCI0M1LD: 485 s->regs[GT_PCI0M1LD] = val & 0x00007fff; 486 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; 487 gt64120_pci_mapping(s); 488 break; 489 case GT_PCI1IOLD: 490 s->regs[GT_PCI1IOLD] = val & 0x00007fff; 491 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; 492 break; 493 case GT_PCI1M0LD: 494 s->regs[GT_PCI1M0LD] = val & 0x00007fff; 495 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; 496 break; 497 case GT_PCI1M1LD: 498 s->regs[GT_PCI1M1LD] = val & 0x00007fff; 499 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; 500 break; 501 case GT_PCI0M0HD: 502 case GT_PCI0M1HD: 503 case GT_PCI0IOHD: 504 s->regs[saddr] = val & 0x0000007f; 505 gt64120_pci_mapping(s); 506 break; 507 case GT_PCI1IOHD: 508 case GT_PCI1M0HD: 509 case GT_PCI1M1HD: 510 s->regs[saddr] = val & 0x0000007f; 511 break; 512 case GT_ISD: 513 s->regs[saddr] = val & 0x00007fff; 514 gt64120_isd_mapping(s); 515 break; 516 517 case GT_PCI0IOREMAP: 518 case GT_PCI0M0REMAP: 519 case GT_PCI0M1REMAP: 520 case GT_PCI1IOREMAP: 521 case GT_PCI1M0REMAP: 522 case GT_PCI1M1REMAP: 523 s->regs[saddr] = val & 0x000007ff; 524 break; 525 526 /* CPU Error Report */ 527 case GT_CPUERR_ADDRLO: 528 case GT_CPUERR_ADDRHI: 529 case GT_CPUERR_DATALO: 530 case GT_CPUERR_DATAHI: 531 case GT_CPUERR_PARITY: 532 /* Read-only registers, do nothing */ 533 qemu_log_mask(LOG_GUEST_ERROR, 534 "gt64120: Read-only register write " 535 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 536 saddr << 2, size, size << 1, val); 537 break; 538 539 /* CPU Sync Barrier */ 540 case GT_PCI0SYNC: 541 case GT_PCI1SYNC: 542 /* Read-only registers, do nothing */ 543 qemu_log_mask(LOG_GUEST_ERROR, 544 "gt64120: Read-only register write " 545 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 546 saddr << 2, size, size << 1, val); 547 break; 548 549 /* SDRAM and Device Address Decode */ 550 case GT_SCS0LD: 551 case GT_SCS0HD: 552 case GT_SCS1LD: 553 case GT_SCS1HD: 554 case GT_SCS2LD: 555 case GT_SCS2HD: 556 case GT_SCS3LD: 557 case GT_SCS3HD: 558 case GT_CS0LD: 559 case GT_CS0HD: 560 case GT_CS1LD: 561 case GT_CS1HD: 562 case GT_CS2LD: 563 case GT_CS2HD: 564 case GT_CS3LD: 565 case GT_CS3HD: 566 case GT_BOOTLD: 567 case GT_BOOTHD: 568 case GT_ADERR: 569 /* SDRAM Configuration */ 570 case GT_SDRAM_CFG: 571 case GT_SDRAM_OPMODE: 572 case GT_SDRAM_BM: 573 case GT_SDRAM_ADDRDECODE: 574 /* Accept and ignore SDRAM interleave configuration */ 575 s->regs[saddr] = val; 576 break; 577 578 /* Device Parameters */ 579 case GT_DEV_B0: 580 case GT_DEV_B1: 581 case GT_DEV_B2: 582 case GT_DEV_B3: 583 case GT_DEV_BOOT: 584 /* Not implemented */ 585 qemu_log_mask(LOG_UNIMP, 586 "gt64120: Unimplemented device register write " 587 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 588 saddr << 2, size, size << 1, val); 589 break; 590 591 /* ECC */ 592 case GT_ECC_ERRDATALO: 593 case GT_ECC_ERRDATAHI: 594 case GT_ECC_MEM: 595 case GT_ECC_CALC: 596 case GT_ECC_ERRADDR: 597 /* Read-only registers, do nothing */ 598 qemu_log_mask(LOG_GUEST_ERROR, 599 "gt64120: Read-only register write " 600 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 601 saddr << 2, size, size << 1, val); 602 break; 603 604 /* DMA Record */ 605 case GT_DMA0_CNT: 606 case GT_DMA1_CNT: 607 case GT_DMA2_CNT: 608 case GT_DMA3_CNT: 609 case GT_DMA0_SA: 610 case GT_DMA1_SA: 611 case GT_DMA2_SA: 612 case GT_DMA3_SA: 613 case GT_DMA0_DA: 614 case GT_DMA1_DA: 615 case GT_DMA2_DA: 616 case GT_DMA3_DA: 617 case GT_DMA0_NEXT: 618 case GT_DMA1_NEXT: 619 case GT_DMA2_NEXT: 620 case GT_DMA3_NEXT: 621 case GT_DMA0_CUR: 622 case GT_DMA1_CUR: 623 case GT_DMA2_CUR: 624 case GT_DMA3_CUR: 625 626 /* DMA Channel Control */ 627 case GT_DMA0_CTRL: 628 case GT_DMA1_CTRL: 629 case GT_DMA2_CTRL: 630 case GT_DMA3_CTRL: 631 632 /* DMA Arbiter */ 633 case GT_DMA_ARB: 634 /* Not implemented */ 635 qemu_log_mask(LOG_UNIMP, 636 "gt64120: Unimplemented DMA register write " 637 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 638 saddr << 2, size, size << 1, val); 639 break; 640 641 /* Timer/Counter */ 642 case GT_TC0: 643 case GT_TC1: 644 case GT_TC2: 645 case GT_TC3: 646 case GT_TC_CONTROL: 647 /* Not implemented */ 648 qemu_log_mask(LOG_UNIMP, 649 "gt64120: Unimplemented timer register write " 650 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 651 saddr << 2, size, size << 1, val); 652 break; 653 654 /* PCI Internal */ 655 case GT_PCI0_CMD: 656 case GT_PCI1_CMD: 657 s->regs[saddr] = val & 0x0401fc0f; 658 gt64120_update_pci_cfgdata_mapping(s); 659 break; 660 case GT_PCI0_TOR: 661 case GT_PCI0_BS_SCS10: 662 case GT_PCI0_BS_SCS32: 663 case GT_PCI0_BS_CS20: 664 case GT_PCI0_BS_CS3BT: 665 case GT_PCI1_IACK: 666 case GT_PCI0_IACK: 667 case GT_PCI0_BARE: 668 case GT_PCI0_PREFMBR: 669 case GT_PCI0_SCS10_BAR: 670 case GT_PCI0_SCS32_BAR: 671 case GT_PCI0_CS20_BAR: 672 case GT_PCI0_CS3BT_BAR: 673 case GT_PCI0_SSCS10_BAR: 674 case GT_PCI0_SSCS32_BAR: 675 case GT_PCI0_SCS3BT_BAR: 676 case GT_PCI1_TOR: 677 case GT_PCI1_BS_SCS10: 678 case GT_PCI1_BS_SCS32: 679 case GT_PCI1_BS_CS20: 680 case GT_PCI1_BS_CS3BT: 681 case GT_PCI1_BARE: 682 case GT_PCI1_PREFMBR: 683 case GT_PCI1_SCS10_BAR: 684 case GT_PCI1_SCS32_BAR: 685 case GT_PCI1_CS20_BAR: 686 case GT_PCI1_CS3BT_BAR: 687 case GT_PCI1_SSCS10_BAR: 688 case GT_PCI1_SSCS32_BAR: 689 case GT_PCI1_SCS3BT_BAR: 690 case GT_PCI1_CFGADDR: 691 case GT_PCI1_CFGDATA: 692 /* not implemented */ 693 qemu_log_mask(LOG_UNIMP, 694 "gt64120: Unimplemented PCI register write " 695 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 696 saddr << 2, size, size << 1, val); 697 break; 698 case GT_PCI0_CFGADDR: 699 case GT_PCI0_CFGDATA: 700 /* Mapped via in gt64120_pci_mapping() */ 701 g_assert_not_reached(); 702 break; 703 704 /* Interrupts */ 705 case GT_INTRCAUSE: 706 /* not really implemented */ 707 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); 708 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); 709 trace_gt64120_write_intreg("INTRCAUSE", size, val); 710 break; 711 case GT_INTRMASK: 712 s->regs[saddr] = val & 0x3c3ffffe; 713 trace_gt64120_write_intreg("INTRMASK", size, val); 714 break; 715 case GT_PCI0_ICMASK: 716 s->regs[saddr] = val & 0x03fffffe; 717 trace_gt64120_write_intreg("ICMASK", size, val); 718 break; 719 case GT_PCI0_SERR0MASK: 720 s->regs[saddr] = val & 0x0000003f; 721 trace_gt64120_write_intreg("SERR0MASK", size, val); 722 break; 723 724 /* Reserved when only PCI_0 is configured. */ 725 case GT_HINTRCAUSE: 726 case GT_CPU_INTSEL: 727 case GT_PCI0_INTSEL: 728 case GT_HINTRMASK: 729 case GT_PCI0_HICMASK: 730 case GT_PCI1_SERR1MASK: 731 /* not implemented */ 732 break; 733 734 /* SDRAM Parameters */ 735 case GT_SDRAM_B0: 736 case GT_SDRAM_B1: 737 case GT_SDRAM_B2: 738 case GT_SDRAM_B3: 739 /* 740 * We don't simulate electrical parameters of the SDRAM. 741 * Accept, but ignore the values. 742 */ 743 s->regs[saddr] = val; 744 break; 745 746 default: 747 qemu_log_mask(LOG_GUEST_ERROR, 748 "gt64120: Illegal register write " 749 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 750 saddr << 2, size, size << 1, val); 751 break; 752 } 753 } 754 755 static uint64_t gt64120_readl(void *opaque, 756 hwaddr addr, unsigned size) 757 { 758 GT64120State *s = opaque; 759 uint32_t val; 760 uint32_t saddr = addr >> 2; 761 762 switch (saddr) { 763 764 /* CPU Configuration */ 765 case GT_MULTI: 766 /* 767 * Only one GT64xxx is present on the CPU bus, return 768 * the initial value. 769 */ 770 val = s->regs[saddr]; 771 break; 772 773 /* CPU Error Report */ 774 case GT_CPUERR_ADDRLO: 775 case GT_CPUERR_ADDRHI: 776 case GT_CPUERR_DATALO: 777 case GT_CPUERR_DATAHI: 778 case GT_CPUERR_PARITY: 779 /* Emulated memory has no error, always return the initial values. */ 780 val = s->regs[saddr]; 781 break; 782 783 /* CPU Sync Barrier */ 784 case GT_PCI0SYNC: 785 case GT_PCI1SYNC: 786 /* 787 * Reading those register should empty all FIFO on the PCI 788 * bus, which are not emulated. The return value should be 789 * a random value that should be ignored. 790 */ 791 val = 0xc000ffee; 792 break; 793 794 /* ECC */ 795 case GT_ECC_ERRDATALO: 796 case GT_ECC_ERRDATAHI: 797 case GT_ECC_MEM: 798 case GT_ECC_CALC: 799 case GT_ECC_ERRADDR: 800 /* Emulated memory has no error, always return the initial values. */ 801 val = s->regs[saddr]; 802 break; 803 804 case GT_CPU: 805 case GT_SCS10LD: 806 case GT_SCS10HD: 807 case GT_SCS32LD: 808 case GT_SCS32HD: 809 case GT_CS20LD: 810 case GT_CS20HD: 811 case GT_CS3BOOTLD: 812 case GT_CS3BOOTHD: 813 case GT_SCS10AR: 814 case GT_SCS32AR: 815 case GT_CS20R: 816 case GT_CS3BOOTR: 817 case GT_PCI0IOLD: 818 case GT_PCI0M0LD: 819 case GT_PCI0M1LD: 820 case GT_PCI1IOLD: 821 case GT_PCI1M0LD: 822 case GT_PCI1M1LD: 823 case GT_PCI0IOHD: 824 case GT_PCI0M0HD: 825 case GT_PCI0M1HD: 826 case GT_PCI1IOHD: 827 case GT_PCI1M0HD: 828 case GT_PCI1M1HD: 829 case GT_PCI0IOREMAP: 830 case GT_PCI0M0REMAP: 831 case GT_PCI0M1REMAP: 832 case GT_PCI1IOREMAP: 833 case GT_PCI1M0REMAP: 834 case GT_PCI1M1REMAP: 835 case GT_ISD: 836 val = s->regs[saddr]; 837 break; 838 case GT_PCI0_IACK: 839 /* Read the IRQ number */ 840 val = pic_read_irq(isa_pic); 841 break; 842 843 /* SDRAM and Device Address Decode */ 844 case GT_SCS0LD: 845 case GT_SCS0HD: 846 case GT_SCS1LD: 847 case GT_SCS1HD: 848 case GT_SCS2LD: 849 case GT_SCS2HD: 850 case GT_SCS3LD: 851 case GT_SCS3HD: 852 case GT_CS0LD: 853 case GT_CS0HD: 854 case GT_CS1LD: 855 case GT_CS1HD: 856 case GT_CS2LD: 857 case GT_CS2HD: 858 case GT_CS3LD: 859 case GT_CS3HD: 860 case GT_BOOTLD: 861 case GT_BOOTHD: 862 case GT_ADERR: 863 val = s->regs[saddr]; 864 break; 865 866 /* SDRAM Configuration */ 867 case GT_SDRAM_CFG: 868 case GT_SDRAM_OPMODE: 869 case GT_SDRAM_BM: 870 case GT_SDRAM_ADDRDECODE: 871 val = s->regs[saddr]; 872 break; 873 874 /* SDRAM Parameters */ 875 case GT_SDRAM_B0: 876 case GT_SDRAM_B1: 877 case GT_SDRAM_B2: 878 case GT_SDRAM_B3: 879 /* 880 * We don't simulate electrical parameters of the SDRAM. 881 * Just return the last written value. 882 */ 883 val = s->regs[saddr]; 884 break; 885 886 /* Device Parameters */ 887 case GT_DEV_B0: 888 case GT_DEV_B1: 889 case GT_DEV_B2: 890 case GT_DEV_B3: 891 case GT_DEV_BOOT: 892 val = s->regs[saddr]; 893 break; 894 895 /* DMA Record */ 896 case GT_DMA0_CNT: 897 case GT_DMA1_CNT: 898 case GT_DMA2_CNT: 899 case GT_DMA3_CNT: 900 case GT_DMA0_SA: 901 case GT_DMA1_SA: 902 case GT_DMA2_SA: 903 case GT_DMA3_SA: 904 case GT_DMA0_DA: 905 case GT_DMA1_DA: 906 case GT_DMA2_DA: 907 case GT_DMA3_DA: 908 case GT_DMA0_NEXT: 909 case GT_DMA1_NEXT: 910 case GT_DMA2_NEXT: 911 case GT_DMA3_NEXT: 912 case GT_DMA0_CUR: 913 case GT_DMA1_CUR: 914 case GT_DMA2_CUR: 915 case GT_DMA3_CUR: 916 val = s->regs[saddr]; 917 break; 918 919 /* DMA Channel Control */ 920 case GT_DMA0_CTRL: 921 case GT_DMA1_CTRL: 922 case GT_DMA2_CTRL: 923 case GT_DMA3_CTRL: 924 val = s->regs[saddr]; 925 break; 926 927 /* DMA Arbiter */ 928 case GT_DMA_ARB: 929 val = s->regs[saddr]; 930 break; 931 932 /* Timer/Counter */ 933 case GT_TC0: 934 case GT_TC1: 935 case GT_TC2: 936 case GT_TC3: 937 case GT_TC_CONTROL: 938 val = s->regs[saddr]; 939 break; 940 941 /* PCI Internal */ 942 case GT_PCI0_CFGADDR: 943 case GT_PCI0_CFGDATA: 944 /* Mapped via in gt64120_pci_mapping() */ 945 g_assert_not_reached(); 946 break; 947 948 case GT_PCI0_CMD: 949 case GT_PCI0_TOR: 950 case GT_PCI0_BS_SCS10: 951 case GT_PCI0_BS_SCS32: 952 case GT_PCI0_BS_CS20: 953 case GT_PCI0_BS_CS3BT: 954 case GT_PCI1_IACK: 955 case GT_PCI0_BARE: 956 case GT_PCI0_PREFMBR: 957 case GT_PCI0_SCS10_BAR: 958 case GT_PCI0_SCS32_BAR: 959 case GT_PCI0_CS20_BAR: 960 case GT_PCI0_CS3BT_BAR: 961 case GT_PCI0_SSCS10_BAR: 962 case GT_PCI0_SSCS32_BAR: 963 case GT_PCI0_SCS3BT_BAR: 964 case GT_PCI1_CMD: 965 case GT_PCI1_TOR: 966 case GT_PCI1_BS_SCS10: 967 case GT_PCI1_BS_SCS32: 968 case GT_PCI1_BS_CS20: 969 case GT_PCI1_BS_CS3BT: 970 case GT_PCI1_BARE: 971 case GT_PCI1_PREFMBR: 972 case GT_PCI1_SCS10_BAR: 973 case GT_PCI1_SCS32_BAR: 974 case GT_PCI1_CS20_BAR: 975 case GT_PCI1_CS3BT_BAR: 976 case GT_PCI1_SSCS10_BAR: 977 case GT_PCI1_SSCS32_BAR: 978 case GT_PCI1_SCS3BT_BAR: 979 case GT_PCI1_CFGADDR: 980 case GT_PCI1_CFGDATA: 981 val = s->regs[saddr]; 982 break; 983 984 /* Interrupts */ 985 case GT_INTRCAUSE: 986 val = s->regs[saddr]; 987 trace_gt64120_read_intreg("INTRCAUSE", size, val); 988 break; 989 case GT_INTRMASK: 990 val = s->regs[saddr]; 991 trace_gt64120_read_intreg("INTRMASK", size, val); 992 break; 993 case GT_PCI0_ICMASK: 994 val = s->regs[saddr]; 995 trace_gt64120_read_intreg("ICMASK", size, val); 996 break; 997 case GT_PCI0_SERR0MASK: 998 val = s->regs[saddr]; 999 trace_gt64120_read_intreg("SERR0MASK", size, val); 1000 break; 1001 1002 /* Reserved when only PCI_0 is configured. */ 1003 case GT_HINTRCAUSE: 1004 case GT_CPU_INTSEL: 1005 case GT_PCI0_INTSEL: 1006 case GT_HINTRMASK: 1007 case GT_PCI0_HICMASK: 1008 case GT_PCI1_SERR1MASK: 1009 val = s->regs[saddr]; 1010 break; 1011 1012 default: 1013 val = s->regs[saddr]; 1014 qemu_log_mask(LOG_GUEST_ERROR, 1015 "gt64120: Illegal register read " 1016 "reg:0x%03x size:%u value:0x%0*x\n", 1017 saddr << 2, size, size << 1, val); 1018 break; 1019 } 1020 1021 if (!(s->regs[GT_CPU] & 0x00001000)) { 1022 val = bswap32(val); 1023 } 1024 trace_gt64120_read(addr, val); 1025 1026 return val; 1027 } 1028 1029 static const MemoryRegionOps isd_mem_ops = { 1030 .read = gt64120_readl, 1031 .write = gt64120_writel, 1032 .endianness = DEVICE_NATIVE_ENDIAN, 1033 .impl = { 1034 .min_access_size = 4, 1035 .max_access_size = 4, 1036 }, 1037 }; 1038 1039 static void gt64120_reset(DeviceState *dev) 1040 { 1041 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); 1042 1043 /* FIXME: Malta specific hw assumptions ahead */ 1044 1045 /* CPU Configuration */ 1046 s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0; 1047 s->regs[GT_MULTI] = 0x00000003; 1048 1049 /* CPU Address decode */ 1050 s->regs[GT_SCS10LD] = 0x00000000; 1051 s->regs[GT_SCS10HD] = 0x00000007; 1052 s->regs[GT_SCS32LD] = 0x00000008; 1053 s->regs[GT_SCS32HD] = 0x0000000f; 1054 s->regs[GT_CS20LD] = 0x000000e0; 1055 s->regs[GT_CS20HD] = 0x00000070; 1056 s->regs[GT_CS3BOOTLD] = 0x000000f8; 1057 s->regs[GT_CS3BOOTHD] = 0x0000007f; 1058 1059 s->regs[GT_PCI0IOLD] = 0x00000080; 1060 s->regs[GT_PCI0IOHD] = 0x0000000f; 1061 s->regs[GT_PCI0M0LD] = 0x00000090; 1062 s->regs[GT_PCI0M0HD] = 0x0000001f; 1063 s->regs[GT_ISD] = 0x000000a0; 1064 s->regs[GT_PCI0M1LD] = 0x00000790; 1065 s->regs[GT_PCI0M1HD] = 0x0000001f; 1066 s->regs[GT_PCI1IOLD] = 0x00000100; 1067 s->regs[GT_PCI1IOHD] = 0x0000000f; 1068 s->regs[GT_PCI1M0LD] = 0x00000110; 1069 s->regs[GT_PCI1M0HD] = 0x0000001f; 1070 s->regs[GT_PCI1M1LD] = 0x00000120; 1071 s->regs[GT_PCI1M1HD] = 0x0000002f; 1072 1073 s->regs[GT_SCS10AR] = 0x00000000; 1074 s->regs[GT_SCS32AR] = 0x00000008; 1075 s->regs[GT_CS20R] = 0x000000e0; 1076 s->regs[GT_CS3BOOTR] = 0x000000f8; 1077 1078 s->regs[GT_PCI0IOREMAP] = 0x00000080; 1079 s->regs[GT_PCI0M0REMAP] = 0x00000090; 1080 s->regs[GT_PCI0M1REMAP] = 0x00000790; 1081 s->regs[GT_PCI1IOREMAP] = 0x00000100; 1082 s->regs[GT_PCI1M0REMAP] = 0x00000110; 1083 s->regs[GT_PCI1M1REMAP] = 0x00000120; 1084 1085 /* CPU Error Report */ 1086 s->regs[GT_CPUERR_ADDRLO] = 0x00000000; 1087 s->regs[GT_CPUERR_ADDRHI] = 0x00000000; 1088 s->regs[GT_CPUERR_DATALO] = 0xffffffff; 1089 s->regs[GT_CPUERR_DATAHI] = 0xffffffff; 1090 s->regs[GT_CPUERR_PARITY] = 0x000000ff; 1091 1092 /* CPU Sync Barrier */ 1093 s->regs[GT_PCI0SYNC] = 0x00000000; 1094 s->regs[GT_PCI1SYNC] = 0x00000000; 1095 1096 /* SDRAM and Device Address Decode */ 1097 s->regs[GT_SCS0LD] = 0x00000000; 1098 s->regs[GT_SCS0HD] = 0x00000007; 1099 s->regs[GT_SCS1LD] = 0x00000008; 1100 s->regs[GT_SCS1HD] = 0x0000000f; 1101 s->regs[GT_SCS2LD] = 0x00000010; 1102 s->regs[GT_SCS2HD] = 0x00000017; 1103 s->regs[GT_SCS3LD] = 0x00000018; 1104 s->regs[GT_SCS3HD] = 0x0000001f; 1105 s->regs[GT_CS0LD] = 0x000000c0; 1106 s->regs[GT_CS0HD] = 0x000000c7; 1107 s->regs[GT_CS1LD] = 0x000000c8; 1108 s->regs[GT_CS1HD] = 0x000000cf; 1109 s->regs[GT_CS2LD] = 0x000000d0; 1110 s->regs[GT_CS2HD] = 0x000000df; 1111 s->regs[GT_CS3LD] = 0x000000f0; 1112 s->regs[GT_CS3HD] = 0x000000fb; 1113 s->regs[GT_BOOTLD] = 0x000000fc; 1114 s->regs[GT_BOOTHD] = 0x000000ff; 1115 s->regs[GT_ADERR] = 0xffffffff; 1116 1117 /* SDRAM Configuration */ 1118 s->regs[GT_SDRAM_CFG] = 0x00000200; 1119 s->regs[GT_SDRAM_OPMODE] = 0x00000000; 1120 s->regs[GT_SDRAM_BM] = 0x00000007; 1121 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; 1122 1123 /* SDRAM Parameters */ 1124 s->regs[GT_SDRAM_B0] = 0x00000005; 1125 s->regs[GT_SDRAM_B1] = 0x00000005; 1126 s->regs[GT_SDRAM_B2] = 0x00000005; 1127 s->regs[GT_SDRAM_B3] = 0x00000005; 1128 1129 /* ECC */ 1130 s->regs[GT_ECC_ERRDATALO] = 0x00000000; 1131 s->regs[GT_ECC_ERRDATAHI] = 0x00000000; 1132 s->regs[GT_ECC_MEM] = 0x00000000; 1133 s->regs[GT_ECC_CALC] = 0x00000000; 1134 s->regs[GT_ECC_ERRADDR] = 0x00000000; 1135 1136 /* Device Parameters */ 1137 s->regs[GT_DEV_B0] = 0x386fffff; 1138 s->regs[GT_DEV_B1] = 0x386fffff; 1139 s->regs[GT_DEV_B2] = 0x386fffff; 1140 s->regs[GT_DEV_B3] = 0x386fffff; 1141 s->regs[GT_DEV_BOOT] = 0x146fffff; 1142 1143 /* DMA registers are all zeroed at reset */ 1144 1145 /* Timer/Counter */ 1146 s->regs[GT_TC0] = 0xffffffff; 1147 s->regs[GT_TC1] = 0x00ffffff; 1148 s->regs[GT_TC2] = 0x00ffffff; 1149 s->regs[GT_TC3] = 0x00ffffff; 1150 s->regs[GT_TC_CONTROL] = 0x00000000; 1151 1152 /* PCI Internal */ 1153 s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0; 1154 s->regs[GT_PCI0_TOR] = 0x0000070f; 1155 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; 1156 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; 1157 s->regs[GT_PCI0_BS_CS20] = 0x01fff000; 1158 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; 1159 s->regs[GT_PCI1_IACK] = 0x00000000; 1160 s->regs[GT_PCI0_IACK] = 0x00000000; 1161 s->regs[GT_PCI0_BARE] = 0x0000000f; 1162 s->regs[GT_PCI0_PREFMBR] = 0x00000040; 1163 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; 1164 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; 1165 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; 1166 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; 1167 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; 1168 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; 1169 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; 1170 s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0; 1171 s->regs[GT_PCI1_TOR] = 0x0000070f; 1172 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; 1173 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; 1174 s->regs[GT_PCI1_BS_CS20] = 0x01fff000; 1175 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; 1176 s->regs[GT_PCI1_BARE] = 0x0000000f; 1177 s->regs[GT_PCI1_PREFMBR] = 0x00000040; 1178 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; 1179 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; 1180 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; 1181 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; 1182 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; 1183 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; 1184 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; 1185 s->regs[GT_PCI1_CFGADDR] = 0x00000000; 1186 s->regs[GT_PCI1_CFGDATA] = 0x00000000; 1187 s->regs[GT_PCI0_CFGADDR] = 0x00000000; 1188 1189 /* Interrupt registers are all zeroed at reset */ 1190 1191 gt64120_isd_mapping(s); 1192 gt64120_pci_mapping(s); 1193 gt64120_update_pci_cfgdata_mapping(s); 1194 } 1195 1196 static void gt64120_realize(DeviceState *dev, Error **errp) 1197 { 1198 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); 1199 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 1200 1201 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, 1202 "gt64120-isd", 0x1000); 1203 memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); 1204 address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem"); 1205 phb->bus = pci_root_bus_new(dev, "pci", 1206 &s->pci0_mem, 1207 get_system_io(), 1208 PCI_DEVFN(18, 0), TYPE_PCI_BUS); 1209 1210 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); 1211 1212 /* 1213 * The whole address space decoded by the GT-64120A doesn't generate 1214 * exception when accessing invalid memory. Create an empty slot to 1215 * emulate this feature. 1216 */ 1217 empty_slot_init("GT64120", 0, 0x20000000); 1218 } 1219 1220 static void gt64120_pci_realize(PCIDevice *d, Error **errp) 1221 { 1222 /* FIXME: Malta specific hw assumptions ahead */ 1223 pci_set_word(d->config + PCI_COMMAND, 0); 1224 pci_set_word(d->config + PCI_STATUS, 1225 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 1226 pci_config_set_prog_interface(d->config, 0); 1227 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); 1228 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); 1229 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); 1230 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); 1231 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); 1232 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); 1233 pci_set_byte(d->config + 0x3d, 0x01); 1234 } 1235 1236 static void gt64120_pci_class_init(ObjectClass *klass, void *data) 1237 { 1238 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1239 DeviceClass *dc = DEVICE_CLASS(klass); 1240 1241 k->realize = gt64120_pci_realize; 1242 k->vendor_id = PCI_VENDOR_ID_MARVELL; 1243 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; 1244 k->revision = 0x10; 1245 k->class_id = PCI_CLASS_BRIDGE_HOST; 1246 /* 1247 * PCI-facing part of the host bridge, not usable without the 1248 * host-facing part, which can't be device_add'ed, yet. 1249 */ 1250 dc->user_creatable = false; 1251 } 1252 1253 static const TypeInfo gt64120_pci_info = { 1254 .name = "gt64120_pci", 1255 .parent = TYPE_PCI_DEVICE, 1256 .instance_size = sizeof(PCIDevice), 1257 .class_init = gt64120_pci_class_init, 1258 .interfaces = (InterfaceInfo[]) { 1259 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1260 { }, 1261 }, 1262 }; 1263 1264 static Property gt64120_properties[] = { 1265 DEFINE_PROP_BOOL("cpu-little-endian", GT64120State, 1266 cpu_little_endian, false), 1267 DEFINE_PROP_END_OF_LIST(), 1268 }; 1269 1270 static void gt64120_class_init(ObjectClass *klass, void *data) 1271 { 1272 DeviceClass *dc = DEVICE_CLASS(klass); 1273 1274 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1275 device_class_set_props(dc, gt64120_properties); 1276 dc->realize = gt64120_realize; 1277 dc->reset = gt64120_reset; 1278 dc->vmsd = &vmstate_gt64120; 1279 } 1280 1281 static const TypeInfo gt64120_info = { 1282 .name = TYPE_GT64120_PCI_HOST_BRIDGE, 1283 .parent = TYPE_PCI_HOST_BRIDGE, 1284 .instance_size = sizeof(GT64120State), 1285 .class_init = gt64120_class_init, 1286 }; 1287 1288 static void gt64120_pci_register_types(void) 1289 { 1290 type_register_static(>64120_info); 1291 type_register_static(>64120_pci_info); 1292 } 1293 1294 type_init(gt64120_pci_register_types) 1295