xref: /qemu/hw/pci-host/ppce500.c (revision abff1abf) 
1 /*
2  * QEMU PowerPC E500 embedded processors pci controller emulation
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from hw/ppc4xx_pci.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "hw/irq.h"
19 #include "hw/ppc/e500-ccsr.h"
20 #include "hw/qdev-properties.h"
21 #include "migration/vmstate.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/pci_host.h"
24 #include "qemu/bswap.h"
25 #include "qemu/module.h"
26 #include "hw/pci-host/ppce500.h"
27 
28 #ifdef DEBUG_PCI
29 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
30 #else
31 #define pci_debug(fmt, ...)
32 #endif
33 
34 #define PCIE500_CFGADDR       0x0
35 #define PCIE500_CFGDATA       0x4
36 #define PCIE500_REG_BASE      0xC00
37 #define PCIE500_ALL_SIZE      0x1000
38 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
39 
40 #define PCIE500_PCI_IOLEN     0x10000ULL
41 
42 #define PPCE500_PCI_CONFIG_ADDR         0x0
43 #define PPCE500_PCI_CONFIG_DATA         0x4
44 #define PPCE500_PCI_INTACK              0x8
45 
46 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
47 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
49 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
50 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
51 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
52 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
53 
54 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
55 
56 #define PCI_POTAR               0x0
57 #define PCI_POTEAR              0x4
58 #define PCI_POWBAR              0x8
59 #define PCI_POWAR               0x10
60 
61 #define PCI_PITAR               0x0
62 #define PCI_PIWBAR              0x8
63 #define PCI_PIWBEAR             0xC
64 #define PCI_PIWAR               0x10
65 
66 #define PPCE500_PCI_NR_POBS     5
67 #define PPCE500_PCI_NR_PIBS     3
68 
69 #define PIWAR_EN                0x80000000      /* Enable */
70 #define PIWAR_PF                0x20000000      /* prefetch */
71 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
72 #define PIWAR_READ_SNOOP        0x00050000
73 #define PIWAR_WRITE_SNOOP       0x00005000
74 #define PIWAR_SZ_MASK           0x0000003f
75 
76 struct  pci_outbound {
77     uint32_t potar;
78     uint32_t potear;
79     uint32_t powbar;
80     uint32_t powar;
81     MemoryRegion mem;
82 };
83 
84 struct pci_inbound {
85     uint32_t pitar;
86     uint32_t piwbar;
87     uint32_t piwbear;
88     uint32_t piwar;
89     MemoryRegion mem;
90 };
91 
92 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
93 
94 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
95     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
96 
97 struct PPCE500PCIState {
98     PCIHostState parent_obj;
99 
100     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
101     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
102     uint32_t gasket_time;
103     qemu_irq irq[PCI_NUM_PINS];
104     uint32_t irq_num[PCI_NUM_PINS];
105     uint32_t first_slot;
106     uint32_t first_pin_irq;
107     AddressSpace bm_as;
108     MemoryRegion bm;
109     /* mmio maps */
110     MemoryRegion container;
111     MemoryRegion iomem;
112     MemoryRegion pio;
113     MemoryRegion busmem;
114 };
115 
116 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
117 #define PPC_E500_PCI_BRIDGE(obj) \
118     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
119 
120 struct PPCE500PCIBridgeState {
121     /*< private >*/
122     PCIDevice parent;
123     /*< public >*/
124 
125     MemoryRegion bar0;
126 };
127 
128 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
129 typedef struct PPCE500PCIState PPCE500PCIState;
130 
131 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
132                               unsigned size)
133 {
134     PPCE500PCIState *pci = opaque;
135     unsigned long win;
136     uint32_t value = 0;
137     int idx;
138 
139     win = addr & 0xfe0;
140 
141     switch (win) {
142     case PPCE500_PCI_OW1:
143     case PPCE500_PCI_OW2:
144     case PPCE500_PCI_OW3:
145     case PPCE500_PCI_OW4:
146         idx = (addr >> 5) & 0x7;
147         switch (addr & 0x1F) {
148         case PCI_POTAR:
149             value = pci->pob[idx].potar;
150             break;
151         case PCI_POTEAR:
152             value = pci->pob[idx].potear;
153             break;
154         case PCI_POWBAR:
155             value = pci->pob[idx].powbar;
156             break;
157         case PCI_POWAR:
158             value = pci->pob[idx].powar;
159             break;
160         default:
161             break;
162         }
163         break;
164 
165     case PPCE500_PCI_IW3:
166     case PPCE500_PCI_IW2:
167     case PPCE500_PCI_IW1:
168         idx = ((addr >> 5) & 0x3) - 1;
169         switch (addr & 0x1F) {
170         case PCI_PITAR:
171             value = pci->pib[idx].pitar;
172             break;
173         case PCI_PIWBAR:
174             value = pci->pib[idx].piwbar;
175             break;
176         case PCI_PIWBEAR:
177             value = pci->pib[idx].piwbear;
178             break;
179         case PCI_PIWAR:
180             value = pci->pib[idx].piwar;
181             break;
182         default:
183             break;
184         };
185         break;
186 
187     case PPCE500_PCI_GASKET_TIMR:
188         value = pci->gasket_time;
189         break;
190 
191     default:
192         break;
193     }
194 
195     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
196               win, addr, value);
197     return value;
198 }
199 
200 /* DMA mapping */
201 static void e500_update_piw(PPCE500PCIState *pci, int idx)
202 {
203     uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
204     uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
205     uint64_t war = pci->pib[idx].piwar;
206     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
207     MemoryRegion *address_space_mem = get_system_memory();
208     MemoryRegion *mem = &pci->pib[idx].mem;
209     MemoryRegion *bm = &pci->bm;
210     char *name;
211 
212     if (memory_region_is_mapped(mem)) {
213         /* Before we modify anything, unmap and destroy the region */
214         memory_region_del_subregion(bm, mem);
215         object_unparent(OBJECT(mem));
216     }
217 
218     if (!(war & PIWAR_EN)) {
219         /* Not enabled, nothing to do */
220         return;
221     }
222 
223     name = g_strdup_printf("PCI Inbound Window %d", idx);
224     memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
225                              size);
226     memory_region_add_subregion_overlap(bm, wbar, mem, -1);
227     g_free(name);
228 
229     pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
230               __func__, size, wbar, tar);
231 }
232 
233 /* BAR mapping */
234 static void e500_update_pow(PPCE500PCIState *pci, int idx)
235 {
236     uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
237     uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
238     uint64_t war = pci->pob[idx].powar;
239     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
240     MemoryRegion *mem = &pci->pob[idx].mem;
241     MemoryRegion *address_space_mem = get_system_memory();
242     char *name;
243 
244     if (memory_region_is_mapped(mem)) {
245         /* Before we modify anything, unmap and destroy the region */
246         memory_region_del_subregion(address_space_mem, mem);
247         object_unparent(OBJECT(mem));
248     }
249 
250     if (!(war & PIWAR_EN)) {
251         /* Not enabled, nothing to do */
252         return;
253     }
254 
255     name = g_strdup_printf("PCI Outbound Window %d", idx);
256     memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
257                              size);
258     memory_region_add_subregion(address_space_mem, wbar, mem);
259     g_free(name);
260 
261     pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
262               __func__, size, wbar, tar);
263 }
264 
265 static void pci_reg_write4(void *opaque, hwaddr addr,
266                            uint64_t value, unsigned size)
267 {
268     PPCE500PCIState *pci = opaque;
269     unsigned long win;
270     int idx;
271 
272     win = addr & 0xfe0;
273 
274     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
275               __func__, (unsigned)value, win, addr);
276 
277     switch (win) {
278     case PPCE500_PCI_OW1:
279     case PPCE500_PCI_OW2:
280     case PPCE500_PCI_OW3:
281     case PPCE500_PCI_OW4:
282         idx = (addr >> 5) & 0x7;
283         switch (addr & 0x1F) {
284         case PCI_POTAR:
285             pci->pob[idx].potar = value;
286             e500_update_pow(pci, idx);
287             break;
288         case PCI_POTEAR:
289             pci->pob[idx].potear = value;
290             e500_update_pow(pci, idx);
291             break;
292         case PCI_POWBAR:
293             pci->pob[idx].powbar = value;
294             e500_update_pow(pci, idx);
295             break;
296         case PCI_POWAR:
297             pci->pob[idx].powar = value;
298             e500_update_pow(pci, idx);
299             break;
300         default:
301             break;
302         };
303         break;
304 
305     case PPCE500_PCI_IW3:
306     case PPCE500_PCI_IW2:
307     case PPCE500_PCI_IW1:
308         idx = ((addr >> 5) & 0x3) - 1;
309         switch (addr & 0x1F) {
310         case PCI_PITAR:
311             pci->pib[idx].pitar = value;
312             e500_update_piw(pci, idx);
313             break;
314         case PCI_PIWBAR:
315             pci->pib[idx].piwbar = value;
316             e500_update_piw(pci, idx);
317             break;
318         case PCI_PIWBEAR:
319             pci->pib[idx].piwbear = value;
320             e500_update_piw(pci, idx);
321             break;
322         case PCI_PIWAR:
323             pci->pib[idx].piwar = value;
324             e500_update_piw(pci, idx);
325             break;
326         default:
327             break;
328         };
329         break;
330 
331     case PPCE500_PCI_GASKET_TIMR:
332         pci->gasket_time = value;
333         break;
334 
335     default:
336         break;
337     };
338 }
339 
340 static const MemoryRegionOps e500_pci_reg_ops = {
341     .read = pci_reg_read4,
342     .write = pci_reg_write4,
343     .endianness = DEVICE_BIG_ENDIAN,
344 };
345 
346 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
347 {
348     int devno = pci_dev->devfn >> 3;
349     int ret;
350 
351     ret = ppce500_pci_map_irq_slot(devno, pin);
352 
353     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
354            pci_dev->devfn, pin, ret, devno);
355 
356     return ret;
357 }
358 
359 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
360 {
361     PPCE500PCIState *s = opaque;
362     qemu_irq *pic = s->irq;
363 
364     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
365 
366     qemu_set_irq(pic[pin], level);
367 }
368 
369 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
370 {
371     PCIINTxRoute route;
372     PPCE500PCIState *s = opaque;
373 
374     route.mode = PCI_INTX_ENABLED;
375     route.irq = s->irq_num[pin];
376 
377     pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
378     return route;
379 }
380 
381 static const VMStateDescription vmstate_pci_outbound = {
382     .name = "pci_outbound",
383     .version_id = 0,
384     .minimum_version_id = 0,
385     .fields = (VMStateField[]) {
386         VMSTATE_UINT32(potar, struct pci_outbound),
387         VMSTATE_UINT32(potear, struct pci_outbound),
388         VMSTATE_UINT32(powbar, struct pci_outbound),
389         VMSTATE_UINT32(powar, struct pci_outbound),
390         VMSTATE_END_OF_LIST()
391     }
392 };
393 
394 static const VMStateDescription vmstate_pci_inbound = {
395     .name = "pci_inbound",
396     .version_id = 0,
397     .minimum_version_id = 0,
398     .fields = (VMStateField[]) {
399         VMSTATE_UINT32(pitar, struct pci_inbound),
400         VMSTATE_UINT32(piwbar, struct pci_inbound),
401         VMSTATE_UINT32(piwbear, struct pci_inbound),
402         VMSTATE_UINT32(piwar, struct pci_inbound),
403         VMSTATE_END_OF_LIST()
404     }
405 };
406 
407 static const VMStateDescription vmstate_ppce500_pci = {
408     .name = "ppce500_pci",
409     .version_id = 1,
410     .minimum_version_id = 1,
411     .fields = (VMStateField[]) {
412         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
413                              vmstate_pci_outbound, struct pci_outbound),
414         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
415                              vmstate_pci_inbound, struct pci_inbound),
416         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
417         VMSTATE_END_OF_LIST()
418     }
419 };
420 
421 #include "exec/address-spaces.h"
422 
423 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
424 {
425     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
426     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
427                                   "/e500-ccsr"));
428 
429     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
430                              0, int128_get64(ccsr->ccsr_space.size));
431     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
432 }
433 
434 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
435                                             int devfn)
436 {
437     PPCE500PCIState *s = opaque;
438 
439     return &s->bm_as;
440 }
441 
442 static void e500_pcihost_realize(DeviceState *dev, Error **errp)
443 {
444     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
445     PCIHostState *h;
446     PPCE500PCIState *s;
447     PCIBus *b;
448     int i;
449 
450     h = PCI_HOST_BRIDGE(dev);
451     s = PPC_E500_PCI_HOST_BRIDGE(dev);
452 
453     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
454         sysbus_init_irq(sbd, &s->irq[i]);
455     }
456 
457     for (i = 0; i < PCI_NUM_PINS; i++) {
458         s->irq_num[i] = s->first_pin_irq + i;
459     }
460 
461     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
462     memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
463 
464     /* PIO lives at the bottom of our bus space */
465     memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
466 
467     b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq,
468                               mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
469                               PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
470     h->bus = b;
471 
472     /* Set up PCI view of memory */
473     memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
474     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
475     address_space_init(&s->bm_as, &s->bm, "pci-bm");
476     pci_setup_iommu(b, e500_pcihost_set_iommu, s);
477 
478     pci_create_simple(b, 0, "e500-host-bridge");
479 
480     memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
481     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
482                           "pci-conf-idx", 4);
483     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
484                           "pci-conf-data", 4);
485     memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
486                           "pci.reg", PCIE500_REG_SIZE);
487     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
488     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
489     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
490     sysbus_init_mmio(sbd, &s->container);
491     pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
492 }
493 
494 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
495 {
496     DeviceClass *dc = DEVICE_CLASS(klass);
497     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
498 
499     k->realize = e500_pcihost_bridge_realize;
500     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
501     k->device_id = PCI_DEVICE_ID_MPC8533E;
502     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
503     dc->desc = "Host bridge";
504     /*
505      * PCI-facing part of the host bridge, not usable without the
506      * host-facing part, which can't be device_add'ed, yet.
507      */
508     dc->user_creatable = false;
509 }
510 
511 static const TypeInfo e500_host_bridge_info = {
512     .name          = "e500-host-bridge",
513     .parent        = TYPE_PCI_DEVICE,
514     .instance_size = sizeof(PPCE500PCIBridgeState),
515     .class_init    = e500_host_bridge_class_init,
516     .interfaces = (InterfaceInfo[]) {
517         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
518         { },
519     },
520 };
521 
522 static Property pcihost_properties[] = {
523     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
524     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
525     DEFINE_PROP_END_OF_LIST(),
526 };
527 
528 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
529 {
530     DeviceClass *dc = DEVICE_CLASS(klass);
531 
532     dc->realize = e500_pcihost_realize;
533     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
534     device_class_set_props(dc, pcihost_properties);
535     dc->vmsd = &vmstate_ppce500_pci;
536 }
537 
538 static const TypeInfo e500_pcihost_info = {
539     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
540     .parent        = TYPE_PCI_HOST_BRIDGE,
541     .instance_size = sizeof(PPCE500PCIState),
542     .class_init    = e500_pcihost_class_init,
543 };
544 
545 static void e500_pci_register_types(void)
546 {
547     type_register_static(&e500_pcihost_info);
548     type_register_static(&e500_host_bridge_info);
549 }
550 
551 type_init(e500_pci_register_types)
552