xref: /qemu/hw/pci-host/ppce500.c (revision d4517d17) 
1 /*
2  * QEMU PowerPC E500 embedded processors pci controller emulation
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from hw/ppc4xx_pci.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16 
17 #include "hw/hw.h"
18 #include "hw/ppc/e500-ccsr.h"
19 #include "hw/pci/pci.h"
20 #include "hw/pci/pci_host.h"
21 #include "qemu/bswap.h"
22 #include "hw/pci-host/ppce500.h"
23 
24 #ifdef DEBUG_PCI
25 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
26 #else
27 #define pci_debug(fmt, ...)
28 #endif
29 
30 #define PCIE500_CFGADDR       0x0
31 #define PCIE500_CFGDATA       0x4
32 #define PCIE500_REG_BASE      0xC00
33 #define PCIE500_ALL_SIZE      0x1000
34 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
35 
36 #define PCIE500_PCI_IOLEN     0x10000ULL
37 
38 #define PPCE500_PCI_CONFIG_ADDR         0x0
39 #define PPCE500_PCI_CONFIG_DATA         0x4
40 #define PPCE500_PCI_INTACK              0x8
41 
42 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
43 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
44 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
45 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
46 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
47 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
49 
50 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
51 
52 #define PCI_POTAR               0x0
53 #define PCI_POTEAR              0x4
54 #define PCI_POWBAR              0x8
55 #define PCI_POWAR               0x10
56 
57 #define PCI_PITAR               0x0
58 #define PCI_PIWBAR              0x8
59 #define PCI_PIWBEAR             0xC
60 #define PCI_PIWAR               0x10
61 
62 #define PPCE500_PCI_NR_POBS     5
63 #define PPCE500_PCI_NR_PIBS     3
64 
65 #define PIWAR_EN                0x80000000      /* Enable */
66 #define PIWAR_PF                0x20000000      /* prefetch */
67 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
68 #define PIWAR_READ_SNOOP        0x00050000
69 #define PIWAR_WRITE_SNOOP       0x00005000
70 #define PIWAR_SZ_MASK           0x0000003f
71 
72 struct  pci_outbound {
73     uint32_t potar;
74     uint32_t potear;
75     uint32_t powbar;
76     uint32_t powar;
77     MemoryRegion mem;
78 };
79 
80 struct pci_inbound {
81     uint32_t pitar;
82     uint32_t piwbar;
83     uint32_t piwbear;
84     uint32_t piwar;
85     MemoryRegion mem;
86 };
87 
88 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
89 
90 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
91     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
92 
93 struct PPCE500PCIState {
94     PCIHostState parent_obj;
95 
96     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
97     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
98     uint32_t gasket_time;
99     qemu_irq irq[PCI_NUM_PINS];
100     uint32_t irq_num[PCI_NUM_PINS];
101     uint32_t first_slot;
102     uint32_t first_pin_irq;
103     AddressSpace bm_as;
104     MemoryRegion bm;
105     /* mmio maps */
106     MemoryRegion container;
107     MemoryRegion iomem;
108     MemoryRegion pio;
109     MemoryRegion busmem;
110 };
111 
112 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
113 #define PPC_E500_PCI_BRIDGE(obj) \
114     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
115 
116 struct PPCE500PCIBridgeState {
117     /*< private >*/
118     PCIDevice parent;
119     /*< public >*/
120 
121     MemoryRegion bar0;
122 };
123 
124 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
125 typedef struct PPCE500PCIState PPCE500PCIState;
126 
127 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
128                               unsigned size)
129 {
130     PPCE500PCIState *pci = opaque;
131     unsigned long win;
132     uint32_t value = 0;
133     int idx;
134 
135     win = addr & 0xfe0;
136 
137     switch (win) {
138     case PPCE500_PCI_OW1:
139     case PPCE500_PCI_OW2:
140     case PPCE500_PCI_OW3:
141     case PPCE500_PCI_OW4:
142         idx = (addr >> 5) & 0x7;
143         switch (addr & 0xC) {
144         case PCI_POTAR:
145             value = pci->pob[idx].potar;
146             break;
147         case PCI_POTEAR:
148             value = pci->pob[idx].potear;
149             break;
150         case PCI_POWBAR:
151             value = pci->pob[idx].powbar;
152             break;
153         case PCI_POWAR:
154             value = pci->pob[idx].powar;
155             break;
156         default:
157             break;
158         }
159         break;
160 
161     case PPCE500_PCI_IW3:
162     case PPCE500_PCI_IW2:
163     case PPCE500_PCI_IW1:
164         idx = ((addr >> 5) & 0x3) - 1;
165         switch (addr & 0xC) {
166         case PCI_PITAR:
167             value = pci->pib[idx].pitar;
168             break;
169         case PCI_PIWBAR:
170             value = pci->pib[idx].piwbar;
171             break;
172         case PCI_PIWBEAR:
173             value = pci->pib[idx].piwbear;
174             break;
175         case PCI_PIWAR:
176             value = pci->pib[idx].piwar;
177             break;
178         default:
179             break;
180         };
181         break;
182 
183     case PPCE500_PCI_GASKET_TIMR:
184         value = pci->gasket_time;
185         break;
186 
187     default:
188         break;
189     }
190 
191     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
192               win, addr, value);
193     return value;
194 }
195 
196 /* DMA mapping */
197 static void e500_update_piw(PPCE500PCIState *pci, int idx)
198 {
199     uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
200     uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
201     uint64_t war = pci->pib[idx].piwar;
202     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
203     MemoryRegion *address_space_mem = get_system_memory();
204     MemoryRegion *mem = &pci->pib[idx].mem;
205     MemoryRegion *bm = &pci->bm;
206     char *name;
207 
208     if (memory_region_is_mapped(mem)) {
209         /* Before we modify anything, unmap and destroy the region */
210         memory_region_del_subregion(bm, mem);
211         object_unparent(OBJECT(mem));
212     }
213 
214     if (!(war & PIWAR_EN)) {
215         /* Not enabled, nothing to do */
216         return;
217     }
218 
219     name = g_strdup_printf("PCI Inbound Window %d", idx);
220     memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
221                              size);
222     memory_region_add_subregion_overlap(bm, wbar, mem, -1);
223     g_free(name);
224 
225     pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
226               __func__, size, wbar, tar);
227 }
228 
229 /* BAR mapping */
230 static void e500_update_pow(PPCE500PCIState *pci, int idx)
231 {
232     uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
233     uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
234     uint64_t war = pci->pob[idx].powar;
235     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
236     MemoryRegion *mem = &pci->pob[idx].mem;
237     MemoryRegion *address_space_mem = get_system_memory();
238     char *name;
239 
240     if (memory_region_is_mapped(mem)) {
241         /* Before we modify anything, unmap and destroy the region */
242         memory_region_del_subregion(address_space_mem, mem);
243         object_unparent(OBJECT(mem));
244     }
245 
246     if (!(war & PIWAR_EN)) {
247         /* Not enabled, nothing to do */
248         return;
249     }
250 
251     name = g_strdup_printf("PCI Outbound Window %d", idx);
252     memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
253                              size);
254     memory_region_add_subregion(address_space_mem, wbar, mem);
255     g_free(name);
256 
257     pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
258               __func__, size, wbar, tar);
259 }
260 
261 static void pci_reg_write4(void *opaque, hwaddr addr,
262                            uint64_t value, unsigned size)
263 {
264     PPCE500PCIState *pci = opaque;
265     unsigned long win;
266     int idx;
267 
268     win = addr & 0xfe0;
269 
270     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
271               __func__, (unsigned)value, win, addr);
272 
273     switch (win) {
274     case PPCE500_PCI_OW1:
275     case PPCE500_PCI_OW2:
276     case PPCE500_PCI_OW3:
277     case PPCE500_PCI_OW4:
278         idx = (addr >> 5) & 0x7;
279         switch (addr & 0x1F) {
280         case PCI_POTAR:
281             pci->pob[idx].potar = value;
282             e500_update_pow(pci, idx);
283             break;
284         case PCI_POTEAR:
285             pci->pob[idx].potear = value;
286             e500_update_pow(pci, idx);
287             break;
288         case PCI_POWBAR:
289             pci->pob[idx].powbar = value;
290             e500_update_pow(pci, idx);
291             break;
292         case PCI_POWAR:
293             pci->pob[idx].powar = value;
294             e500_update_pow(pci, idx);
295             break;
296         default:
297             break;
298         };
299         break;
300 
301     case PPCE500_PCI_IW3:
302     case PPCE500_PCI_IW2:
303     case PPCE500_PCI_IW1:
304         idx = ((addr >> 5) & 0x3) - 1;
305         switch (addr & 0x1F) {
306         case PCI_PITAR:
307             pci->pib[idx].pitar = value;
308             e500_update_piw(pci, idx);
309             break;
310         case PCI_PIWBAR:
311             pci->pib[idx].piwbar = value;
312             e500_update_piw(pci, idx);
313             break;
314         case PCI_PIWBEAR:
315             pci->pib[idx].piwbear = value;
316             e500_update_piw(pci, idx);
317             break;
318         case PCI_PIWAR:
319             pci->pib[idx].piwar = value;
320             e500_update_piw(pci, idx);
321             break;
322         default:
323             break;
324         };
325         break;
326 
327     case PPCE500_PCI_GASKET_TIMR:
328         pci->gasket_time = value;
329         break;
330 
331     default:
332         break;
333     };
334 }
335 
336 static const MemoryRegionOps e500_pci_reg_ops = {
337     .read = pci_reg_read4,
338     .write = pci_reg_write4,
339     .endianness = DEVICE_BIG_ENDIAN,
340 };
341 
342 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
343 {
344     int devno = pci_dev->devfn >> 3;
345     int ret;
346 
347     ret = ppce500_pci_map_irq_slot(devno, pin);
348 
349     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
350            pci_dev->devfn, pin, ret, devno);
351 
352     return ret;
353 }
354 
355 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
356 {
357     PPCE500PCIState *s = opaque;
358     qemu_irq *pic = s->irq;
359 
360     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
361 
362     qemu_set_irq(pic[pin], level);
363 }
364 
365 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
366 {
367     PCIINTxRoute route;
368     PPCE500PCIState *s = opaque;
369 
370     route.mode = PCI_INTX_ENABLED;
371     route.irq = s->irq_num[pin];
372 
373     pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
374     return route;
375 }
376 
377 static const VMStateDescription vmstate_pci_outbound = {
378     .name = "pci_outbound",
379     .version_id = 0,
380     .minimum_version_id = 0,
381     .fields = (VMStateField[]) {
382         VMSTATE_UINT32(potar, struct pci_outbound),
383         VMSTATE_UINT32(potear, struct pci_outbound),
384         VMSTATE_UINT32(powbar, struct pci_outbound),
385         VMSTATE_UINT32(powar, struct pci_outbound),
386         VMSTATE_END_OF_LIST()
387     }
388 };
389 
390 static const VMStateDescription vmstate_pci_inbound = {
391     .name = "pci_inbound",
392     .version_id = 0,
393     .minimum_version_id = 0,
394     .fields = (VMStateField[]) {
395         VMSTATE_UINT32(pitar, struct pci_inbound),
396         VMSTATE_UINT32(piwbar, struct pci_inbound),
397         VMSTATE_UINT32(piwbear, struct pci_inbound),
398         VMSTATE_UINT32(piwar, struct pci_inbound),
399         VMSTATE_END_OF_LIST()
400     }
401 };
402 
403 static const VMStateDescription vmstate_ppce500_pci = {
404     .name = "ppce500_pci",
405     .version_id = 1,
406     .minimum_version_id = 1,
407     .fields = (VMStateField[]) {
408         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
409                              vmstate_pci_outbound, struct pci_outbound),
410         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
411                              vmstate_pci_inbound, struct pci_inbound),
412         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
413         VMSTATE_END_OF_LIST()
414     }
415 };
416 
417 #include "exec/address-spaces.h"
418 
419 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
420 {
421     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
422     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
423                                   "/e500-ccsr"));
424 
425     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
426     d->config[PCI_HEADER_TYPE] =
427         (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
428         PCI_HEADER_TYPE_BRIDGE;
429 
430     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
431                              0, int128_get64(ccsr->ccsr_space.size));
432     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
433 }
434 
435 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
436                                             int devfn)
437 {
438     PPCE500PCIState *s = opaque;
439 
440     return &s->bm_as;
441 }
442 
443 static int e500_pcihost_initfn(SysBusDevice *dev)
444 {
445     PCIHostState *h;
446     PPCE500PCIState *s;
447     PCIBus *b;
448     int i;
449 
450     h = PCI_HOST_BRIDGE(dev);
451     s = PPC_E500_PCI_HOST_BRIDGE(dev);
452 
453     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
454         sysbus_init_irq(dev, &s->irq[i]);
455     }
456 
457     for (i = 0; i < PCI_NUM_PINS; i++) {
458         s->irq_num[i] = s->first_pin_irq + i;
459     }
460 
461     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
462     memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
463 
464     /* PIO lives at the bottom of our bus space */
465     memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
466 
467     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
468                          mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
469                          PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
470     h->bus = b;
471 
472     /* Set up PCI view of memory */
473     memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
474     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
475     address_space_init(&s->bm_as, &s->bm, "pci-bm");
476     pci_setup_iommu(b, e500_pcihost_set_iommu, s);
477 
478     pci_create_simple(b, 0, "e500-host-bridge");
479 
480     memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
481     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
482                           "pci-conf-idx", 4);
483     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
484                           "pci-conf-data", 4);
485     memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
486                           "pci.reg", PCIE500_REG_SIZE);
487     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
488     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
489     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
490     sysbus_init_mmio(dev, &s->container);
491     pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
492 
493     return 0;
494 }
495 
496 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
497 {
498     DeviceClass *dc = DEVICE_CLASS(klass);
499     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
500 
501     k->realize = e500_pcihost_bridge_realize;
502     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
503     k->device_id = PCI_DEVICE_ID_MPC8533E;
504     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
505     dc->desc = "Host bridge";
506     /*
507      * PCI-facing part of the host bridge, not usable without the
508      * host-facing part, which can't be device_add'ed, yet.
509      */
510     dc->cannot_instantiate_with_device_add_yet = true;
511 }
512 
513 static const TypeInfo e500_host_bridge_info = {
514     .name          = "e500-host-bridge",
515     .parent        = TYPE_PCI_DEVICE,
516     .instance_size = sizeof(PPCE500PCIBridgeState),
517     .class_init    = e500_host_bridge_class_init,
518 };
519 
520 static Property pcihost_properties[] = {
521     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
522     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
523     DEFINE_PROP_END_OF_LIST(),
524 };
525 
526 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
527 {
528     DeviceClass *dc = DEVICE_CLASS(klass);
529     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
530 
531     k->init = e500_pcihost_initfn;
532     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
533     dc->props = pcihost_properties;
534     dc->vmsd = &vmstate_ppce500_pci;
535 }
536 
537 static const TypeInfo e500_pcihost_info = {
538     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
539     .parent        = TYPE_PCI_HOST_BRIDGE,
540     .instance_size = sizeof(PPCE500PCIState),
541     .class_init    = e500_pcihost_class_init,
542 };
543 
544 static void e500_pci_register_types(void)
545 {
546     type_register_static(&e500_pcihost_info);
547     type_register_static(&e500_host_bridge_info);
548 }
549 
550 type_init(e500_pci_register_types)
551