1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 329b0ca75eSPhilippe Mathieu-Daudé #include "qemu/log.h" 3371adf91aSPhilippe Mathieu-Daudé #include "hw/i386/pc.h" 34c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 35a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 36d6454270SMarkus Armbruster #include "migration/vmstate.h" 37da34e65cSMarkus Armbruster #include "qapi/error.h" 3839848901SIgor Mammedov #include "qapi/visitor.h" 390b8fa32fSMarkus Armbruster #include "qemu/module.h" 40c0907c9eSPaolo Bonzini 41c0907c9eSPaolo Bonzini /**************************************************************************** 42c0907c9eSPaolo Bonzini * Q35 host 43c0907c9eSPaolo Bonzini */ 44c0907c9eSPaolo Bonzini 459fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 469fa99d25SMarcel Apfelbaum 4762d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 48c0907c9eSPaolo Bonzini { 49ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 50ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 5162d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 52c0907c9eSPaolo Bonzini 5362d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5462d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 55c0907c9eSPaolo Bonzini 5662d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5762d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 58c0907c9eSPaolo Bonzini 59a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 60a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 61a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 62a8de0115SPeng Hao 631115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 641115ff6dSDavid Gibson s->mch.pci_address_space, 651115ff6dSDavid Gibson s->mch.address_space_io, 66c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 67621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 68c9e96b04SXingang Wang pci->bypass_iommu = 69c9e96b04SXingang Wang PC_MACHINE(qdev_get_machine())->default_bus_bypass_iommu; 7099ba777eSMarkus Armbruster qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); 71c0907c9eSPaolo Bonzini } 72c0907c9eSPaolo Bonzini 73568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 74568f0690SDavid Gibson PCIBus *rootbus) 75568f0690SDavid Gibson { 7604c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 7704c7d8b8SCole Robinson 78568f0690SDavid Gibson /* For backwards compat with old device paths */ 7904c7d8b8SCole Robinson if (s->mch.short_root_bus) { 80568f0690SDavid Gibson return "0000"; 81568f0690SDavid Gibson } 8204c7d8b8SCole Robinson return "0000:00"; 8304c7d8b8SCole Robinson } 84568f0690SDavid Gibson 8539848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 86d7bce999SEric Blake const char *name, void *opaque, 8739848901SIgor Mammedov Error **errp) 8839848901SIgor Mammedov { 8939848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 90a0efbf16SMarkus Armbruster uint64_t val64; 91a0efbf16SMarkus Armbruster uint32_t value; 9239848901SIgor Mammedov 93a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 94a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 95a0efbf16SMarkus Armbruster value = val64; 96a0efbf16SMarkus Armbruster assert(value == val64); 9751e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9839848901SIgor Mammedov } 9939848901SIgor Mammedov 10039848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 101d7bce999SEric Blake const char *name, void *opaque, 10239848901SIgor Mammedov Error **errp) 10339848901SIgor Mammedov { 10439848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 105a0efbf16SMarkus Armbruster uint64_t val64; 106a0efbf16SMarkus Armbruster uint32_t value; 10739848901SIgor Mammedov 108a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 109a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 110a0efbf16SMarkus Armbruster value = val64; 111a0efbf16SMarkus Armbruster assert(value == val64); 11251e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 11339848901SIgor Mammedov } 11439848901SIgor Mammedov 1159fa99d25SMarcel Apfelbaum /* 1169fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1179fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1189fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1199fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1209fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1219fa99d25SMarcel Apfelbaum */ 122ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 12339848901SIgor Mammedov { 1248b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1259fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1268b42d730SMichael S. Tsirkin Range w64; 127a0efbf16SMarkus Armbruster uint64_t value; 12839848901SIgor Mammedov 1298b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 130a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1319fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1329fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1339fa99d25SMarcel Apfelbaum } 134ccef5b1fSLaszlo Ersek return value; 135ccef5b1fSLaszlo Ersek } 136ccef5b1fSLaszlo Ersek 137ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 138ccef5b1fSLaszlo Ersek const char *name, void *opaque, 139ccef5b1fSLaszlo Ersek Error **errp) 140ccef5b1fSLaszlo Ersek { 141ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 142ccef5b1fSLaszlo Ersek 143ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 14439848901SIgor Mammedov } 14539848901SIgor Mammedov 1469fa99d25SMarcel Apfelbaum /* 1479fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1489fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1499fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1509fa99d25SMarcel Apfelbaum * that can be configured by the user. 1519fa99d25SMarcel Apfelbaum */ 15239848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 153d7bce999SEric Blake const char *name, void *opaque, 15439848901SIgor Mammedov Error **errp) 15539848901SIgor Mammedov { 1568b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1579fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 158ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1598b42d730SMichael S. Tsirkin Range w64; 1609fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 16139848901SIgor Mammedov 1628b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 163a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1649fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1659fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1669fa99d25SMarcel Apfelbaum value = hole64_end; 1679fa99d25SMarcel Apfelbaum } 168a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16939848901SIgor Mammedov } 17039848901SIgor Mammedov 1719fa99d25SMarcel Apfelbaum /* 1729fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1739fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1749fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1759fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1769fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1779fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1789fa99d25SMarcel Apfelbaum */ 1792f295167SLaszlo Ersek static Property q35_host_props[] = { 18087f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 181c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 18239848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1839fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 18404c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 185401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 186401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 187401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 188401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1899fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 190c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 191c0907c9eSPaolo Bonzini }; 192c0907c9eSPaolo Bonzini 193c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 194c0907c9eSPaolo Bonzini { 195c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 196568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 197c0907c9eSPaolo Bonzini 198568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 19962d92e43SHu Tao dc->realize = q35_host_realize; 2004f67d30bSMarc-André Lureau device_class_set_props(dc, q35_host_props); 201bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 202e90f2a8cSEduardo Habkost dc->user_creatable = false; 203125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 20468c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 205c0907c9eSPaolo Bonzini } 206c0907c9eSPaolo Bonzini 207c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 208c0907c9eSPaolo Bonzini { 209c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 21062d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 21164a7b8deSFelipe Franciosi PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); 21262d92e43SHu Tao 21362d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 21462d92e43SHu Tao "pci-conf-idx", 4); 21562d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 21662d92e43SHu Tao "pci-conf-data", 4); 217c0907c9eSPaolo Bonzini 2189fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); 219446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 220c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2219fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2229fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2239fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2241e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 22539848901SIgor Mammedov q35_host_get_pci_hole_start, 226d2623129SMarkus Armbruster NULL, NULL, NULL); 22739848901SIgor Mammedov 2281e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 22939848901SIgor Mammedov q35_host_get_pci_hole_end, 230d2623129SMarkus Armbruster NULL, NULL, NULL); 23139848901SIgor Mammedov 2321e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 23339848901SIgor Mammedov q35_host_get_pci_hole64_start, 234d2623129SMarkus Armbruster NULL, NULL, NULL); 23539848901SIgor Mammedov 2361e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 23739848901SIgor Mammedov q35_host_get_pci_hole64_end, 238d2623129SMarkus Armbruster NULL, NULL, NULL); 23939848901SIgor Mammedov 24064a7b8deSFelipe Franciosi object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, 241d2623129SMarkus Armbruster &pehb->size, OBJ_PROP_FLAG_READ); 242cbcaf79eSMichael S. Tsirkin 243401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 244401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 245d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 246401f2f3eSEfimov Vasily 247401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 248401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 249d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 250401f2f3eSEfimov Vasily 251401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 252401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 253d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 254401f2f3eSEfimov Vasily 255401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 256401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 257d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 258c0907c9eSPaolo Bonzini } 259c0907c9eSPaolo Bonzini 260c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 261c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 262c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 263c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 264c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 265c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 266c0907c9eSPaolo Bonzini }; 267c0907c9eSPaolo Bonzini 268c0907c9eSPaolo Bonzini /**************************************************************************** 269c0907c9eSPaolo Bonzini * MCH D0:F0 270c0907c9eSPaolo Bonzini */ 271c0907c9eSPaolo Bonzini 272f404220eSIgor Mammedov static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 273bafc90bdSGerd Hoffmann { 274bafc90bdSGerd Hoffmann return 0xffffffff; 275bafc90bdSGerd Hoffmann } 276bafc90bdSGerd Hoffmann 277f404220eSIgor Mammedov static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 278bafc90bdSGerd Hoffmann unsigned width) 279bafc90bdSGerd Hoffmann { 280bafc90bdSGerd Hoffmann /* nothing */ 281bafc90bdSGerd Hoffmann } 282bafc90bdSGerd Hoffmann 283f404220eSIgor Mammedov static const MemoryRegionOps blackhole_ops = { 284f404220eSIgor Mammedov .read = blackhole_read, 285f404220eSIgor Mammedov .write = blackhole_write, 286bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 287bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 288bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 289bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 290bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 291bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 292bafc90bdSGerd Hoffmann }; 293bafc90bdSGerd Hoffmann 294c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 295c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 296c0907c9eSPaolo Bonzini { 297ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 298ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 299ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 300c0907c9eSPaolo Bonzini 301c0907c9eSPaolo Bonzini uint64_t pciexbar; 302c0907c9eSPaolo Bonzini int enable; 303c0907c9eSPaolo Bonzini uint64_t addr; 304c0907c9eSPaolo Bonzini uint64_t addr_mask; 305c0907c9eSPaolo Bonzini uint32_t length; 306c0907c9eSPaolo Bonzini 307c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 308c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 309c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 310c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 311c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 312c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 313c0907c9eSPaolo Bonzini break; 314c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 315c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 316c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 317c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 318c0907c9eSPaolo Bonzini break; 319c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 320c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 321c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 322c0907c9eSPaolo Bonzini break; 323c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 3249b0ca75eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); 3259b0ca75eSPhilippe Mathieu-Daudé return; 326c0907c9eSPaolo Bonzini default: 327c0907c9eSPaolo Bonzini abort(); 328c0907c9eSPaolo Bonzini } 329c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 330ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 331c0907c9eSPaolo Bonzini } 332c0907c9eSPaolo Bonzini 333c0907c9eSPaolo Bonzini /* PAM */ 334c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 335c0907c9eSPaolo Bonzini { 336ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 337c0907c9eSPaolo Bonzini int i; 338c0907c9eSPaolo Bonzini 339c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 340c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 341c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 34266175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 343c0907c9eSPaolo Bonzini } 344c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 345c0907c9eSPaolo Bonzini } 346c0907c9eSPaolo Bonzini 347c0907c9eSPaolo Bonzini /* SMRAM */ 348c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 349c0907c9eSPaolo Bonzini { 350ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 35164130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 352bafc90bdSGerd Hoffmann uint32_t tseg_size; 353ce88812fSHu Tao 35468c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 35568c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 35668c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 35768c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 35868c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 35968c77acfSGerd Hoffmann } 36068c77acfSGerd Hoffmann 361c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 36264130fa4SPaolo Bonzini 36364130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 36464130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 36564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 36664130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 36764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 36864130fa4SPaolo Bonzini } else { 36964130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 37064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 37164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 37264130fa4SPaolo Bonzini } 37364130fa4SPaolo Bonzini 37464130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 37564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 37664130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 37764130fa4SPaolo Bonzini } else { 37864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 37964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 38064130fa4SPaolo Bonzini } 38164130fa4SPaolo Bonzini 382766a9814SZhenzhong Duan if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && 383766a9814SZhenzhong Duan (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { 384bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 385bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 386bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 387bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 388bafc90bdSGerd Hoffmann break; 389bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 390bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 391bafc90bdSGerd Hoffmann break; 392bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 393bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 394bafc90bdSGerd Hoffmann break; 395bafc90bdSGerd Hoffmann default: 3962f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 397bafc90bdSGerd Hoffmann break; 398bafc90bdSGerd Hoffmann } 399bafc90bdSGerd Hoffmann } else { 400bafc90bdSGerd Hoffmann tseg_size = 0; 401bafc90bdSGerd Hoffmann } 402bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 403bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 404bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 405bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 406bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 407bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 408bafc90bdSGerd Hoffmann 409bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 410bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 411bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 412bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 413bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 414bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 415bafc90bdSGerd Hoffmann 416c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 417c0907c9eSPaolo Bonzini } 418c0907c9eSPaolo Bonzini 4192f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4202f295167SLaszlo Ersek { 4212f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4222f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4232f295167SLaszlo Ersek 4242f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4252f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4262f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4272f295167SLaszlo Ersek } 4282f295167SLaszlo Ersek } 4292f295167SLaszlo Ersek 430f404220eSIgor Mammedov static void mch_update_smbase_smram(MCHPCIState *mch) 431f404220eSIgor Mammedov { 432f404220eSIgor Mammedov PCIDevice *pd = PCI_DEVICE(mch); 433f404220eSIgor Mammedov uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 434f404220eSIgor Mammedov bool lck; 435f404220eSIgor Mammedov 436f404220eSIgor Mammedov if (!mch->has_smram_at_smbase) { 437f404220eSIgor Mammedov return; 438f404220eSIgor Mammedov } 439f404220eSIgor Mammedov 440f404220eSIgor Mammedov if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 441f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 442f404220eSIgor Mammedov MCH_HOST_BRIDGE_F_SMBASE_LCK; 443f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 444f404220eSIgor Mammedov return; 445f404220eSIgor Mammedov } 446f404220eSIgor Mammedov 447f404220eSIgor Mammedov /* 448f404220eSIgor Mammedov * default/reset state, discard written value 449f404220eSIgor Mammedov * which will disable SMRAM balackhole at SMBASE 450f404220eSIgor Mammedov */ 451f404220eSIgor Mammedov if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 452f404220eSIgor Mammedov *reg = 0x00; 453f404220eSIgor Mammedov } 454f404220eSIgor Mammedov 455f404220eSIgor Mammedov memory_region_transaction_begin(); 456f404220eSIgor Mammedov if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 457f404220eSIgor Mammedov /* disable all writes */ 458f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 459f404220eSIgor Mammedov ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 460f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 461f404220eSIgor Mammedov lck = true; 462f404220eSIgor Mammedov } else { 463f404220eSIgor Mammedov lck = false; 464f404220eSIgor Mammedov } 465f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, lck); 466f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, lck); 467f404220eSIgor Mammedov memory_region_transaction_commit(); 468f404220eSIgor Mammedov } 469f404220eSIgor Mammedov 470c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 471c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 472c0907c9eSPaolo Bonzini { 473c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 474c0907c9eSPaolo Bonzini 475c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 476c0907c9eSPaolo Bonzini 477c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 478c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 479c0907c9eSPaolo Bonzini mch_update_pam(mch); 480c0907c9eSPaolo Bonzini } 481c0907c9eSPaolo Bonzini 482c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 483c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 484c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 485c0907c9eSPaolo Bonzini } 486c0907c9eSPaolo Bonzini 487263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 488263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 489c0907c9eSPaolo Bonzini mch_update_smram(mch); 490c0907c9eSPaolo Bonzini } 4912f295167SLaszlo Ersek 4922f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4932f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4942f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4952f295167SLaszlo Ersek } 496f404220eSIgor Mammedov 497f404220eSIgor Mammedov if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 498f404220eSIgor Mammedov mch_update_smbase_smram(mch); 499f404220eSIgor Mammedov } 500c0907c9eSPaolo Bonzini } 501c0907c9eSPaolo Bonzini 502c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 503c0907c9eSPaolo Bonzini { 504c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 505c0907c9eSPaolo Bonzini mch_update_pam(mch); 506c0907c9eSPaolo Bonzini mch_update_smram(mch); 5072f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 508f404220eSIgor Mammedov mch_update_smbase_smram(mch); 5094a441836SGerd Hoffmann 5104a441836SGerd Hoffmann /* 5114a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 5124a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 5134a441836SGerd Hoffmann */ 5144a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 5154a441836SGerd Hoffmann mch->below_4g_mem_size, 5164a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 517c0907c9eSPaolo Bonzini } 518c0907c9eSPaolo Bonzini 519c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 520c0907c9eSPaolo Bonzini { 521c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 522c0907c9eSPaolo Bonzini mch_update(mch); 523c0907c9eSPaolo Bonzini return 0; 524c0907c9eSPaolo Bonzini } 525c0907c9eSPaolo Bonzini 526c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 527c0907c9eSPaolo Bonzini .name = "mch", 528c0907c9eSPaolo Bonzini .version_id = 1, 529c0907c9eSPaolo Bonzini .minimum_version_id = 1, 530c0907c9eSPaolo Bonzini .post_load = mch_post_load, 531c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 532ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 533f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 534f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 535f809c605SPaolo Bonzini */ 536f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 537c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 538c0907c9eSPaolo Bonzini } 539c0907c9eSPaolo Bonzini }; 540c0907c9eSPaolo Bonzini 541c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 542c0907c9eSPaolo Bonzini { 543c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 544c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 545c0907c9eSPaolo Bonzini 546c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 547c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 548c0907c9eSPaolo Bonzini 549263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 55077447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 551b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 552b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 553c0907c9eSPaolo Bonzini 5542f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5552f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5562f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5572f295167SLaszlo Ersek } 5582f295167SLaszlo Ersek 559f404220eSIgor Mammedov d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 560f404220eSIgor Mammedov d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 561f404220eSIgor Mammedov 562c0907c9eSPaolo Bonzini mch_update(mch); 563c0907c9eSPaolo Bonzini } 564c0907c9eSPaolo Bonzini 5659af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 566c0907c9eSPaolo Bonzini { 567c0907c9eSPaolo Bonzini int i; 568c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 569c0907c9eSPaolo Bonzini 5702f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5712f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5722f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5732f295167SLaszlo Ersek return; 5742f295167SLaszlo Ersek } 5752f295167SLaszlo Ersek 57683d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 57709aa7be1SPhilippe Mathieu-Daudé pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); 57839848901SIgor Mammedov 579fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 58040c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 581dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 582dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 583dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 584c0907c9eSPaolo Bonzini &mch->smram_region, 1); 585fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 586fe6567d5SPaolo Bonzini 58764130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 588dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 589dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 59064130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 59164130fa4SPaolo Bonzini &mch->open_high_smram, 1); 59264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 59364130fa4SPaolo Bonzini 594fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 59551eae1e7SPhilippe Mathieu-Daudé memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB); 596fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 597fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 598dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 599dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 600fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 601dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 602dda53ee9SZihan Yang &mch->low_smram); 60364130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 604dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 605dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 60664130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 60764130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 608bafc90bdSGerd Hoffmann 609bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 610f404220eSIgor Mammedov &blackhole_ops, NULL, 611bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 612bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 613bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 614bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 615bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 616bafc90bdSGerd Hoffmann 617bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 618bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 619bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 620bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 621bafc90bdSGerd Hoffmann &mch->tseg_window); 622f404220eSIgor Mammedov 623f404220eSIgor Mammedov /* 624f404220eSIgor Mammedov * This is not what hardware does, so it's QEMU specific hack. 625f404220eSIgor Mammedov * See commit message for details. 626f404220eSIgor Mammedov */ 627f404220eSIgor Mammedov memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 628f404220eSIgor Mammedov NULL, "smbase-blackhole", 629f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 630f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, false); 631f404220eSIgor Mammedov memory_region_add_subregion_overlap(mch->system_memory, 632f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 633f404220eSIgor Mammedov &mch->smbase_blackhole, 1); 634f404220eSIgor Mammedov 635f404220eSIgor Mammedov memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 636f404220eSIgor Mammedov "smbase-window", mch->ram_memory, 637f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 638f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 639f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, false); 640f404220eSIgor Mammedov memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 641f404220eSIgor Mammedov &mch->smbase_window); 642f404220eSIgor Mammedov 643fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 644d2623129SMarkus Armbruster OBJECT(&mch->smram)); 645fe6567d5SPaolo Bonzini 646ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 647ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 648ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 649f6a3c86eSPhilippe Mathieu-Daudé for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { 650ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 651ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 652ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 653c0907c9eSPaolo Bonzini } 654c0907c9eSPaolo Bonzini } 655c0907c9eSPaolo Bonzini 6566f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 6576f1426abSMichael S. Tsirkin { 6586f1426abSMichael S. Tsirkin bool ambiguous; 6596f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 6606f1426abSMichael S. Tsirkin if (!o) { 6616f1426abSMichael S. Tsirkin return 0; 6626f1426abSMichael S. Tsirkin } 6636f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 6646f1426abSMichael S. Tsirkin } 6656f1426abSMichael S. Tsirkin 6662f295167SLaszlo Ersek static Property mch_props[] = { 6672f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6682f295167SLaszlo Ersek 16), 669f404220eSIgor Mammedov DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 6702f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6712f295167SLaszlo Ersek }; 6722f295167SLaszlo Ersek 673c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 674c0907c9eSPaolo Bonzini { 675c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 676c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 677c0907c9eSPaolo Bonzini 6789af21dbeSMarkus Armbruster k->realize = mch_realize; 679c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 680c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6814f67d30bSMarc-André Lureau device_class_set_props(dc, mch_props); 682125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 683c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 684c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 685c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 686d4715481SDaniel P. Berrangé /* 687d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 688d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 689d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 690d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 691d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 692d4715481SDaniel P. Berrangé * chipset. 693d4715481SDaniel P. Berrangé */ 694d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 695451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 696c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 69708c58f92SMarkus Armbruster /* 69808c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 69908c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 70008c58f92SMarkus Armbruster */ 701e90f2a8cSEduardo Habkost dc->user_creatable = false; 702c0907c9eSPaolo Bonzini } 703c0907c9eSPaolo Bonzini 704c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 705c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 706c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 707c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 708c0907c9eSPaolo Bonzini .class_init = mch_class_init, 709fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 710fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 711fd3b02c8SEduardo Habkost { }, 712fd3b02c8SEduardo Habkost }, 713c0907c9eSPaolo Bonzini }; 714c0907c9eSPaolo Bonzini 715c0907c9eSPaolo Bonzini static void q35_register(void) 716c0907c9eSPaolo Bonzini { 717c0907c9eSPaolo Bonzini type_register_static(&mch_info); 718c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 719c0907c9eSPaolo Bonzini } 720c0907c9eSPaolo Bonzini 721c0907c9eSPaolo Bonzini type_init(q35_register); 722