1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30b6a0aa05SPeter Maydell #include "qemu/osdep.h" 31c0907c9eSPaolo Bonzini #include "hw/hw.h" 32c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 33da34e65cSMarkus Armbruster #include "qapi/error.h" 3439848901SIgor Mammedov #include "qapi/visitor.h" 35c0907c9eSPaolo Bonzini 36c0907c9eSPaolo Bonzini /**************************************************************************** 37c0907c9eSPaolo Bonzini * Q35 host 38c0907c9eSPaolo Bonzini */ 39c0907c9eSPaolo Bonzini 409fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 419fa99d25SMarcel Apfelbaum 4262d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 43c0907c9eSPaolo Bonzini { 44ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 45ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4662d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 47c0907c9eSPaolo Bonzini 4862d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4962d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 50c0907c9eSPaolo Bonzini 5162d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5262d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 53c0907c9eSPaolo Bonzini 54*1115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 55*1115ff6dSDavid Gibson s->mch.pci_address_space, 56*1115ff6dSDavid Gibson s->mch.address_space_io, 57c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 58621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 59ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 60c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 61c0907c9eSPaolo Bonzini } 62c0907c9eSPaolo Bonzini 63568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 64568f0690SDavid Gibson PCIBus *rootbus) 65568f0690SDavid Gibson { 6604c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 6704c7d8b8SCole Robinson 68568f0690SDavid Gibson /* For backwards compat with old device paths */ 6904c7d8b8SCole Robinson if (s->mch.short_root_bus) { 70568f0690SDavid Gibson return "0000"; 71568f0690SDavid Gibson } 7204c7d8b8SCole Robinson return "0000:00"; 7304c7d8b8SCole Robinson } 74568f0690SDavid Gibson 7539848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 76d7bce999SEric Blake const char *name, void *opaque, 7739848901SIgor Mammedov Error **errp) 7839848901SIgor Mammedov { 7939848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 80a0efbf16SMarkus Armbruster uint64_t val64; 81a0efbf16SMarkus Armbruster uint32_t value; 8239848901SIgor Mammedov 83a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 84a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 85a0efbf16SMarkus Armbruster value = val64; 86a0efbf16SMarkus Armbruster assert(value == val64); 8751e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 8839848901SIgor Mammedov } 8939848901SIgor Mammedov 9039848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 91d7bce999SEric Blake const char *name, void *opaque, 9239848901SIgor Mammedov Error **errp) 9339848901SIgor Mammedov { 9439848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 95a0efbf16SMarkus Armbruster uint64_t val64; 96a0efbf16SMarkus Armbruster uint32_t value; 9739848901SIgor Mammedov 98a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 99a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 100a0efbf16SMarkus Armbruster value = val64; 101a0efbf16SMarkus Armbruster assert(value == val64); 10251e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 10339848901SIgor Mammedov } 10439848901SIgor Mammedov 1059fa99d25SMarcel Apfelbaum /* 1069fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1079fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1089fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1099fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1109fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1119fa99d25SMarcel Apfelbaum */ 11239848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 113d7bce999SEric Blake const char *name, void *opaque, 11439848901SIgor Mammedov Error **errp) 11539848901SIgor Mammedov { 1168b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1179fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1188b42d730SMichael S. Tsirkin Range w64; 119a0efbf16SMarkus Armbruster uint64_t value; 12039848901SIgor Mammedov 1218b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 122a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1239fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1249fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1259fa99d25SMarcel Apfelbaum } 126a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 12739848901SIgor Mammedov } 12839848901SIgor Mammedov 1299fa99d25SMarcel Apfelbaum /* 1309fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1319fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1329fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1339fa99d25SMarcel Apfelbaum * that can be configured by the user. 1349fa99d25SMarcel Apfelbaum */ 13539848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 136d7bce999SEric Blake const char *name, void *opaque, 13739848901SIgor Mammedov Error **errp) 13839848901SIgor Mammedov { 1398b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1409fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1419fa99d25SMarcel Apfelbaum uint64_t hole64_start = pc_pci_hole64_start(); 1428b42d730SMichael S. Tsirkin Range w64; 1439fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 14439848901SIgor Mammedov 1458b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 146a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1479fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1489fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1499fa99d25SMarcel Apfelbaum value = hole64_end; 1509fa99d25SMarcel Apfelbaum } 151a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 15239848901SIgor Mammedov } 15339848901SIgor Mammedov 154d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 155d7bce999SEric Blake void *opaque, Error **errp) 156cbcaf79eSMichael S. Tsirkin { 157cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 158cbcaf79eSMichael S. Tsirkin 159d015c4eaSMarc-André Lureau visit_type_uint64(v, name, &e->size, errp); 160cbcaf79eSMichael S. Tsirkin } 161cbcaf79eSMichael S. Tsirkin 1629fa99d25SMarcel Apfelbaum /* 1639fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1649fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1659fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1669fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1679fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1689fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1699fa99d25SMarcel Apfelbaum */ 1702f295167SLaszlo Ersek static Property q35_host_props[] = { 17187f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 172c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 17339848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1749fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 17504c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 176401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 177401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 178401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 179401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1809fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 181c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 182c0907c9eSPaolo Bonzini }; 183c0907c9eSPaolo Bonzini 184c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 185c0907c9eSPaolo Bonzini { 186c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 187568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 188c0907c9eSPaolo Bonzini 189568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 19062d92e43SHu Tao dc->realize = q35_host_realize; 1912f295167SLaszlo Ersek dc->props = q35_host_props; 192bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 193e90f2a8cSEduardo Habkost dc->user_creatable = false; 194125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 19568c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 196c0907c9eSPaolo Bonzini } 197c0907c9eSPaolo Bonzini 198c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 199c0907c9eSPaolo Bonzini { 200c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 20162d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 20262d92e43SHu Tao 20362d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 20462d92e43SHu Tao "pci-conf-idx", 4); 20562d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 20662d92e43SHu Tao "pci-conf-data", 4); 207c0907c9eSPaolo Bonzini 208213f0c4fSAndreas Färber object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 209c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 210446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 211c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2129fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2139fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2149fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2151e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 21639848901SIgor Mammedov q35_host_get_pci_hole_start, 21739848901SIgor Mammedov NULL, NULL, NULL, NULL); 21839848901SIgor Mammedov 2191e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 22039848901SIgor Mammedov q35_host_get_pci_hole_end, 22139848901SIgor Mammedov NULL, NULL, NULL, NULL); 22239848901SIgor Mammedov 2231e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 22439848901SIgor Mammedov q35_host_get_pci_hole64_start, 22539848901SIgor Mammedov NULL, NULL, NULL, NULL); 22639848901SIgor Mammedov 2271e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 22839848901SIgor Mammedov q35_host_get_pci_hole64_end, 22939848901SIgor Mammedov NULL, NULL, NULL, NULL); 23039848901SIgor Mammedov 2311e507bb0SMarc-André Lureau object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 232cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 233cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 234cbcaf79eSMichael S. Tsirkin 235401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 236401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 237401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 238401f2f3eSEfimov Vasily 239401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 240401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 241401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 242401f2f3eSEfimov Vasily 243401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 244401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 245401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 246401f2f3eSEfimov Vasily 247401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 248401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 249401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 250401f2f3eSEfimov Vasily 25139848901SIgor Mammedov /* Leave enough space for the biggest MCFG BAR */ 25239848901SIgor Mammedov /* TODO: this matches current bios behaviour, but 25339848901SIgor Mammedov * it's not a power of two, which means an MTRR 25439848901SIgor Mammedov * can't cover it exactly. 25539848901SIgor Mammedov */ 256a0efbf16SMarkus Armbruster range_set_bounds(&s->mch.pci_hole, 257a0efbf16SMarkus Armbruster MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 258a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 259c0907c9eSPaolo Bonzini } 260c0907c9eSPaolo Bonzini 261c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 262c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 263c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 264c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 265c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 266c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 267c0907c9eSPaolo Bonzini }; 268c0907c9eSPaolo Bonzini 269c0907c9eSPaolo Bonzini /**************************************************************************** 270c0907c9eSPaolo Bonzini * MCH D0:F0 271c0907c9eSPaolo Bonzini */ 272c0907c9eSPaolo Bonzini 273bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 274bafc90bdSGerd Hoffmann { 275bafc90bdSGerd Hoffmann return 0xffffffff; 276bafc90bdSGerd Hoffmann } 277bafc90bdSGerd Hoffmann 278bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 279bafc90bdSGerd Hoffmann unsigned width) 280bafc90bdSGerd Hoffmann { 281bafc90bdSGerd Hoffmann /* nothing */ 282bafc90bdSGerd Hoffmann } 283bafc90bdSGerd Hoffmann 284bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = { 285bafc90bdSGerd Hoffmann .read = tseg_blackhole_read, 286bafc90bdSGerd Hoffmann .write = tseg_blackhole_write, 287bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 288bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 289bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 290bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 291bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 292bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 293bafc90bdSGerd Hoffmann }; 294bafc90bdSGerd Hoffmann 295c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 296c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 297c0907c9eSPaolo Bonzini { 298ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 299ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 300ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 301c0907c9eSPaolo Bonzini 302c0907c9eSPaolo Bonzini uint64_t pciexbar; 303c0907c9eSPaolo Bonzini int enable; 304c0907c9eSPaolo Bonzini uint64_t addr; 305c0907c9eSPaolo Bonzini uint64_t addr_mask; 306c0907c9eSPaolo Bonzini uint32_t length; 307c0907c9eSPaolo Bonzini 308c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 309c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 310c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 311c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 312c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 313c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 314c0907c9eSPaolo Bonzini break; 315c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 316c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 317c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 318c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 319c0907c9eSPaolo Bonzini break; 320c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 321c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 322c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 323c0907c9eSPaolo Bonzini break; 324c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 325c0907c9eSPaolo Bonzini default: 326c0907c9eSPaolo Bonzini abort(); 327c0907c9eSPaolo Bonzini } 328c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 329ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 330636228a8SMichael S. Tsirkin /* Leave enough space for the MCFG BAR */ 331636228a8SMichael S. Tsirkin /* 332636228a8SMichael S. Tsirkin * TODO: this matches current bios behaviour, but it's not a power of two, 333636228a8SMichael S. Tsirkin * which means an MTRR can't cover it exactly. 334636228a8SMichael S. Tsirkin */ 335636228a8SMichael S. Tsirkin if (enable) { 336a0efbf16SMarkus Armbruster range_set_bounds(&mch->pci_hole, 337a0efbf16SMarkus Armbruster addr + length, 338a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 339636228a8SMichael S. Tsirkin } else { 340a0efbf16SMarkus Armbruster range_set_bounds(&mch->pci_hole, 341a0efbf16SMarkus Armbruster MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 342a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 343636228a8SMichael S. Tsirkin } 344c0907c9eSPaolo Bonzini } 345c0907c9eSPaolo Bonzini 346c0907c9eSPaolo Bonzini /* PAM */ 347c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 348c0907c9eSPaolo Bonzini { 349ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 350c0907c9eSPaolo Bonzini int i; 351c0907c9eSPaolo Bonzini 352c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 353c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 354c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 355fa141081SMarc-André Lureau pd->config[MCH_HOST_BRIDGE_PAM0 + (DIV_ROUND_UP(i, 2))]); 356c0907c9eSPaolo Bonzini } 357c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 358c0907c9eSPaolo Bonzini } 359c0907c9eSPaolo Bonzini 360c0907c9eSPaolo Bonzini /* SMRAM */ 361c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 362c0907c9eSPaolo Bonzini { 363ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 36464130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 365bafc90bdSGerd Hoffmann uint32_t tseg_size; 366ce88812fSHu Tao 36768c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 36868c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 36968c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 37068c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 37168c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 37268c77acfSGerd Hoffmann } 37368c77acfSGerd Hoffmann 374c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 37564130fa4SPaolo Bonzini 37664130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 37764130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 37864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 37964130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 38064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 38164130fa4SPaolo Bonzini } else { 38264130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 38364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 38464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 38564130fa4SPaolo Bonzini } 38664130fa4SPaolo Bonzini 38764130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 38864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 38964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 39064130fa4SPaolo Bonzini } else { 39164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 39264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 39364130fa4SPaolo Bonzini } 39464130fa4SPaolo Bonzini 395bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 396bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 397bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 398bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 399bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 400bafc90bdSGerd Hoffmann break; 401bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 402bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 403bafc90bdSGerd Hoffmann break; 404bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 405bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 406bafc90bdSGerd Hoffmann break; 407bafc90bdSGerd Hoffmann default: 4082f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 409bafc90bdSGerd Hoffmann break; 410bafc90bdSGerd Hoffmann } 411bafc90bdSGerd Hoffmann } else { 412bafc90bdSGerd Hoffmann tseg_size = 0; 413bafc90bdSGerd Hoffmann } 414bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 415bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 416bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 417bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 418bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 419bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 420bafc90bdSGerd Hoffmann 421bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 422bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 423bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 424bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 425bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 426bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 427bafc90bdSGerd Hoffmann 428c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 429c0907c9eSPaolo Bonzini } 430c0907c9eSPaolo Bonzini 4312f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4322f295167SLaszlo Ersek { 4332f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4342f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4352f295167SLaszlo Ersek 4362f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4372f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4382f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4392f295167SLaszlo Ersek } 4402f295167SLaszlo Ersek } 4412f295167SLaszlo Ersek 442c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 443c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 444c0907c9eSPaolo Bonzini { 445c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 446c0907c9eSPaolo Bonzini 447c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 448c0907c9eSPaolo Bonzini 449c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 450c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 451c0907c9eSPaolo Bonzini mch_update_pam(mch); 452c0907c9eSPaolo Bonzini } 453c0907c9eSPaolo Bonzini 454c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 455c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 456c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 457c0907c9eSPaolo Bonzini } 458c0907c9eSPaolo Bonzini 459263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 460263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 461c0907c9eSPaolo Bonzini mch_update_smram(mch); 462c0907c9eSPaolo Bonzini } 4632f295167SLaszlo Ersek 4642f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4652f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4662f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4672f295167SLaszlo Ersek } 468c0907c9eSPaolo Bonzini } 469c0907c9eSPaolo Bonzini 470c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 471c0907c9eSPaolo Bonzini { 472c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 473c0907c9eSPaolo Bonzini mch_update_pam(mch); 474c0907c9eSPaolo Bonzini mch_update_smram(mch); 4752f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 476c0907c9eSPaolo Bonzini } 477c0907c9eSPaolo Bonzini 478c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 479c0907c9eSPaolo Bonzini { 480c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 481c0907c9eSPaolo Bonzini mch_update(mch); 482c0907c9eSPaolo Bonzini return 0; 483c0907c9eSPaolo Bonzini } 484c0907c9eSPaolo Bonzini 485c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 486c0907c9eSPaolo Bonzini .name = "mch", 487c0907c9eSPaolo Bonzini .version_id = 1, 488c0907c9eSPaolo Bonzini .minimum_version_id = 1, 489c0907c9eSPaolo Bonzini .post_load = mch_post_load, 490c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 491ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 492f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 493f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 494f809c605SPaolo Bonzini */ 495f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 496c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 497c0907c9eSPaolo Bonzini } 498c0907c9eSPaolo Bonzini }; 499c0907c9eSPaolo Bonzini 500c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 501c0907c9eSPaolo Bonzini { 502c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 503c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 504c0907c9eSPaolo Bonzini 505c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 506c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 507c0907c9eSPaolo Bonzini 508263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 50977447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 510b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 511b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 512c0907c9eSPaolo Bonzini 5132f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5142f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5152f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5162f295167SLaszlo Ersek } 5172f295167SLaszlo Ersek 518c0907c9eSPaolo Bonzini mch_update(mch); 519c0907c9eSPaolo Bonzini } 520c0907c9eSPaolo Bonzini 5219af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 522c0907c9eSPaolo Bonzini { 523c0907c9eSPaolo Bonzini int i; 524c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 525c0907c9eSPaolo Bonzini 5262f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5272f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5282f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5292f295167SLaszlo Ersek return; 5302f295167SLaszlo Ersek } 5312f295167SLaszlo Ersek 53283d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 53383d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 53483d08f26SMichael S. Tsirkin mch->pci_address_space); 53539848901SIgor Mammedov 536fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 53740c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 538c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 539c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 540c0907c9eSPaolo Bonzini &mch->smram_region, 1); 541fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 542fe6567d5SPaolo Bonzini 54364130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 54464130fa4SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 54564130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 54664130fa4SPaolo Bonzini &mch->open_high_smram, 1); 54764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 54864130fa4SPaolo Bonzini 549fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 550fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 551fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 552fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 553f809c605SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 554fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 555fe6567d5SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 55664130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 55764130fa4SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 55864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 55964130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 560bafc90bdSGerd Hoffmann 561bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 562bafc90bdSGerd Hoffmann &tseg_blackhole_ops, NULL, 563bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 564bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 565bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 566bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 567bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 568bafc90bdSGerd Hoffmann 569bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 570bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 571bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 572bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 573bafc90bdSGerd Hoffmann &mch->tseg_window); 574fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 575fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 576fe6567d5SPaolo Bonzini 577ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 578ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 579ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 580c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 581ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 582ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 583ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 584c0907c9eSPaolo Bonzini } 585c0907c9eSPaolo Bonzini } 586c0907c9eSPaolo Bonzini 5876f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 5886f1426abSMichael S. Tsirkin { 5896f1426abSMichael S. Tsirkin bool ambiguous; 5906f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 5916f1426abSMichael S. Tsirkin if (!o) { 5926f1426abSMichael S. Tsirkin return 0; 5936f1426abSMichael S. Tsirkin } 5946f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 5956f1426abSMichael S. Tsirkin } 5966f1426abSMichael S. Tsirkin 5972f295167SLaszlo Ersek static Property mch_props[] = { 5982f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 5992f295167SLaszlo Ersek 16), 6002f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6012f295167SLaszlo Ersek }; 6022f295167SLaszlo Ersek 603c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 604c0907c9eSPaolo Bonzini { 605c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 606c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 607c0907c9eSPaolo Bonzini 6089af21dbeSMarkus Armbruster k->realize = mch_realize; 609c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 610c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6112f295167SLaszlo Ersek dc->props = mch_props; 612125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 613c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 614c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 615c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 616c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 617451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 618c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 61908c58f92SMarkus Armbruster /* 62008c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 62108c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 62208c58f92SMarkus Armbruster */ 623e90f2a8cSEduardo Habkost dc->user_creatable = false; 624c0907c9eSPaolo Bonzini } 625c0907c9eSPaolo Bonzini 626c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 627c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 628c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 629c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 630c0907c9eSPaolo Bonzini .class_init = mch_class_init, 631fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 632fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 633fd3b02c8SEduardo Habkost { }, 634fd3b02c8SEduardo Habkost }, 635c0907c9eSPaolo Bonzini }; 636c0907c9eSPaolo Bonzini 637c0907c9eSPaolo Bonzini static void q35_register(void) 638c0907c9eSPaolo Bonzini { 639c0907c9eSPaolo Bonzini type_register_static(&mch_info); 640c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 641c0907c9eSPaolo Bonzini } 642c0907c9eSPaolo Bonzini 643c0907c9eSPaolo Bonzini type_init(q35_register); 644