1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10c0907c9eSPaolo Bonzini * This is based on piix_pci.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30c0907c9eSPaolo Bonzini #include "hw/hw.h" 31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 32c0907c9eSPaolo Bonzini 33c0907c9eSPaolo Bonzini /**************************************************************************** 34c0907c9eSPaolo Bonzini * Q35 host 35c0907c9eSPaolo Bonzini */ 36c0907c9eSPaolo Bonzini 3762d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 38c0907c9eSPaolo Bonzini { 39ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 40ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4162d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 42c0907c9eSPaolo Bonzini 4362d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4462d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 45c0907c9eSPaolo Bonzini 4662d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 4762d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 48c0907c9eSPaolo Bonzini 49ce88812fSHu Tao if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 5062d92e43SHu Tao error_setg(errp, "failed to initialize pcie host"); 5162d92e43SHu Tao return; 52c0907c9eSPaolo Bonzini } 53ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 54c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 55c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 56ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 57c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 58c0907c9eSPaolo Bonzini } 59c0907c9eSPaolo Bonzini 60568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 61568f0690SDavid Gibson PCIBus *rootbus) 62568f0690SDavid Gibson { 63568f0690SDavid Gibson /* For backwards compat with old device paths */ 64568f0690SDavid Gibson return "0000"; 65568f0690SDavid Gibson } 66568f0690SDavid Gibson 67c0907c9eSPaolo Bonzini static Property mch_props[] = { 68ce88812fSHu Tao DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 69c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 70c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 71c0907c9eSPaolo Bonzini }; 72c0907c9eSPaolo Bonzini 73c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 74c0907c9eSPaolo Bonzini { 75c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 76568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 77c0907c9eSPaolo Bonzini 78568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 7962d92e43SHu Tao dc->realize = q35_host_realize; 80c0907c9eSPaolo Bonzini dc->props = mch_props; 81*125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 8268c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 83c0907c9eSPaolo Bonzini } 84c0907c9eSPaolo Bonzini 85c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 86c0907c9eSPaolo Bonzini { 87c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 8862d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 8962d92e43SHu Tao 9062d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 9162d92e43SHu Tao "pci-conf-idx", 4); 9262d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 9362d92e43SHu Tao "pci-conf-data", 4); 94c0907c9eSPaolo Bonzini 95c0907c9eSPaolo Bonzini object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 96c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 97c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 98c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 99c0907c9eSPaolo Bonzini } 100c0907c9eSPaolo Bonzini 101c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 102c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 103c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 104c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 105c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 106c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 107c0907c9eSPaolo Bonzini }; 108c0907c9eSPaolo Bonzini 109c0907c9eSPaolo Bonzini /**************************************************************************** 110c0907c9eSPaolo Bonzini * MCH D0:F0 111c0907c9eSPaolo Bonzini */ 112c0907c9eSPaolo Bonzini 113c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 114c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 115c0907c9eSPaolo Bonzini { 116ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 117ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 118ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 119c0907c9eSPaolo Bonzini 120c0907c9eSPaolo Bonzini uint64_t pciexbar; 121c0907c9eSPaolo Bonzini int enable; 122c0907c9eSPaolo Bonzini uint64_t addr; 123c0907c9eSPaolo Bonzini uint64_t addr_mask; 124c0907c9eSPaolo Bonzini uint32_t length; 125c0907c9eSPaolo Bonzini 126c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 127c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 128c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 129c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 130c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 131c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 132c0907c9eSPaolo Bonzini break; 133c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 134c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 135c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 136c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 137c0907c9eSPaolo Bonzini break; 138c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 139c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 140c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 141c0907c9eSPaolo Bonzini break; 142c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 143c0907c9eSPaolo Bonzini default: 144c0907c9eSPaolo Bonzini enable = 0; 145c0907c9eSPaolo Bonzini length = 0; 146c0907c9eSPaolo Bonzini abort(); 147c0907c9eSPaolo Bonzini break; 148c0907c9eSPaolo Bonzini } 149c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 150ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 151c0907c9eSPaolo Bonzini } 152c0907c9eSPaolo Bonzini 153c0907c9eSPaolo Bonzini /* PAM */ 154c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 155c0907c9eSPaolo Bonzini { 156ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 157c0907c9eSPaolo Bonzini int i; 158c0907c9eSPaolo Bonzini 159c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 160c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 161c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 162ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 163c0907c9eSPaolo Bonzini } 164c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 165c0907c9eSPaolo Bonzini } 166c0907c9eSPaolo Bonzini 167c0907c9eSPaolo Bonzini /* SMRAM */ 168c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 169c0907c9eSPaolo Bonzini { 170ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 171ce88812fSHu Tao 172c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 173ce88812fSHu Tao smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 174c0907c9eSPaolo Bonzini mch->smm_enabled); 175c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 176c0907c9eSPaolo Bonzini } 177c0907c9eSPaolo Bonzini 178c0907c9eSPaolo Bonzini static void mch_set_smm(int smm, void *arg) 179c0907c9eSPaolo Bonzini { 180c0907c9eSPaolo Bonzini MCHPCIState *mch = arg; 181ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 182c0907c9eSPaolo Bonzini 183c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 184ce88812fSHu Tao smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 185c0907c9eSPaolo Bonzini &mch->smram_region); 186c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 187c0907c9eSPaolo Bonzini } 188c0907c9eSPaolo Bonzini 189c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 190c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 191c0907c9eSPaolo Bonzini { 192c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 193c0907c9eSPaolo Bonzini 194c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 195c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 196c0907c9eSPaolo Bonzini 197c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 198c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 199c0907c9eSPaolo Bonzini mch_update_pam(mch); 200c0907c9eSPaolo Bonzini } 201c0907c9eSPaolo Bonzini 202c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 203c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 204c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 205c0907c9eSPaolo Bonzini } 206c0907c9eSPaolo Bonzini 207c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 208c0907c9eSPaolo Bonzini MCH_HOST_BRDIGE_SMRAM_SIZE)) { 209c0907c9eSPaolo Bonzini mch_update_smram(mch); 210c0907c9eSPaolo Bonzini } 211c0907c9eSPaolo Bonzini } 212c0907c9eSPaolo Bonzini 213c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 214c0907c9eSPaolo Bonzini { 215c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 216c0907c9eSPaolo Bonzini mch_update_pam(mch); 217c0907c9eSPaolo Bonzini mch_update_smram(mch); 218c0907c9eSPaolo Bonzini } 219c0907c9eSPaolo Bonzini 220c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 221c0907c9eSPaolo Bonzini { 222c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 223c0907c9eSPaolo Bonzini mch_update(mch); 224c0907c9eSPaolo Bonzini return 0; 225c0907c9eSPaolo Bonzini } 226c0907c9eSPaolo Bonzini 227c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 228c0907c9eSPaolo Bonzini .name = "mch", 229c0907c9eSPaolo Bonzini .version_id = 1, 230c0907c9eSPaolo Bonzini .minimum_version_id = 1, 231c0907c9eSPaolo Bonzini .minimum_version_id_old = 1, 232c0907c9eSPaolo Bonzini .post_load = mch_post_load, 233c0907c9eSPaolo Bonzini .fields = (VMStateField []) { 234ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 235c0907c9eSPaolo Bonzini VMSTATE_UINT8(smm_enabled, MCHPCIState), 236c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 237c0907c9eSPaolo Bonzini } 238c0907c9eSPaolo Bonzini }; 239c0907c9eSPaolo Bonzini 240c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 241c0907c9eSPaolo Bonzini { 242c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 243c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 244c0907c9eSPaolo Bonzini 245c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 246c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 247c0907c9eSPaolo Bonzini 248c0907c9eSPaolo Bonzini d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 249c0907c9eSPaolo Bonzini 250c0907c9eSPaolo Bonzini mch_update(mch); 251c0907c9eSPaolo Bonzini } 252c0907c9eSPaolo Bonzini 253c0907c9eSPaolo Bonzini static int mch_init(PCIDevice *d) 254c0907c9eSPaolo Bonzini { 255c0907c9eSPaolo Bonzini int i; 256c0907c9eSPaolo Bonzini hwaddr pci_hole64_size; 257c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 258c0907c9eSPaolo Bonzini 2593459a625SMichael S. Tsirkin /* Leave enough space for the biggest MCFG BAR */ 2603459a625SMichael S. Tsirkin /* TODO: this matches current bios behaviour, but 2613459a625SMichael S. Tsirkin * it's not a power of two, which means an MTRR 2623459a625SMichael S. Tsirkin * can't cover it exactly. 2633459a625SMichael S. Tsirkin */ 2643459a625SMichael S. Tsirkin mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 2653459a625SMichael S. Tsirkin MCH_HOST_BRIDGE_PCIEXBAR_MAX; 2663459a625SMichael S. Tsirkin 267c0907c9eSPaolo Bonzini /* setup pci memory regions */ 26840c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 269c0907c9eSPaolo Bonzini mch->pci_address_space, 270c0907c9eSPaolo Bonzini mch->below_4g_mem_size, 271c0907c9eSPaolo Bonzini 0x100000000ULL - mch->below_4g_mem_size); 272c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 273c0907c9eSPaolo Bonzini &mch->pci_hole); 274c0907c9eSPaolo Bonzini pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : 275c0907c9eSPaolo Bonzini ((uint64_t)1 << 62)); 27640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 277c0907c9eSPaolo Bonzini mch->pci_address_space, 278c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 279c0907c9eSPaolo Bonzini pci_hole64_size); 280c0907c9eSPaolo Bonzini if (pci_hole64_size) { 281c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, 282c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 283c0907c9eSPaolo Bonzini &mch->pci_hole_64bit); 284c0907c9eSPaolo Bonzini } 285c0907c9eSPaolo Bonzini /* smram */ 286c0907c9eSPaolo Bonzini cpu_smm_register(&mch_set_smm, mch); 28740c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 288c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 289c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 290c0907c9eSPaolo Bonzini &mch->smram_region, 1); 291c0907c9eSPaolo Bonzini memory_region_set_enabled(&mch->smram_region, false); 2923cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 293c0907c9eSPaolo Bonzini &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 294c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 2953cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 296c0907c9eSPaolo Bonzini &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 297c0907c9eSPaolo Bonzini PAM_EXPAN_SIZE); 298c0907c9eSPaolo Bonzini } 299c0907c9eSPaolo Bonzini return 0; 300c0907c9eSPaolo Bonzini } 301c0907c9eSPaolo Bonzini 302c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 303c0907c9eSPaolo Bonzini { 304c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 305c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 306c0907c9eSPaolo Bonzini 307c0907c9eSPaolo Bonzini k->init = mch_init; 308c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 309c0907c9eSPaolo Bonzini dc->reset = mch_reset; 310*125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 311c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 312c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 313c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 314c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 315c0907c9eSPaolo Bonzini k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 316c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 317c0907c9eSPaolo Bonzini } 318c0907c9eSPaolo Bonzini 319c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 320c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 321c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 322c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 323c0907c9eSPaolo Bonzini .class_init = mch_class_init, 324c0907c9eSPaolo Bonzini }; 325c0907c9eSPaolo Bonzini 326c0907c9eSPaolo Bonzini static void q35_register(void) 327c0907c9eSPaolo Bonzini { 328c0907c9eSPaolo Bonzini type_register_static(&mch_info); 329c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 330c0907c9eSPaolo Bonzini } 331c0907c9eSPaolo Bonzini 332c0907c9eSPaolo Bonzini type_init(q35_register); 333