1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10c0907c9eSPaolo Bonzini * This is based on piix_pci.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30c0907c9eSPaolo Bonzini #include "hw/hw.h" 31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 32*39848901SIgor Mammedov #include "qapi/visitor.h" 33c0907c9eSPaolo Bonzini 34c0907c9eSPaolo Bonzini /**************************************************************************** 35c0907c9eSPaolo Bonzini * Q35 host 36c0907c9eSPaolo Bonzini */ 37c0907c9eSPaolo Bonzini 3862d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 39c0907c9eSPaolo Bonzini { 40ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 41ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4262d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 43c0907c9eSPaolo Bonzini 4462d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4562d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46c0907c9eSPaolo Bonzini 4762d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 4862d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 49c0907c9eSPaolo Bonzini 50ce88812fSHu Tao if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 5162d92e43SHu Tao error_setg(errp, "failed to initialize pcie host"); 5262d92e43SHu Tao return; 53c0907c9eSPaolo Bonzini } 54ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 55c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 56c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 57ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 58c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 59c0907c9eSPaolo Bonzini } 60c0907c9eSPaolo Bonzini 61568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 62568f0690SDavid Gibson PCIBus *rootbus) 63568f0690SDavid Gibson { 64568f0690SDavid Gibson /* For backwards compat with old device paths */ 65568f0690SDavid Gibson return "0000"; 66568f0690SDavid Gibson } 67568f0690SDavid Gibson 68*39848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 69*39848901SIgor Mammedov void *opaque, const char *name, 70*39848901SIgor Mammedov Error **errp) 71*39848901SIgor Mammedov { 72*39848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 73*39848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.begin; 74*39848901SIgor Mammedov 75*39848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 76*39848901SIgor Mammedov } 77*39848901SIgor Mammedov 78*39848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 79*39848901SIgor Mammedov void *opaque, const char *name, 80*39848901SIgor Mammedov Error **errp) 81*39848901SIgor Mammedov { 82*39848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 83*39848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.end; 84*39848901SIgor Mammedov 85*39848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 86*39848901SIgor Mammedov } 87*39848901SIgor Mammedov 88*39848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 89*39848901SIgor Mammedov void *opaque, const char *name, 90*39848901SIgor Mammedov Error **errp) 91*39848901SIgor Mammedov { 92*39848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 93*39848901SIgor Mammedov 94*39848901SIgor Mammedov visit_type_uint64(v, &s->mch.pci_info.w64.begin, name, errp); 95*39848901SIgor Mammedov } 96*39848901SIgor Mammedov 97*39848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 98*39848901SIgor Mammedov void *opaque, const char *name, 99*39848901SIgor Mammedov Error **errp) 100*39848901SIgor Mammedov { 101*39848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 102*39848901SIgor Mammedov 103*39848901SIgor Mammedov visit_type_uint64(v, &s->mch.pci_info.w64.end, name, errp); 104*39848901SIgor Mammedov } 105*39848901SIgor Mammedov 106c0907c9eSPaolo Bonzini static Property mch_props[] = { 107ce88812fSHu Tao DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 108c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 109*39848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 110*39848901SIgor Mammedov mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 111c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 112c0907c9eSPaolo Bonzini }; 113c0907c9eSPaolo Bonzini 114c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 115c0907c9eSPaolo Bonzini { 116c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 117568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 118c0907c9eSPaolo Bonzini 119568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 12062d92e43SHu Tao dc->realize = q35_host_realize; 121c0907c9eSPaolo Bonzini dc->props = mch_props; 122125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 12368c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 124c0907c9eSPaolo Bonzini } 125c0907c9eSPaolo Bonzini 126c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 127c0907c9eSPaolo Bonzini { 128c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 12962d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 13062d92e43SHu Tao 13162d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 13262d92e43SHu Tao "pci-conf-idx", 4); 13362d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 13462d92e43SHu Tao "pci-conf-data", 4); 135c0907c9eSPaolo Bonzini 136c0907c9eSPaolo Bonzini object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 137c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 138c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 139c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 140*39848901SIgor Mammedov 141*39848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 142*39848901SIgor Mammedov q35_host_get_pci_hole_start, 143*39848901SIgor Mammedov NULL, NULL, NULL, NULL); 144*39848901SIgor Mammedov 145*39848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 146*39848901SIgor Mammedov q35_host_get_pci_hole_end, 147*39848901SIgor Mammedov NULL, NULL, NULL, NULL); 148*39848901SIgor Mammedov 149*39848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 150*39848901SIgor Mammedov q35_host_get_pci_hole64_start, 151*39848901SIgor Mammedov NULL, NULL, NULL, NULL); 152*39848901SIgor Mammedov 153*39848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 154*39848901SIgor Mammedov q35_host_get_pci_hole64_end, 155*39848901SIgor Mammedov NULL, NULL, NULL, NULL); 156*39848901SIgor Mammedov 157*39848901SIgor Mammedov /* Leave enough space for the biggest MCFG BAR */ 158*39848901SIgor Mammedov /* TODO: this matches current bios behaviour, but 159*39848901SIgor Mammedov * it's not a power of two, which means an MTRR 160*39848901SIgor Mammedov * can't cover it exactly. 161*39848901SIgor Mammedov */ 162*39848901SIgor Mammedov s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 163*39848901SIgor Mammedov MCH_HOST_BRIDGE_PCIEXBAR_MAX; 164*39848901SIgor Mammedov s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 165c0907c9eSPaolo Bonzini } 166c0907c9eSPaolo Bonzini 167c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 168c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 169c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 170c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 171c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 172c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 173c0907c9eSPaolo Bonzini }; 174c0907c9eSPaolo Bonzini 175c0907c9eSPaolo Bonzini /**************************************************************************** 176c0907c9eSPaolo Bonzini * MCH D0:F0 177c0907c9eSPaolo Bonzini */ 178c0907c9eSPaolo Bonzini 179c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 180c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 181c0907c9eSPaolo Bonzini { 182ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 183ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 184ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 185c0907c9eSPaolo Bonzini 186c0907c9eSPaolo Bonzini uint64_t pciexbar; 187c0907c9eSPaolo Bonzini int enable; 188c0907c9eSPaolo Bonzini uint64_t addr; 189c0907c9eSPaolo Bonzini uint64_t addr_mask; 190c0907c9eSPaolo Bonzini uint32_t length; 191c0907c9eSPaolo Bonzini 192c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 193c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 194c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 195c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 196c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 197c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 198c0907c9eSPaolo Bonzini break; 199c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 200c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 201c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 202c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 203c0907c9eSPaolo Bonzini break; 204c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 205c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 206c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 207c0907c9eSPaolo Bonzini break; 208c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 209c0907c9eSPaolo Bonzini default: 210c0907c9eSPaolo Bonzini enable = 0; 211c0907c9eSPaolo Bonzini length = 0; 212c0907c9eSPaolo Bonzini abort(); 213c0907c9eSPaolo Bonzini break; 214c0907c9eSPaolo Bonzini } 215c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 216ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 217c0907c9eSPaolo Bonzini } 218c0907c9eSPaolo Bonzini 219c0907c9eSPaolo Bonzini /* PAM */ 220c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 221c0907c9eSPaolo Bonzini { 222ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 223c0907c9eSPaolo Bonzini int i; 224c0907c9eSPaolo Bonzini 225c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 226c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 227c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 228ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 229c0907c9eSPaolo Bonzini } 230c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 231c0907c9eSPaolo Bonzini } 232c0907c9eSPaolo Bonzini 233c0907c9eSPaolo Bonzini /* SMRAM */ 234c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 235c0907c9eSPaolo Bonzini { 236ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 237ce88812fSHu Tao 238c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 239ce88812fSHu Tao smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 240c0907c9eSPaolo Bonzini mch->smm_enabled); 241c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 242c0907c9eSPaolo Bonzini } 243c0907c9eSPaolo Bonzini 244c0907c9eSPaolo Bonzini static void mch_set_smm(int smm, void *arg) 245c0907c9eSPaolo Bonzini { 246c0907c9eSPaolo Bonzini MCHPCIState *mch = arg; 247ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 248c0907c9eSPaolo Bonzini 249c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 250ce88812fSHu Tao smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 251c0907c9eSPaolo Bonzini &mch->smram_region); 252c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 253c0907c9eSPaolo Bonzini } 254c0907c9eSPaolo Bonzini 255c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 256c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 257c0907c9eSPaolo Bonzini { 258c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 259c0907c9eSPaolo Bonzini 260c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 261c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 262c0907c9eSPaolo Bonzini 263c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 264c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 265c0907c9eSPaolo Bonzini mch_update_pam(mch); 266c0907c9eSPaolo Bonzini } 267c0907c9eSPaolo Bonzini 268c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 269c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 270c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 271c0907c9eSPaolo Bonzini } 272c0907c9eSPaolo Bonzini 273c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 274c0907c9eSPaolo Bonzini MCH_HOST_BRDIGE_SMRAM_SIZE)) { 275c0907c9eSPaolo Bonzini mch_update_smram(mch); 276c0907c9eSPaolo Bonzini } 277c0907c9eSPaolo Bonzini } 278c0907c9eSPaolo Bonzini 279c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 280c0907c9eSPaolo Bonzini { 281c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 282c0907c9eSPaolo Bonzini mch_update_pam(mch); 283c0907c9eSPaolo Bonzini mch_update_smram(mch); 284c0907c9eSPaolo Bonzini } 285c0907c9eSPaolo Bonzini 286c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 287c0907c9eSPaolo Bonzini { 288c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 289c0907c9eSPaolo Bonzini mch_update(mch); 290c0907c9eSPaolo Bonzini return 0; 291c0907c9eSPaolo Bonzini } 292c0907c9eSPaolo Bonzini 293c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 294c0907c9eSPaolo Bonzini .name = "mch", 295c0907c9eSPaolo Bonzini .version_id = 1, 296c0907c9eSPaolo Bonzini .minimum_version_id = 1, 297c0907c9eSPaolo Bonzini .minimum_version_id_old = 1, 298c0907c9eSPaolo Bonzini .post_load = mch_post_load, 299c0907c9eSPaolo Bonzini .fields = (VMStateField []) { 300ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 301c0907c9eSPaolo Bonzini VMSTATE_UINT8(smm_enabled, MCHPCIState), 302c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 303c0907c9eSPaolo Bonzini } 304c0907c9eSPaolo Bonzini }; 305c0907c9eSPaolo Bonzini 306c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 307c0907c9eSPaolo Bonzini { 308c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 309c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 310c0907c9eSPaolo Bonzini 311c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 312c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 313c0907c9eSPaolo Bonzini 314c0907c9eSPaolo Bonzini d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 315c0907c9eSPaolo Bonzini 316c0907c9eSPaolo Bonzini mch_update(mch); 317c0907c9eSPaolo Bonzini } 318c0907c9eSPaolo Bonzini 319c0907c9eSPaolo Bonzini static int mch_init(PCIDevice *d) 320c0907c9eSPaolo Bonzini { 321c0907c9eSPaolo Bonzini int i; 322c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 323c0907c9eSPaolo Bonzini 324c0907c9eSPaolo Bonzini /* setup pci memory regions */ 32540c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 326c0907c9eSPaolo Bonzini mch->pci_address_space, 327c0907c9eSPaolo Bonzini mch->below_4g_mem_size, 328c0907c9eSPaolo Bonzini 0x100000000ULL - mch->below_4g_mem_size); 329c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 330c0907c9eSPaolo Bonzini &mch->pci_hole); 331*39848901SIgor Mammedov 332*39848901SIgor Mammedov pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, 333*39848901SIgor Mammedov mch->pci_hole64_size); 33440c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 335c0907c9eSPaolo Bonzini mch->pci_address_space, 336*39848901SIgor Mammedov mch->pci_info.w64.begin, 337*39848901SIgor Mammedov mch->pci_hole64_size); 338*39848901SIgor Mammedov if (mch->pci_hole64_size) { 339c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, 340*39848901SIgor Mammedov mch->pci_info.w64.begin, 341c0907c9eSPaolo Bonzini &mch->pci_hole_64bit); 342c0907c9eSPaolo Bonzini } 343c0907c9eSPaolo Bonzini /* smram */ 344c0907c9eSPaolo Bonzini cpu_smm_register(&mch_set_smm, mch); 34540c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 346c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 347c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 348c0907c9eSPaolo Bonzini &mch->smram_region, 1); 349c0907c9eSPaolo Bonzini memory_region_set_enabled(&mch->smram_region, false); 3503cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 351c0907c9eSPaolo Bonzini &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 352c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 3533cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 354c0907c9eSPaolo Bonzini &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 355c0907c9eSPaolo Bonzini PAM_EXPAN_SIZE); 356c0907c9eSPaolo Bonzini } 357c0907c9eSPaolo Bonzini return 0; 358c0907c9eSPaolo Bonzini } 359c0907c9eSPaolo Bonzini 360c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 361c0907c9eSPaolo Bonzini { 362c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 363c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 364c0907c9eSPaolo Bonzini 365c0907c9eSPaolo Bonzini k->init = mch_init; 366c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 367c0907c9eSPaolo Bonzini dc->reset = mch_reset; 368125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 369c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 370c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 371c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 372c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 373c0907c9eSPaolo Bonzini k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 374c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 375c0907c9eSPaolo Bonzini } 376c0907c9eSPaolo Bonzini 377c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 378c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 379c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 380c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 381c0907c9eSPaolo Bonzini .class_init = mch_class_init, 382c0907c9eSPaolo Bonzini }; 383c0907c9eSPaolo Bonzini 384c0907c9eSPaolo Bonzini static void q35_register(void) 385c0907c9eSPaolo Bonzini { 386c0907c9eSPaolo Bonzini type_register_static(&mch_info); 387c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 388c0907c9eSPaolo Bonzini } 389c0907c9eSPaolo Bonzini 390c0907c9eSPaolo Bonzini type_init(q35_register); 391