1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30b6a0aa05SPeter Maydell #include "qemu/osdep.h" 31c0907c9eSPaolo Bonzini #include "hw/hw.h" 32c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 33da34e65cSMarkus Armbruster #include "qapi/error.h" 3439848901SIgor Mammedov #include "qapi/visitor.h" 35c0907c9eSPaolo Bonzini 36c0907c9eSPaolo Bonzini /**************************************************************************** 37c0907c9eSPaolo Bonzini * Q35 host 38c0907c9eSPaolo Bonzini */ 39c0907c9eSPaolo Bonzini 4062d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 41c0907c9eSPaolo Bonzini { 42ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 43ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4462d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 45c0907c9eSPaolo Bonzini 4662d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4762d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 48c0907c9eSPaolo Bonzini 4962d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5062d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51c0907c9eSPaolo Bonzini 52ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 53c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 54c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 55621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 56ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 57c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 58c0907c9eSPaolo Bonzini } 59c0907c9eSPaolo Bonzini 60568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 61568f0690SDavid Gibson PCIBus *rootbus) 62568f0690SDavid Gibson { 6304c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 6404c7d8b8SCole Robinson 65568f0690SDavid Gibson /* For backwards compat with old device paths */ 6604c7d8b8SCole Robinson if (s->mch.short_root_bus) { 67568f0690SDavid Gibson return "0000"; 68568f0690SDavid Gibson } 6904c7d8b8SCole Robinson return "0000:00"; 7004c7d8b8SCole Robinson } 71568f0690SDavid Gibson 7239848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 73d7bce999SEric Blake const char *name, void *opaque, 7439848901SIgor Mammedov Error **errp) 7539848901SIgor Mammedov { 7639848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 77a0efbf16SMarkus Armbruster uint64_t val64; 78a0efbf16SMarkus Armbruster uint32_t value; 7939848901SIgor Mammedov 80a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 81a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 82a0efbf16SMarkus Armbruster value = val64; 83a0efbf16SMarkus Armbruster assert(value == val64); 8451e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 8539848901SIgor Mammedov } 8639848901SIgor Mammedov 8739848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 88d7bce999SEric Blake const char *name, void *opaque, 8939848901SIgor Mammedov Error **errp) 9039848901SIgor Mammedov { 9139848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 92a0efbf16SMarkus Armbruster uint64_t val64; 93a0efbf16SMarkus Armbruster uint32_t value; 9439848901SIgor Mammedov 95a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 96a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 97a0efbf16SMarkus Armbruster value = val64; 98a0efbf16SMarkus Armbruster assert(value == val64); 9951e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 10039848901SIgor Mammedov } 10139848901SIgor Mammedov 10239848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 103d7bce999SEric Blake const char *name, void *opaque, 10439848901SIgor Mammedov Error **errp) 10539848901SIgor Mammedov { 1068b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1078b42d730SMichael S. Tsirkin Range w64; 108a0efbf16SMarkus Armbruster uint64_t value; 10939848901SIgor Mammedov 1108b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 111a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 112a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 11339848901SIgor Mammedov } 11439848901SIgor Mammedov 11539848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 116d7bce999SEric Blake const char *name, void *opaque, 11739848901SIgor Mammedov Error **errp) 11839848901SIgor Mammedov { 1198b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1208b42d730SMichael S. Tsirkin Range w64; 121a0efbf16SMarkus Armbruster uint64_t value; 12239848901SIgor Mammedov 1238b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 124a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 125a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 12639848901SIgor Mammedov } 12739848901SIgor Mammedov 128d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 129d7bce999SEric Blake void *opaque, Error **errp) 130cbcaf79eSMichael S. Tsirkin { 131cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 132cbcaf79eSMichael S. Tsirkin 133d015c4eaSMarc-André Lureau visit_type_uint64(v, name, &e->size, errp); 134cbcaf79eSMichael S. Tsirkin } 135cbcaf79eSMichael S. Tsirkin 136c0907c9eSPaolo Bonzini static Property mch_props[] = { 13787f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 138c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 13939848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 14039848901SIgor Mammedov mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 14104c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 142401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 143401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 144401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 145401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 146c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 147c0907c9eSPaolo Bonzini }; 148c0907c9eSPaolo Bonzini 149c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 150c0907c9eSPaolo Bonzini { 151c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 152568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 153c0907c9eSPaolo Bonzini 154568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 15562d92e43SHu Tao dc->realize = q35_host_realize; 156c0907c9eSPaolo Bonzini dc->props = mch_props; 157bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 158e90f2a8cSEduardo Habkost dc->user_creatable = false; 159125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 16068c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 161c0907c9eSPaolo Bonzini } 162c0907c9eSPaolo Bonzini 163c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 164c0907c9eSPaolo Bonzini { 165c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 16662d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 16762d92e43SHu Tao 16862d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 16962d92e43SHu Tao "pci-conf-idx", 4); 17062d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 17162d92e43SHu Tao "pci-conf-data", 4); 172c0907c9eSPaolo Bonzini 173213f0c4fSAndreas Färber object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 174c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 175*446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 176c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 17739848901SIgor Mammedov 1781e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 17939848901SIgor Mammedov q35_host_get_pci_hole_start, 18039848901SIgor Mammedov NULL, NULL, NULL, NULL); 18139848901SIgor Mammedov 1821e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 18339848901SIgor Mammedov q35_host_get_pci_hole_end, 18439848901SIgor Mammedov NULL, NULL, NULL, NULL); 18539848901SIgor Mammedov 1861e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 18739848901SIgor Mammedov q35_host_get_pci_hole64_start, 18839848901SIgor Mammedov NULL, NULL, NULL, NULL); 18939848901SIgor Mammedov 1901e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 19139848901SIgor Mammedov q35_host_get_pci_hole64_end, 19239848901SIgor Mammedov NULL, NULL, NULL, NULL); 19339848901SIgor Mammedov 1941e507bb0SMarc-André Lureau object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 195cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 196cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 197cbcaf79eSMichael S. Tsirkin 198401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 199401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 200401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 201401f2f3eSEfimov Vasily 202401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 203401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 204401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 205401f2f3eSEfimov Vasily 206401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 207401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 208401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 209401f2f3eSEfimov Vasily 210401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 211401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 212401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 213401f2f3eSEfimov Vasily 21439848901SIgor Mammedov /* Leave enough space for the biggest MCFG BAR */ 21539848901SIgor Mammedov /* TODO: this matches current bios behaviour, but 21639848901SIgor Mammedov * it's not a power of two, which means an MTRR 21739848901SIgor Mammedov * can't cover it exactly. 21839848901SIgor Mammedov */ 219a0efbf16SMarkus Armbruster range_set_bounds(&s->mch.pci_hole, 220a0efbf16SMarkus Armbruster MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 221a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 222c0907c9eSPaolo Bonzini } 223c0907c9eSPaolo Bonzini 224c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 225c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 226c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 227c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 228c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 229c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 230c0907c9eSPaolo Bonzini }; 231c0907c9eSPaolo Bonzini 232c0907c9eSPaolo Bonzini /**************************************************************************** 233c0907c9eSPaolo Bonzini * MCH D0:F0 234c0907c9eSPaolo Bonzini */ 235c0907c9eSPaolo Bonzini 236bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 237bafc90bdSGerd Hoffmann { 238bafc90bdSGerd Hoffmann return 0xffffffff; 239bafc90bdSGerd Hoffmann } 240bafc90bdSGerd Hoffmann 241bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 242bafc90bdSGerd Hoffmann unsigned width) 243bafc90bdSGerd Hoffmann { 244bafc90bdSGerd Hoffmann /* nothing */ 245bafc90bdSGerd Hoffmann } 246bafc90bdSGerd Hoffmann 247bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = { 248bafc90bdSGerd Hoffmann .read = tseg_blackhole_read, 249bafc90bdSGerd Hoffmann .write = tseg_blackhole_write, 250bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 251bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 252bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 253bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 254bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 255bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 256bafc90bdSGerd Hoffmann }; 257bafc90bdSGerd Hoffmann 258c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 259c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 260c0907c9eSPaolo Bonzini { 261ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 262ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 263ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 264c0907c9eSPaolo Bonzini 265c0907c9eSPaolo Bonzini uint64_t pciexbar; 266c0907c9eSPaolo Bonzini int enable; 267c0907c9eSPaolo Bonzini uint64_t addr; 268c0907c9eSPaolo Bonzini uint64_t addr_mask; 269c0907c9eSPaolo Bonzini uint32_t length; 270c0907c9eSPaolo Bonzini 271c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 272c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 273c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 274c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 275c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 276c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 277c0907c9eSPaolo Bonzini break; 278c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 279c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 280c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 281c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 282c0907c9eSPaolo Bonzini break; 283c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 284c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 285c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 286c0907c9eSPaolo Bonzini break; 287c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 288c0907c9eSPaolo Bonzini default: 289c0907c9eSPaolo Bonzini abort(); 290c0907c9eSPaolo Bonzini } 291c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 292ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 293636228a8SMichael S. Tsirkin /* Leave enough space for the MCFG BAR */ 294636228a8SMichael S. Tsirkin /* 295636228a8SMichael S. Tsirkin * TODO: this matches current bios behaviour, but it's not a power of two, 296636228a8SMichael S. Tsirkin * which means an MTRR can't cover it exactly. 297636228a8SMichael S. Tsirkin */ 298636228a8SMichael S. Tsirkin if (enable) { 299a0efbf16SMarkus Armbruster range_set_bounds(&mch->pci_hole, 300a0efbf16SMarkus Armbruster addr + length, 301a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 302636228a8SMichael S. Tsirkin } else { 303a0efbf16SMarkus Armbruster range_set_bounds(&mch->pci_hole, 304a0efbf16SMarkus Armbruster MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 305a0efbf16SMarkus Armbruster IO_APIC_DEFAULT_ADDRESS - 1); 306636228a8SMichael S. Tsirkin } 307c0907c9eSPaolo Bonzini } 308c0907c9eSPaolo Bonzini 309c0907c9eSPaolo Bonzini /* PAM */ 310c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 311c0907c9eSPaolo Bonzini { 312ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 313c0907c9eSPaolo Bonzini int i; 314c0907c9eSPaolo Bonzini 315c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 316c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 317c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 318ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 319c0907c9eSPaolo Bonzini } 320c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 321c0907c9eSPaolo Bonzini } 322c0907c9eSPaolo Bonzini 323c0907c9eSPaolo Bonzini /* SMRAM */ 324c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 325c0907c9eSPaolo Bonzini { 326ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 32764130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 328bafc90bdSGerd Hoffmann uint32_t tseg_size; 329ce88812fSHu Tao 33068c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 33168c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 33268c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 33368c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 33468c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 33568c77acfSGerd Hoffmann } 33668c77acfSGerd Hoffmann 337c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 33864130fa4SPaolo Bonzini 33964130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 34064130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 34164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 34264130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 34364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 34464130fa4SPaolo Bonzini } else { 34564130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 34664130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 34764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 34864130fa4SPaolo Bonzini } 34964130fa4SPaolo Bonzini 35064130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 35164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 35264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 35364130fa4SPaolo Bonzini } else { 35464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 35564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 35664130fa4SPaolo Bonzini } 35764130fa4SPaolo Bonzini 358bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 359bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 360bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 361bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 362bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 363bafc90bdSGerd Hoffmann break; 364bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 365bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 366bafc90bdSGerd Hoffmann break; 367bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 368bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 369bafc90bdSGerd Hoffmann break; 370bafc90bdSGerd Hoffmann default: 371bafc90bdSGerd Hoffmann tseg_size = 0; 372bafc90bdSGerd Hoffmann break; 373bafc90bdSGerd Hoffmann } 374bafc90bdSGerd Hoffmann } else { 375bafc90bdSGerd Hoffmann tseg_size = 0; 376bafc90bdSGerd Hoffmann } 377bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 378bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 379bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 380bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 381bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 382bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 383bafc90bdSGerd Hoffmann 384bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 385bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 386bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 387bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 388bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 389bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 390bafc90bdSGerd Hoffmann 391c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 392c0907c9eSPaolo Bonzini } 393c0907c9eSPaolo Bonzini 394c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 395c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 396c0907c9eSPaolo Bonzini { 397c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 398c0907c9eSPaolo Bonzini 399c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 400c0907c9eSPaolo Bonzini 401c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 402c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 403c0907c9eSPaolo Bonzini mch_update_pam(mch); 404c0907c9eSPaolo Bonzini } 405c0907c9eSPaolo Bonzini 406c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 407c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 408c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 409c0907c9eSPaolo Bonzini } 410c0907c9eSPaolo Bonzini 411263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 412263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 413c0907c9eSPaolo Bonzini mch_update_smram(mch); 414c0907c9eSPaolo Bonzini } 415c0907c9eSPaolo Bonzini } 416c0907c9eSPaolo Bonzini 417c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 418c0907c9eSPaolo Bonzini { 419c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 420c0907c9eSPaolo Bonzini mch_update_pam(mch); 421c0907c9eSPaolo Bonzini mch_update_smram(mch); 422c0907c9eSPaolo Bonzini } 423c0907c9eSPaolo Bonzini 424c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 425c0907c9eSPaolo Bonzini { 426c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 427c0907c9eSPaolo Bonzini mch_update(mch); 428c0907c9eSPaolo Bonzini return 0; 429c0907c9eSPaolo Bonzini } 430c0907c9eSPaolo Bonzini 431c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 432c0907c9eSPaolo Bonzini .name = "mch", 433c0907c9eSPaolo Bonzini .version_id = 1, 434c0907c9eSPaolo Bonzini .minimum_version_id = 1, 435c0907c9eSPaolo Bonzini .post_load = mch_post_load, 436c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 437ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 438f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 439f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 440f809c605SPaolo Bonzini */ 441f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 442c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 443c0907c9eSPaolo Bonzini } 444c0907c9eSPaolo Bonzini }; 445c0907c9eSPaolo Bonzini 446c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 447c0907c9eSPaolo Bonzini { 448c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 449c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 450c0907c9eSPaolo Bonzini 451c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 452c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 453c0907c9eSPaolo Bonzini 454263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 45577447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 456b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 457b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 458c0907c9eSPaolo Bonzini 459c0907c9eSPaolo Bonzini mch_update(mch); 460c0907c9eSPaolo Bonzini } 461c0907c9eSPaolo Bonzini 4629af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 463c0907c9eSPaolo Bonzini { 464c0907c9eSPaolo Bonzini int i; 465c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 466c0907c9eSPaolo Bonzini 46783d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 46883d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 46983d08f26SMichael S. Tsirkin mch->pci_address_space); 47039848901SIgor Mammedov 471fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 47240c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 473c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 474c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 475c0907c9eSPaolo Bonzini &mch->smram_region, 1); 476fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 477fe6567d5SPaolo Bonzini 47864130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 47964130fa4SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 48064130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 48164130fa4SPaolo Bonzini &mch->open_high_smram, 1); 48264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 48364130fa4SPaolo Bonzini 484fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 485fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 486fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 487fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 488f809c605SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 489fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 490fe6567d5SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 49164130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 49264130fa4SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 49364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 49464130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 495bafc90bdSGerd Hoffmann 496bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 497bafc90bdSGerd Hoffmann &tseg_blackhole_ops, NULL, 498bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 499bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 500bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 501bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 502bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 503bafc90bdSGerd Hoffmann 504bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 505bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 506bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 507bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 508bafc90bdSGerd Hoffmann &mch->tseg_window); 509fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 510fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 511fe6567d5SPaolo Bonzini 512ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 513ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 514ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 515c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 516ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 517ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 518ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 519c0907c9eSPaolo Bonzini } 520c0907c9eSPaolo Bonzini } 521c0907c9eSPaolo Bonzini 5226f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 5236f1426abSMichael S. Tsirkin { 5246f1426abSMichael S. Tsirkin bool ambiguous; 5256f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 5266f1426abSMichael S. Tsirkin if (!o) { 5276f1426abSMichael S. Tsirkin return 0; 5286f1426abSMichael S. Tsirkin } 5296f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 5306f1426abSMichael S. Tsirkin } 5316f1426abSMichael S. Tsirkin 532c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 533c0907c9eSPaolo Bonzini { 534c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 535c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 536c0907c9eSPaolo Bonzini 5379af21dbeSMarkus Armbruster k->realize = mch_realize; 538c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 539c0907c9eSPaolo Bonzini dc->reset = mch_reset; 540125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 541c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 542c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 543c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 544c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 545451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 546c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 54708c58f92SMarkus Armbruster /* 54808c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 54908c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 55008c58f92SMarkus Armbruster */ 551e90f2a8cSEduardo Habkost dc->user_creatable = false; 552c0907c9eSPaolo Bonzini } 553c0907c9eSPaolo Bonzini 554c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 555c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 556c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 557c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 558c0907c9eSPaolo Bonzini .class_init = mch_class_init, 559c0907c9eSPaolo Bonzini }; 560c0907c9eSPaolo Bonzini 561c0907c9eSPaolo Bonzini static void q35_register(void) 562c0907c9eSPaolo Bonzini { 563c0907c9eSPaolo Bonzini type_register_static(&mch_info); 564c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 565c0907c9eSPaolo Bonzini } 566c0907c9eSPaolo Bonzini 567c0907c9eSPaolo Bonzini type_init(q35_register); 568