1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 32c0907c9eSPaolo Bonzini #include "hw/hw.h" 33c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 34da34e65cSMarkus Armbruster #include "qapi/error.h" 3539848901SIgor Mammedov #include "qapi/visitor.h" 360b8fa32fSMarkus Armbruster #include "qemu/module.h" 37c0907c9eSPaolo Bonzini 38c0907c9eSPaolo Bonzini /**************************************************************************** 39c0907c9eSPaolo Bonzini * Q35 host 40c0907c9eSPaolo Bonzini */ 41c0907c9eSPaolo Bonzini 429fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 439fa99d25SMarcel Apfelbaum 4462d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 45c0907c9eSPaolo Bonzini { 46ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 47ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4862d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49c0907c9eSPaolo Bonzini 5062d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5162d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 52c0907c9eSPaolo Bonzini 5362d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5462d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 55c0907c9eSPaolo Bonzini 56a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 57a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 58a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 59a8de0115SPeng Hao 601115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 611115ff6dSDavid Gibson s->mch.pci_address_space, 621115ff6dSDavid Gibson s->mch.address_space_io, 63c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 64621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 65ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 66c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 67c0907c9eSPaolo Bonzini } 68c0907c9eSPaolo Bonzini 69568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 70568f0690SDavid Gibson PCIBus *rootbus) 71568f0690SDavid Gibson { 7204c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 7304c7d8b8SCole Robinson 74568f0690SDavid Gibson /* For backwards compat with old device paths */ 7504c7d8b8SCole Robinson if (s->mch.short_root_bus) { 76568f0690SDavid Gibson return "0000"; 77568f0690SDavid Gibson } 7804c7d8b8SCole Robinson return "0000:00"; 7904c7d8b8SCole Robinson } 80568f0690SDavid Gibson 8139848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 82d7bce999SEric Blake const char *name, void *opaque, 8339848901SIgor Mammedov Error **errp) 8439848901SIgor Mammedov { 8539848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 86a0efbf16SMarkus Armbruster uint64_t val64; 87a0efbf16SMarkus Armbruster uint32_t value; 8839848901SIgor Mammedov 89a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 90a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 91a0efbf16SMarkus Armbruster value = val64; 92a0efbf16SMarkus Armbruster assert(value == val64); 9351e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9439848901SIgor Mammedov } 9539848901SIgor Mammedov 9639848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 97d7bce999SEric Blake const char *name, void *opaque, 9839848901SIgor Mammedov Error **errp) 9939848901SIgor Mammedov { 10039848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 101a0efbf16SMarkus Armbruster uint64_t val64; 102a0efbf16SMarkus Armbruster uint32_t value; 10339848901SIgor Mammedov 104a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 105a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 106a0efbf16SMarkus Armbruster value = val64; 107a0efbf16SMarkus Armbruster assert(value == val64); 10851e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 10939848901SIgor Mammedov } 11039848901SIgor Mammedov 1119fa99d25SMarcel Apfelbaum /* 1129fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1139fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1149fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1159fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1169fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1179fa99d25SMarcel Apfelbaum */ 118ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 11939848901SIgor Mammedov { 1208b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1219fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1228b42d730SMichael S. Tsirkin Range w64; 123a0efbf16SMarkus Armbruster uint64_t value; 12439848901SIgor Mammedov 1258b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 126a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1279fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1289fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1299fa99d25SMarcel Apfelbaum } 130ccef5b1fSLaszlo Ersek return value; 131ccef5b1fSLaszlo Ersek } 132ccef5b1fSLaszlo Ersek 133ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 134ccef5b1fSLaszlo Ersek const char *name, void *opaque, 135ccef5b1fSLaszlo Ersek Error **errp) 136ccef5b1fSLaszlo Ersek { 137ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 138ccef5b1fSLaszlo Ersek 139ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 14039848901SIgor Mammedov } 14139848901SIgor Mammedov 1429fa99d25SMarcel Apfelbaum /* 1439fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1449fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1459fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1469fa99d25SMarcel Apfelbaum * that can be configured by the user. 1479fa99d25SMarcel Apfelbaum */ 14839848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 149d7bce999SEric Blake const char *name, void *opaque, 15039848901SIgor Mammedov Error **errp) 15139848901SIgor Mammedov { 1528b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1539fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 154ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1558b42d730SMichael S. Tsirkin Range w64; 1569fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 15739848901SIgor Mammedov 1588b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 159a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1609fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1619fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1629fa99d25SMarcel Apfelbaum value = hole64_end; 1639fa99d25SMarcel Apfelbaum } 164a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16539848901SIgor Mammedov } 16639848901SIgor Mammedov 167d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 168d7bce999SEric Blake void *opaque, Error **errp) 169cbcaf79eSMichael S. Tsirkin { 170cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 171cbcaf79eSMichael S. Tsirkin 172d015c4eaSMarc-André Lureau visit_type_uint64(v, name, &e->size, errp); 173cbcaf79eSMichael S. Tsirkin } 174cbcaf79eSMichael S. Tsirkin 1759fa99d25SMarcel Apfelbaum /* 1769fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1779fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1789fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1799fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1809fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1819fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1829fa99d25SMarcel Apfelbaum */ 1832f295167SLaszlo Ersek static Property q35_host_props[] = { 18487f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 185c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 18639848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1879fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 18804c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 189401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 190401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 191401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 192401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1939fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 194c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 195c0907c9eSPaolo Bonzini }; 196c0907c9eSPaolo Bonzini 197c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 198c0907c9eSPaolo Bonzini { 199c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 200568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 201c0907c9eSPaolo Bonzini 202568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 20362d92e43SHu Tao dc->realize = q35_host_realize; 2042f295167SLaszlo Ersek dc->props = q35_host_props; 205bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 206e90f2a8cSEduardo Habkost dc->user_creatable = false; 207125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 20868c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 209c0907c9eSPaolo Bonzini } 210c0907c9eSPaolo Bonzini 211c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 212c0907c9eSPaolo Bonzini { 213c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 21462d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 21562d92e43SHu Tao 21662d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 21762d92e43SHu Tao "pci-conf-idx", 4); 21862d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 21962d92e43SHu Tao "pci-conf-data", 4); 220c0907c9eSPaolo Bonzini 221aff39be0SThomas Huth object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 222aff39be0SThomas Huth TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 223446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 224c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2259fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2269fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2279fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2281e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 22939848901SIgor Mammedov q35_host_get_pci_hole_start, 23039848901SIgor Mammedov NULL, NULL, NULL, NULL); 23139848901SIgor Mammedov 2321e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 23339848901SIgor Mammedov q35_host_get_pci_hole_end, 23439848901SIgor Mammedov NULL, NULL, NULL, NULL); 23539848901SIgor Mammedov 2361e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 23739848901SIgor Mammedov q35_host_get_pci_hole64_start, 23839848901SIgor Mammedov NULL, NULL, NULL, NULL); 23939848901SIgor Mammedov 2401e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 24139848901SIgor Mammedov q35_host_get_pci_hole64_end, 24239848901SIgor Mammedov NULL, NULL, NULL, NULL); 24339848901SIgor Mammedov 2441e507bb0SMarc-André Lureau object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 245cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 246cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 247cbcaf79eSMichael S. Tsirkin 248401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 249401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 250401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 251401f2f3eSEfimov Vasily 252401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 253401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 254401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 255401f2f3eSEfimov Vasily 256401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 257401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 258401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 259401f2f3eSEfimov Vasily 260401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 261401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 262401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 263c0907c9eSPaolo Bonzini } 264c0907c9eSPaolo Bonzini 265c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 266c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 267c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 268c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 269c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 270c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 271c0907c9eSPaolo Bonzini }; 272c0907c9eSPaolo Bonzini 273c0907c9eSPaolo Bonzini /**************************************************************************** 274c0907c9eSPaolo Bonzini * MCH D0:F0 275c0907c9eSPaolo Bonzini */ 276c0907c9eSPaolo Bonzini 277bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 278bafc90bdSGerd Hoffmann { 279bafc90bdSGerd Hoffmann return 0xffffffff; 280bafc90bdSGerd Hoffmann } 281bafc90bdSGerd Hoffmann 282bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 283bafc90bdSGerd Hoffmann unsigned width) 284bafc90bdSGerd Hoffmann { 285bafc90bdSGerd Hoffmann /* nothing */ 286bafc90bdSGerd Hoffmann } 287bafc90bdSGerd Hoffmann 288bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = { 289bafc90bdSGerd Hoffmann .read = tseg_blackhole_read, 290bafc90bdSGerd Hoffmann .write = tseg_blackhole_write, 291bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 292bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 293bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 294bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 295bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 296bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 297bafc90bdSGerd Hoffmann }; 298bafc90bdSGerd Hoffmann 299c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 300c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 301c0907c9eSPaolo Bonzini { 302ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 303ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 304ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 305c0907c9eSPaolo Bonzini 306c0907c9eSPaolo Bonzini uint64_t pciexbar; 307c0907c9eSPaolo Bonzini int enable; 308c0907c9eSPaolo Bonzini uint64_t addr; 309c0907c9eSPaolo Bonzini uint64_t addr_mask; 310c0907c9eSPaolo Bonzini uint32_t length; 311c0907c9eSPaolo Bonzini 312c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 313c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 314c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 315c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 316c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 317c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 318c0907c9eSPaolo Bonzini break; 319c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 320c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 321c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 322c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 323c0907c9eSPaolo Bonzini break; 324c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 325c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 326c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 327c0907c9eSPaolo Bonzini break; 328c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 329c0907c9eSPaolo Bonzini default: 330c0907c9eSPaolo Bonzini abort(); 331c0907c9eSPaolo Bonzini } 332c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 333ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 334c0907c9eSPaolo Bonzini } 335c0907c9eSPaolo Bonzini 336c0907c9eSPaolo Bonzini /* PAM */ 337c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 338c0907c9eSPaolo Bonzini { 339ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 340c0907c9eSPaolo Bonzini int i; 341c0907c9eSPaolo Bonzini 342c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 343c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 344c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 34566175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 346c0907c9eSPaolo Bonzini } 347c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 348c0907c9eSPaolo Bonzini } 349c0907c9eSPaolo Bonzini 350c0907c9eSPaolo Bonzini /* SMRAM */ 351c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 352c0907c9eSPaolo Bonzini { 353ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 35464130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 355bafc90bdSGerd Hoffmann uint32_t tseg_size; 356ce88812fSHu Tao 35768c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 35868c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 35968c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 36068c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 36168c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 36268c77acfSGerd Hoffmann } 36368c77acfSGerd Hoffmann 364c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 36564130fa4SPaolo Bonzini 36664130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 36764130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 36864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 36964130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 37064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 37164130fa4SPaolo Bonzini } else { 37264130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 37364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 37464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 37564130fa4SPaolo Bonzini } 37664130fa4SPaolo Bonzini 37764130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 37864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 37964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 38064130fa4SPaolo Bonzini } else { 38164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 38264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 38364130fa4SPaolo Bonzini } 38464130fa4SPaolo Bonzini 385bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 386bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 387bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 388bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 389bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 390bafc90bdSGerd Hoffmann break; 391bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 392bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 393bafc90bdSGerd Hoffmann break; 394bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 395bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 396bafc90bdSGerd Hoffmann break; 397bafc90bdSGerd Hoffmann default: 3982f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 399bafc90bdSGerd Hoffmann break; 400bafc90bdSGerd Hoffmann } 401bafc90bdSGerd Hoffmann } else { 402bafc90bdSGerd Hoffmann tseg_size = 0; 403bafc90bdSGerd Hoffmann } 404bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 405bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 406bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 407bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 408bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 409bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 410bafc90bdSGerd Hoffmann 411bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 412bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 413bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 414bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 415bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 416bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 417bafc90bdSGerd Hoffmann 418c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 419c0907c9eSPaolo Bonzini } 420c0907c9eSPaolo Bonzini 4212f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4222f295167SLaszlo Ersek { 4232f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4242f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4252f295167SLaszlo Ersek 4262f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4272f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4282f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4292f295167SLaszlo Ersek } 4302f295167SLaszlo Ersek } 4312f295167SLaszlo Ersek 432c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 433c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 434c0907c9eSPaolo Bonzini { 435c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 436c0907c9eSPaolo Bonzini 437c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 438c0907c9eSPaolo Bonzini 439c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 440c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 441c0907c9eSPaolo Bonzini mch_update_pam(mch); 442c0907c9eSPaolo Bonzini } 443c0907c9eSPaolo Bonzini 444c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 445c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 446c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 447c0907c9eSPaolo Bonzini } 448c0907c9eSPaolo Bonzini 449263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 450263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 451c0907c9eSPaolo Bonzini mch_update_smram(mch); 452c0907c9eSPaolo Bonzini } 4532f295167SLaszlo Ersek 4542f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4552f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4562f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4572f295167SLaszlo Ersek } 458c0907c9eSPaolo Bonzini } 459c0907c9eSPaolo Bonzini 460c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 461c0907c9eSPaolo Bonzini { 462c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 463c0907c9eSPaolo Bonzini mch_update_pam(mch); 464c0907c9eSPaolo Bonzini mch_update_smram(mch); 4652f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 466*4a441836SGerd Hoffmann 467*4a441836SGerd Hoffmann /* 468*4a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 469*4a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 470*4a441836SGerd Hoffmann */ 471*4a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 472*4a441836SGerd Hoffmann mch->below_4g_mem_size, 473*4a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 474c0907c9eSPaolo Bonzini } 475c0907c9eSPaolo Bonzini 476c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 477c0907c9eSPaolo Bonzini { 478c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 479c0907c9eSPaolo Bonzini mch_update(mch); 480c0907c9eSPaolo Bonzini return 0; 481c0907c9eSPaolo Bonzini } 482c0907c9eSPaolo Bonzini 483c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 484c0907c9eSPaolo Bonzini .name = "mch", 485c0907c9eSPaolo Bonzini .version_id = 1, 486c0907c9eSPaolo Bonzini .minimum_version_id = 1, 487c0907c9eSPaolo Bonzini .post_load = mch_post_load, 488c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 489ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 490f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 491f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 492f809c605SPaolo Bonzini */ 493f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 494c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 495c0907c9eSPaolo Bonzini } 496c0907c9eSPaolo Bonzini }; 497c0907c9eSPaolo Bonzini 498c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 499c0907c9eSPaolo Bonzini { 500c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 501c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 502c0907c9eSPaolo Bonzini 503c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 504c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 505c0907c9eSPaolo Bonzini 506263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 50777447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 508b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 509b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 510c0907c9eSPaolo Bonzini 5112f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5122f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5132f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5142f295167SLaszlo Ersek } 5152f295167SLaszlo Ersek 516c0907c9eSPaolo Bonzini mch_update(mch); 517c0907c9eSPaolo Bonzini } 518c0907c9eSPaolo Bonzini 5199af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 520c0907c9eSPaolo Bonzini { 521c0907c9eSPaolo Bonzini int i; 522c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 523c0907c9eSPaolo Bonzini 5242f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5252f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5262f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5272f295167SLaszlo Ersek return; 5282f295167SLaszlo Ersek } 5292f295167SLaszlo Ersek 53083d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 53183d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 53283d08f26SMichael S. Tsirkin mch->pci_address_space); 53339848901SIgor Mammedov 534fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 53540c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 536dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 537dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 538dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 539c0907c9eSPaolo Bonzini &mch->smram_region, 1); 540fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 541fe6567d5SPaolo Bonzini 54264130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 543dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 544dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 54564130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 54664130fa4SPaolo Bonzini &mch->open_high_smram, 1); 54764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 54864130fa4SPaolo Bonzini 549fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 550fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 551fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 552fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 553dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 554dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 555fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 556dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 557dda53ee9SZihan Yang &mch->low_smram); 55864130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 559dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 560dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 56164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 56264130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 563bafc90bdSGerd Hoffmann 564bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 565bafc90bdSGerd Hoffmann &tseg_blackhole_ops, NULL, 566bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 567bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 568bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 569bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 570bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 571bafc90bdSGerd Hoffmann 572bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 573bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 574bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 575bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 576bafc90bdSGerd Hoffmann &mch->tseg_window); 577fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 578fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 579fe6567d5SPaolo Bonzini 580ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 581ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 582ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 583c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 584ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 585ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 586ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 587c0907c9eSPaolo Bonzini } 588c0907c9eSPaolo Bonzini } 589c0907c9eSPaolo Bonzini 5906f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 5916f1426abSMichael S. Tsirkin { 5926f1426abSMichael S. Tsirkin bool ambiguous; 5936f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 5946f1426abSMichael S. Tsirkin if (!o) { 5956f1426abSMichael S. Tsirkin return 0; 5966f1426abSMichael S. Tsirkin } 5976f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 5986f1426abSMichael S. Tsirkin } 5996f1426abSMichael S. Tsirkin 6002f295167SLaszlo Ersek static Property mch_props[] = { 6012f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6022f295167SLaszlo Ersek 16), 6032f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6042f295167SLaszlo Ersek }; 6052f295167SLaszlo Ersek 606c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 607c0907c9eSPaolo Bonzini { 608c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 609c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 610c0907c9eSPaolo Bonzini 6119af21dbeSMarkus Armbruster k->realize = mch_realize; 612c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 613c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6142f295167SLaszlo Ersek dc->props = mch_props; 615125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 616c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 617c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 618c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 619d4715481SDaniel P. Berrangé /* 620d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 621d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 622d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 623d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 624d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 625d4715481SDaniel P. Berrangé * chipset. 626d4715481SDaniel P. Berrangé */ 627d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 628451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 629c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 63008c58f92SMarkus Armbruster /* 63108c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 63208c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 63308c58f92SMarkus Armbruster */ 634e90f2a8cSEduardo Habkost dc->user_creatable = false; 635c0907c9eSPaolo Bonzini } 636c0907c9eSPaolo Bonzini 637c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 638c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 639c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 640c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 641c0907c9eSPaolo Bonzini .class_init = mch_class_init, 642fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 643fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 644fd3b02c8SEduardo Habkost { }, 645fd3b02c8SEduardo Habkost }, 646c0907c9eSPaolo Bonzini }; 647c0907c9eSPaolo Bonzini 648c0907c9eSPaolo Bonzini static void q35_register(void) 649c0907c9eSPaolo Bonzini { 650c0907c9eSPaolo Bonzini type_register_static(&mch_info); 651c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 652c0907c9eSPaolo Bonzini } 653c0907c9eSPaolo Bonzini 654c0907c9eSPaolo Bonzini type_init(q35_register); 655