1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 32c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 33a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 34d6454270SMarkus Armbruster #include "migration/vmstate.h" 35da34e65cSMarkus Armbruster #include "qapi/error.h" 3639848901SIgor Mammedov #include "qapi/visitor.h" 370b8fa32fSMarkus Armbruster #include "qemu/module.h" 38c0907c9eSPaolo Bonzini 39c0907c9eSPaolo Bonzini /**************************************************************************** 40c0907c9eSPaolo Bonzini * Q35 host 41c0907c9eSPaolo Bonzini */ 42c0907c9eSPaolo Bonzini 439fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 449fa99d25SMarcel Apfelbaum 4562d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 46c0907c9eSPaolo Bonzini { 47ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 48ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4962d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 50c0907c9eSPaolo Bonzini 5162d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5262d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 53c0907c9eSPaolo Bonzini 5462d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5562d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 56c0907c9eSPaolo Bonzini 57a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 58a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 59a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 60a8de0115SPeng Hao 611115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 621115ff6dSDavid Gibson s->mch.pci_address_space, 631115ff6dSDavid Gibson s->mch.address_space_io, 64c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 65621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 66ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 67c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 68c0907c9eSPaolo Bonzini } 69c0907c9eSPaolo Bonzini 70568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 71568f0690SDavid Gibson PCIBus *rootbus) 72568f0690SDavid Gibson { 7304c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 7404c7d8b8SCole Robinson 75568f0690SDavid Gibson /* For backwards compat with old device paths */ 7604c7d8b8SCole Robinson if (s->mch.short_root_bus) { 77568f0690SDavid Gibson return "0000"; 78568f0690SDavid Gibson } 7904c7d8b8SCole Robinson return "0000:00"; 8004c7d8b8SCole Robinson } 81568f0690SDavid Gibson 8239848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 83d7bce999SEric Blake const char *name, void *opaque, 8439848901SIgor Mammedov Error **errp) 8539848901SIgor Mammedov { 8639848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 87a0efbf16SMarkus Armbruster uint64_t val64; 88a0efbf16SMarkus Armbruster uint32_t value; 8939848901SIgor Mammedov 90a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 91a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 92a0efbf16SMarkus Armbruster value = val64; 93a0efbf16SMarkus Armbruster assert(value == val64); 9451e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9539848901SIgor Mammedov } 9639848901SIgor Mammedov 9739848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 98d7bce999SEric Blake const char *name, void *opaque, 9939848901SIgor Mammedov Error **errp) 10039848901SIgor Mammedov { 10139848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 102a0efbf16SMarkus Armbruster uint64_t val64; 103a0efbf16SMarkus Armbruster uint32_t value; 10439848901SIgor Mammedov 105a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 106a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 107a0efbf16SMarkus Armbruster value = val64; 108a0efbf16SMarkus Armbruster assert(value == val64); 10951e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 11039848901SIgor Mammedov } 11139848901SIgor Mammedov 1129fa99d25SMarcel Apfelbaum /* 1139fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1149fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1159fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1169fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1179fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1189fa99d25SMarcel Apfelbaum */ 119ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 12039848901SIgor Mammedov { 1218b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1229fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1238b42d730SMichael S. Tsirkin Range w64; 124a0efbf16SMarkus Armbruster uint64_t value; 12539848901SIgor Mammedov 1268b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 127a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1289fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1299fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1309fa99d25SMarcel Apfelbaum } 131ccef5b1fSLaszlo Ersek return value; 132ccef5b1fSLaszlo Ersek } 133ccef5b1fSLaszlo Ersek 134ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 135ccef5b1fSLaszlo Ersek const char *name, void *opaque, 136ccef5b1fSLaszlo Ersek Error **errp) 137ccef5b1fSLaszlo Ersek { 138ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 139ccef5b1fSLaszlo Ersek 140ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 14139848901SIgor Mammedov } 14239848901SIgor Mammedov 1439fa99d25SMarcel Apfelbaum /* 1449fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1459fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1469fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1479fa99d25SMarcel Apfelbaum * that can be configured by the user. 1489fa99d25SMarcel Apfelbaum */ 14939848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 150d7bce999SEric Blake const char *name, void *opaque, 15139848901SIgor Mammedov Error **errp) 15239848901SIgor Mammedov { 1538b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1549fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 155ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1568b42d730SMichael S. Tsirkin Range w64; 1579fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 15839848901SIgor Mammedov 1598b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 160a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1619fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1629fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1639fa99d25SMarcel Apfelbaum value = hole64_end; 1649fa99d25SMarcel Apfelbaum } 165a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16639848901SIgor Mammedov } 16739848901SIgor Mammedov 168d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 169d7bce999SEric Blake void *opaque, Error **errp) 170cbcaf79eSMichael S. Tsirkin { 171cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 172cbcaf79eSMichael S. Tsirkin 173d015c4eaSMarc-André Lureau visit_type_uint64(v, name, &e->size, errp); 174cbcaf79eSMichael S. Tsirkin } 175cbcaf79eSMichael S. Tsirkin 1769fa99d25SMarcel Apfelbaum /* 1779fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1789fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1799fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1809fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1819fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1829fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1839fa99d25SMarcel Apfelbaum */ 1842f295167SLaszlo Ersek static Property q35_host_props[] = { 18587f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 186c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 18739848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1889fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 18904c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 190401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 191401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 192401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 193401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1949fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 195c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 196c0907c9eSPaolo Bonzini }; 197c0907c9eSPaolo Bonzini 198c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 199c0907c9eSPaolo Bonzini { 200c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 201568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 202c0907c9eSPaolo Bonzini 203568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 20462d92e43SHu Tao dc->realize = q35_host_realize; 205*4f67d30bSMarc-André Lureau device_class_set_props(dc, q35_host_props); 206bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 207e90f2a8cSEduardo Habkost dc->user_creatable = false; 208125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 20968c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 210c0907c9eSPaolo Bonzini } 211c0907c9eSPaolo Bonzini 212c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 213c0907c9eSPaolo Bonzini { 214c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 21562d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 21662d92e43SHu Tao 21762d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 21862d92e43SHu Tao "pci-conf-idx", 4); 21962d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 22062d92e43SHu Tao "pci-conf-data", 4); 221c0907c9eSPaolo Bonzini 222aff39be0SThomas Huth object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 223aff39be0SThomas Huth TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 224446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 225c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2269fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2279fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2289fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2291e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 23039848901SIgor Mammedov q35_host_get_pci_hole_start, 23139848901SIgor Mammedov NULL, NULL, NULL, NULL); 23239848901SIgor Mammedov 2331e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 23439848901SIgor Mammedov q35_host_get_pci_hole_end, 23539848901SIgor Mammedov NULL, NULL, NULL, NULL); 23639848901SIgor Mammedov 2371e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 23839848901SIgor Mammedov q35_host_get_pci_hole64_start, 23939848901SIgor Mammedov NULL, NULL, NULL, NULL); 24039848901SIgor Mammedov 2411e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 24239848901SIgor Mammedov q35_host_get_pci_hole64_end, 24339848901SIgor Mammedov NULL, NULL, NULL, NULL); 24439848901SIgor Mammedov 2451e507bb0SMarc-André Lureau object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 246cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 247cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 248cbcaf79eSMichael S. Tsirkin 249401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 250401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 251401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 252401f2f3eSEfimov Vasily 253401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 254401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 255401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 256401f2f3eSEfimov Vasily 257401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 258401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 259401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 260401f2f3eSEfimov Vasily 261401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 262401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 263401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 264c0907c9eSPaolo Bonzini } 265c0907c9eSPaolo Bonzini 266c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 267c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 268c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 269c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 270c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 271c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 272c0907c9eSPaolo Bonzini }; 273c0907c9eSPaolo Bonzini 274c0907c9eSPaolo Bonzini /**************************************************************************** 275c0907c9eSPaolo Bonzini * MCH D0:F0 276c0907c9eSPaolo Bonzini */ 277c0907c9eSPaolo Bonzini 278bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 279bafc90bdSGerd Hoffmann { 280bafc90bdSGerd Hoffmann return 0xffffffff; 281bafc90bdSGerd Hoffmann } 282bafc90bdSGerd Hoffmann 283bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 284bafc90bdSGerd Hoffmann unsigned width) 285bafc90bdSGerd Hoffmann { 286bafc90bdSGerd Hoffmann /* nothing */ 287bafc90bdSGerd Hoffmann } 288bafc90bdSGerd Hoffmann 289bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = { 290bafc90bdSGerd Hoffmann .read = tseg_blackhole_read, 291bafc90bdSGerd Hoffmann .write = tseg_blackhole_write, 292bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 293bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 294bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 295bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 296bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 297bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 298bafc90bdSGerd Hoffmann }; 299bafc90bdSGerd Hoffmann 300c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 301c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 302c0907c9eSPaolo Bonzini { 303ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 304ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 305ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 306c0907c9eSPaolo Bonzini 307c0907c9eSPaolo Bonzini uint64_t pciexbar; 308c0907c9eSPaolo Bonzini int enable; 309c0907c9eSPaolo Bonzini uint64_t addr; 310c0907c9eSPaolo Bonzini uint64_t addr_mask; 311c0907c9eSPaolo Bonzini uint32_t length; 312c0907c9eSPaolo Bonzini 313c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 314c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 315c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 316c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 317c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 318c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 319c0907c9eSPaolo Bonzini break; 320c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 321c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 322c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 323c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 324c0907c9eSPaolo Bonzini break; 325c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 326c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 327c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 328c0907c9eSPaolo Bonzini break; 329c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 330c0907c9eSPaolo Bonzini default: 331c0907c9eSPaolo Bonzini abort(); 332c0907c9eSPaolo Bonzini } 333c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 334ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 335c0907c9eSPaolo Bonzini } 336c0907c9eSPaolo Bonzini 337c0907c9eSPaolo Bonzini /* PAM */ 338c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 339c0907c9eSPaolo Bonzini { 340ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 341c0907c9eSPaolo Bonzini int i; 342c0907c9eSPaolo Bonzini 343c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 344c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 345c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 34666175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 347c0907c9eSPaolo Bonzini } 348c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 349c0907c9eSPaolo Bonzini } 350c0907c9eSPaolo Bonzini 351c0907c9eSPaolo Bonzini /* SMRAM */ 352c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 353c0907c9eSPaolo Bonzini { 354ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 35564130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 356bafc90bdSGerd Hoffmann uint32_t tseg_size; 357ce88812fSHu Tao 35868c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 35968c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 36068c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 36168c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 36268c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 36368c77acfSGerd Hoffmann } 36468c77acfSGerd Hoffmann 365c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 36664130fa4SPaolo Bonzini 36764130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 36864130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 36964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 37064130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 37164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 37264130fa4SPaolo Bonzini } else { 37364130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 37464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 37564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 37664130fa4SPaolo Bonzini } 37764130fa4SPaolo Bonzini 37864130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 37964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 38064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 38164130fa4SPaolo Bonzini } else { 38264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 38364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 38464130fa4SPaolo Bonzini } 38564130fa4SPaolo Bonzini 386bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 387bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 388bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 389bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 390bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 391bafc90bdSGerd Hoffmann break; 392bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 393bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 394bafc90bdSGerd Hoffmann break; 395bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 396bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 397bafc90bdSGerd Hoffmann break; 398bafc90bdSGerd Hoffmann default: 3992f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 400bafc90bdSGerd Hoffmann break; 401bafc90bdSGerd Hoffmann } 402bafc90bdSGerd Hoffmann } else { 403bafc90bdSGerd Hoffmann tseg_size = 0; 404bafc90bdSGerd Hoffmann } 405bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 406bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 407bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 408bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 409bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 410bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 411bafc90bdSGerd Hoffmann 412bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 413bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 414bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 415bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 416bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 417bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 418bafc90bdSGerd Hoffmann 419c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 420c0907c9eSPaolo Bonzini } 421c0907c9eSPaolo Bonzini 4222f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4232f295167SLaszlo Ersek { 4242f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4252f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4262f295167SLaszlo Ersek 4272f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4282f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4292f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4302f295167SLaszlo Ersek } 4312f295167SLaszlo Ersek } 4322f295167SLaszlo Ersek 433c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 434c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 435c0907c9eSPaolo Bonzini { 436c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 437c0907c9eSPaolo Bonzini 438c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 439c0907c9eSPaolo Bonzini 440c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 441c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 442c0907c9eSPaolo Bonzini mch_update_pam(mch); 443c0907c9eSPaolo Bonzini } 444c0907c9eSPaolo Bonzini 445c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 446c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 447c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 448c0907c9eSPaolo Bonzini } 449c0907c9eSPaolo Bonzini 450263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 451263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 452c0907c9eSPaolo Bonzini mch_update_smram(mch); 453c0907c9eSPaolo Bonzini } 4542f295167SLaszlo Ersek 4552f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4562f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4572f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4582f295167SLaszlo Ersek } 459c0907c9eSPaolo Bonzini } 460c0907c9eSPaolo Bonzini 461c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 462c0907c9eSPaolo Bonzini { 463c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 464c0907c9eSPaolo Bonzini mch_update_pam(mch); 465c0907c9eSPaolo Bonzini mch_update_smram(mch); 4662f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4674a441836SGerd Hoffmann 4684a441836SGerd Hoffmann /* 4694a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 4704a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 4714a441836SGerd Hoffmann */ 4724a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 4734a441836SGerd Hoffmann mch->below_4g_mem_size, 4744a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 475c0907c9eSPaolo Bonzini } 476c0907c9eSPaolo Bonzini 477c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 478c0907c9eSPaolo Bonzini { 479c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 480c0907c9eSPaolo Bonzini mch_update(mch); 481c0907c9eSPaolo Bonzini return 0; 482c0907c9eSPaolo Bonzini } 483c0907c9eSPaolo Bonzini 484c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 485c0907c9eSPaolo Bonzini .name = "mch", 486c0907c9eSPaolo Bonzini .version_id = 1, 487c0907c9eSPaolo Bonzini .minimum_version_id = 1, 488c0907c9eSPaolo Bonzini .post_load = mch_post_load, 489c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 490ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 491f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 492f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 493f809c605SPaolo Bonzini */ 494f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 495c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 496c0907c9eSPaolo Bonzini } 497c0907c9eSPaolo Bonzini }; 498c0907c9eSPaolo Bonzini 499c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 500c0907c9eSPaolo Bonzini { 501c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 502c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 503c0907c9eSPaolo Bonzini 504c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 505c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 506c0907c9eSPaolo Bonzini 507263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 50877447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 509b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 510b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 511c0907c9eSPaolo Bonzini 5122f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5132f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5142f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5152f295167SLaszlo Ersek } 5162f295167SLaszlo Ersek 517c0907c9eSPaolo Bonzini mch_update(mch); 518c0907c9eSPaolo Bonzini } 519c0907c9eSPaolo Bonzini 5209af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 521c0907c9eSPaolo Bonzini { 522c0907c9eSPaolo Bonzini int i; 523c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 524c0907c9eSPaolo Bonzini 5252f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5262f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5272f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5282f295167SLaszlo Ersek return; 5292f295167SLaszlo Ersek } 5302f295167SLaszlo Ersek 53183d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 53283d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 53383d08f26SMichael S. Tsirkin mch->pci_address_space); 53439848901SIgor Mammedov 535fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 53640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 537dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 538dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 539dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 540c0907c9eSPaolo Bonzini &mch->smram_region, 1); 541fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 542fe6567d5SPaolo Bonzini 54364130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 544dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 545dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 54664130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 54764130fa4SPaolo Bonzini &mch->open_high_smram, 1); 54864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 54964130fa4SPaolo Bonzini 550fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 551fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 552fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 553fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 554dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 555dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 556fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 557dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 558dda53ee9SZihan Yang &mch->low_smram); 55964130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 560dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 561dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 56264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 56364130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 564bafc90bdSGerd Hoffmann 565bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 566bafc90bdSGerd Hoffmann &tseg_blackhole_ops, NULL, 567bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 568bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 569bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 570bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 571bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 572bafc90bdSGerd Hoffmann 573bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 574bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 575bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 576bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 577bafc90bdSGerd Hoffmann &mch->tseg_window); 578fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 579fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 580fe6567d5SPaolo Bonzini 581ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 582ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 583ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 584c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 585ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 586ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 587ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 588c0907c9eSPaolo Bonzini } 589c0907c9eSPaolo Bonzini } 590c0907c9eSPaolo Bonzini 5916f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 5926f1426abSMichael S. Tsirkin { 5936f1426abSMichael S. Tsirkin bool ambiguous; 5946f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 5956f1426abSMichael S. Tsirkin if (!o) { 5966f1426abSMichael S. Tsirkin return 0; 5976f1426abSMichael S. Tsirkin } 5986f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 5996f1426abSMichael S. Tsirkin } 6006f1426abSMichael S. Tsirkin 6012f295167SLaszlo Ersek static Property mch_props[] = { 6022f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6032f295167SLaszlo Ersek 16), 6042f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6052f295167SLaszlo Ersek }; 6062f295167SLaszlo Ersek 607c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 608c0907c9eSPaolo Bonzini { 609c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 610c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 611c0907c9eSPaolo Bonzini 6129af21dbeSMarkus Armbruster k->realize = mch_realize; 613c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 614c0907c9eSPaolo Bonzini dc->reset = mch_reset; 615*4f67d30bSMarc-André Lureau device_class_set_props(dc, mch_props); 616125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 617c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 618c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 619c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 620d4715481SDaniel P. Berrangé /* 621d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 622d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 623d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 624d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 625d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 626d4715481SDaniel P. Berrangé * chipset. 627d4715481SDaniel P. Berrangé */ 628d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 629451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 630c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 63108c58f92SMarkus Armbruster /* 63208c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 63308c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 63408c58f92SMarkus Armbruster */ 635e90f2a8cSEduardo Habkost dc->user_creatable = false; 636c0907c9eSPaolo Bonzini } 637c0907c9eSPaolo Bonzini 638c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 639c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 640c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 641c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 642c0907c9eSPaolo Bonzini .class_init = mch_class_init, 643fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 644fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 645fd3b02c8SEduardo Habkost { }, 646fd3b02c8SEduardo Habkost }, 647c0907c9eSPaolo Bonzini }; 648c0907c9eSPaolo Bonzini 649c0907c9eSPaolo Bonzini static void q35_register(void) 650c0907c9eSPaolo Bonzini { 651c0907c9eSPaolo Bonzini type_register_static(&mch_info); 652c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 653c0907c9eSPaolo Bonzini } 654c0907c9eSPaolo Bonzini 655c0907c9eSPaolo Bonzini type_init(q35_register); 656