1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 32*71adf91aSPhilippe Mathieu-Daudé #include "hw/i386/pc.h" 33c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 34a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 35d6454270SMarkus Armbruster #include "migration/vmstate.h" 36da34e65cSMarkus Armbruster #include "qapi/error.h" 3739848901SIgor Mammedov #include "qapi/visitor.h" 380b8fa32fSMarkus Armbruster #include "qemu/module.h" 39c0907c9eSPaolo Bonzini 40c0907c9eSPaolo Bonzini /**************************************************************************** 41c0907c9eSPaolo Bonzini * Q35 host 42c0907c9eSPaolo Bonzini */ 43c0907c9eSPaolo Bonzini 449fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 459fa99d25SMarcel Apfelbaum 4662d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 47c0907c9eSPaolo Bonzini { 48ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 49ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 5062d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 51c0907c9eSPaolo Bonzini 5262d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5362d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 54c0907c9eSPaolo Bonzini 5562d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5662d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 57c0907c9eSPaolo Bonzini 58a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 59a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 60a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 61a8de0115SPeng Hao 621115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 631115ff6dSDavid Gibson s->mch.pci_address_space, 641115ff6dSDavid Gibson s->mch.address_space_io, 65c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 66621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 67ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 68c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 69c0907c9eSPaolo Bonzini } 70c0907c9eSPaolo Bonzini 71568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 72568f0690SDavid Gibson PCIBus *rootbus) 73568f0690SDavid Gibson { 7404c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 7504c7d8b8SCole Robinson 76568f0690SDavid Gibson /* For backwards compat with old device paths */ 7704c7d8b8SCole Robinson if (s->mch.short_root_bus) { 78568f0690SDavid Gibson return "0000"; 79568f0690SDavid Gibson } 8004c7d8b8SCole Robinson return "0000:00"; 8104c7d8b8SCole Robinson } 82568f0690SDavid Gibson 8339848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 84d7bce999SEric Blake const char *name, void *opaque, 8539848901SIgor Mammedov Error **errp) 8639848901SIgor Mammedov { 8739848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 88a0efbf16SMarkus Armbruster uint64_t val64; 89a0efbf16SMarkus Armbruster uint32_t value; 9039848901SIgor Mammedov 91a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 92a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 93a0efbf16SMarkus Armbruster value = val64; 94a0efbf16SMarkus Armbruster assert(value == val64); 9551e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9639848901SIgor Mammedov } 9739848901SIgor Mammedov 9839848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 99d7bce999SEric Blake const char *name, void *opaque, 10039848901SIgor Mammedov Error **errp) 10139848901SIgor Mammedov { 10239848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 103a0efbf16SMarkus Armbruster uint64_t val64; 104a0efbf16SMarkus Armbruster uint32_t value; 10539848901SIgor Mammedov 106a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 107a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 108a0efbf16SMarkus Armbruster value = val64; 109a0efbf16SMarkus Armbruster assert(value == val64); 11051e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 11139848901SIgor Mammedov } 11239848901SIgor Mammedov 1139fa99d25SMarcel Apfelbaum /* 1149fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1159fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1169fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1179fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1189fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1199fa99d25SMarcel Apfelbaum */ 120ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 12139848901SIgor Mammedov { 1228b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1239fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1248b42d730SMichael S. Tsirkin Range w64; 125a0efbf16SMarkus Armbruster uint64_t value; 12639848901SIgor Mammedov 1278b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 128a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1299fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1309fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1319fa99d25SMarcel Apfelbaum } 132ccef5b1fSLaszlo Ersek return value; 133ccef5b1fSLaszlo Ersek } 134ccef5b1fSLaszlo Ersek 135ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 136ccef5b1fSLaszlo Ersek const char *name, void *opaque, 137ccef5b1fSLaszlo Ersek Error **errp) 138ccef5b1fSLaszlo Ersek { 139ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 140ccef5b1fSLaszlo Ersek 141ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 14239848901SIgor Mammedov } 14339848901SIgor Mammedov 1449fa99d25SMarcel Apfelbaum /* 1459fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1469fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1479fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1489fa99d25SMarcel Apfelbaum * that can be configured by the user. 1499fa99d25SMarcel Apfelbaum */ 15039848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 151d7bce999SEric Blake const char *name, void *opaque, 15239848901SIgor Mammedov Error **errp) 15339848901SIgor Mammedov { 1548b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1559fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 156ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1578b42d730SMichael S. Tsirkin Range w64; 1589fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 15939848901SIgor Mammedov 1608b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 161a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1629fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1639fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1649fa99d25SMarcel Apfelbaum value = hole64_end; 1659fa99d25SMarcel Apfelbaum } 166a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16739848901SIgor Mammedov } 16839848901SIgor Mammedov 169d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 170d7bce999SEric Blake void *opaque, Error **errp) 171cbcaf79eSMichael S. Tsirkin { 172cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 173cbcaf79eSMichael S. Tsirkin 174d015c4eaSMarc-André Lureau visit_type_uint64(v, name, &e->size, errp); 175cbcaf79eSMichael S. Tsirkin } 176cbcaf79eSMichael S. Tsirkin 1779fa99d25SMarcel Apfelbaum /* 1789fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1799fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1809fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1819fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1829fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1839fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1849fa99d25SMarcel Apfelbaum */ 1852f295167SLaszlo Ersek static Property q35_host_props[] = { 18687f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 187c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 18839848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1899fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 19004c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 191401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 192401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 193401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 194401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1959fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 196c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 197c0907c9eSPaolo Bonzini }; 198c0907c9eSPaolo Bonzini 199c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 200c0907c9eSPaolo Bonzini { 201c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 202568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 203c0907c9eSPaolo Bonzini 204568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 20562d92e43SHu Tao dc->realize = q35_host_realize; 2064f67d30bSMarc-André Lureau device_class_set_props(dc, q35_host_props); 207bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 208e90f2a8cSEduardo Habkost dc->user_creatable = false; 209125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 21068c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 211c0907c9eSPaolo Bonzini } 212c0907c9eSPaolo Bonzini 213c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 214c0907c9eSPaolo Bonzini { 215c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 21662d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 21762d92e43SHu Tao 21862d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 21962d92e43SHu Tao "pci-conf-idx", 4); 22062d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 22162d92e43SHu Tao "pci-conf-data", 4); 222c0907c9eSPaolo Bonzini 223aff39be0SThomas Huth object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 224aff39be0SThomas Huth TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 225446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 226c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2279fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2289fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2299fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2301e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 23139848901SIgor Mammedov q35_host_get_pci_hole_start, 23239848901SIgor Mammedov NULL, NULL, NULL, NULL); 23339848901SIgor Mammedov 2341e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 23539848901SIgor Mammedov q35_host_get_pci_hole_end, 23639848901SIgor Mammedov NULL, NULL, NULL, NULL); 23739848901SIgor Mammedov 2381e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 23939848901SIgor Mammedov q35_host_get_pci_hole64_start, 24039848901SIgor Mammedov NULL, NULL, NULL, NULL); 24139848901SIgor Mammedov 2421e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 24339848901SIgor Mammedov q35_host_get_pci_hole64_end, 24439848901SIgor Mammedov NULL, NULL, NULL, NULL); 24539848901SIgor Mammedov 2461e507bb0SMarc-André Lureau object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 247cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 248cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 249cbcaf79eSMichael S. Tsirkin 250401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 251401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 252401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 253401f2f3eSEfimov Vasily 254401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 255401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 256401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 257401f2f3eSEfimov Vasily 258401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 259401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 260401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 261401f2f3eSEfimov Vasily 262401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 263401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 264401f2f3eSEfimov Vasily qdev_prop_allow_set_link_before_realize, 0, NULL); 265c0907c9eSPaolo Bonzini } 266c0907c9eSPaolo Bonzini 267c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 268c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 269c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 270c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 271c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 272c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 273c0907c9eSPaolo Bonzini }; 274c0907c9eSPaolo Bonzini 275c0907c9eSPaolo Bonzini /**************************************************************************** 276c0907c9eSPaolo Bonzini * MCH D0:F0 277c0907c9eSPaolo Bonzini */ 278c0907c9eSPaolo Bonzini 279f404220eSIgor Mammedov static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 280bafc90bdSGerd Hoffmann { 281bafc90bdSGerd Hoffmann return 0xffffffff; 282bafc90bdSGerd Hoffmann } 283bafc90bdSGerd Hoffmann 284f404220eSIgor Mammedov static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 285bafc90bdSGerd Hoffmann unsigned width) 286bafc90bdSGerd Hoffmann { 287bafc90bdSGerd Hoffmann /* nothing */ 288bafc90bdSGerd Hoffmann } 289bafc90bdSGerd Hoffmann 290f404220eSIgor Mammedov static const MemoryRegionOps blackhole_ops = { 291f404220eSIgor Mammedov .read = blackhole_read, 292f404220eSIgor Mammedov .write = blackhole_write, 293bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 294bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 295bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 296bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 297bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 298bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 299bafc90bdSGerd Hoffmann }; 300bafc90bdSGerd Hoffmann 301c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 302c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 303c0907c9eSPaolo Bonzini { 304ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 305ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 306ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 307c0907c9eSPaolo Bonzini 308c0907c9eSPaolo Bonzini uint64_t pciexbar; 309c0907c9eSPaolo Bonzini int enable; 310c0907c9eSPaolo Bonzini uint64_t addr; 311c0907c9eSPaolo Bonzini uint64_t addr_mask; 312c0907c9eSPaolo Bonzini uint32_t length; 313c0907c9eSPaolo Bonzini 314c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 315c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 316c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 317c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 318c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 319c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 320c0907c9eSPaolo Bonzini break; 321c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 322c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 323c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 324c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 325c0907c9eSPaolo Bonzini break; 326c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 327c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 328c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 329c0907c9eSPaolo Bonzini break; 330c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 331c0907c9eSPaolo Bonzini default: 332c0907c9eSPaolo Bonzini abort(); 333c0907c9eSPaolo Bonzini } 334c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 335ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 336c0907c9eSPaolo Bonzini } 337c0907c9eSPaolo Bonzini 338c0907c9eSPaolo Bonzini /* PAM */ 339c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 340c0907c9eSPaolo Bonzini { 341ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 342c0907c9eSPaolo Bonzini int i; 343c0907c9eSPaolo Bonzini 344c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 345c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 346c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 34766175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 348c0907c9eSPaolo Bonzini } 349c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 350c0907c9eSPaolo Bonzini } 351c0907c9eSPaolo Bonzini 352c0907c9eSPaolo Bonzini /* SMRAM */ 353c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 354c0907c9eSPaolo Bonzini { 355ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 35664130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 357bafc90bdSGerd Hoffmann uint32_t tseg_size; 358ce88812fSHu Tao 35968c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 36068c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 36168c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 36268c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 36368c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 36468c77acfSGerd Hoffmann } 36568c77acfSGerd Hoffmann 366c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 36764130fa4SPaolo Bonzini 36864130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 36964130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 37064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 37164130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 37264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 37364130fa4SPaolo Bonzini } else { 37464130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 37564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 37664130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 37764130fa4SPaolo Bonzini } 37864130fa4SPaolo Bonzini 37964130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 38064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 38164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 38264130fa4SPaolo Bonzini } else { 38364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 38464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 38564130fa4SPaolo Bonzini } 38664130fa4SPaolo Bonzini 387bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 388bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 389bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 390bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 391bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 392bafc90bdSGerd Hoffmann break; 393bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 394bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 395bafc90bdSGerd Hoffmann break; 396bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 397bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 398bafc90bdSGerd Hoffmann break; 399bafc90bdSGerd Hoffmann default: 4002f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 401bafc90bdSGerd Hoffmann break; 402bafc90bdSGerd Hoffmann } 403bafc90bdSGerd Hoffmann } else { 404bafc90bdSGerd Hoffmann tseg_size = 0; 405bafc90bdSGerd Hoffmann } 406bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 407bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 408bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 409bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 410bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 411bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 412bafc90bdSGerd Hoffmann 413bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 414bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 415bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 416bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 417bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 418bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 419bafc90bdSGerd Hoffmann 420c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 421c0907c9eSPaolo Bonzini } 422c0907c9eSPaolo Bonzini 4232f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4242f295167SLaszlo Ersek { 4252f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4262f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4272f295167SLaszlo Ersek 4282f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4292f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4302f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4312f295167SLaszlo Ersek } 4322f295167SLaszlo Ersek } 4332f295167SLaszlo Ersek 434f404220eSIgor Mammedov static void mch_update_smbase_smram(MCHPCIState *mch) 435f404220eSIgor Mammedov { 436f404220eSIgor Mammedov PCIDevice *pd = PCI_DEVICE(mch); 437f404220eSIgor Mammedov uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 438f404220eSIgor Mammedov bool lck; 439f404220eSIgor Mammedov 440f404220eSIgor Mammedov if (!mch->has_smram_at_smbase) { 441f404220eSIgor Mammedov return; 442f404220eSIgor Mammedov } 443f404220eSIgor Mammedov 444f404220eSIgor Mammedov if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 445f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 446f404220eSIgor Mammedov MCH_HOST_BRIDGE_F_SMBASE_LCK; 447f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 448f404220eSIgor Mammedov return; 449f404220eSIgor Mammedov } 450f404220eSIgor Mammedov 451f404220eSIgor Mammedov /* 452f404220eSIgor Mammedov * default/reset state, discard written value 453f404220eSIgor Mammedov * which will disable SMRAM balackhole at SMBASE 454f404220eSIgor Mammedov */ 455f404220eSIgor Mammedov if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 456f404220eSIgor Mammedov *reg = 0x00; 457f404220eSIgor Mammedov } 458f404220eSIgor Mammedov 459f404220eSIgor Mammedov memory_region_transaction_begin(); 460f404220eSIgor Mammedov if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 461f404220eSIgor Mammedov /* disable all writes */ 462f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 463f404220eSIgor Mammedov ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 464f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 465f404220eSIgor Mammedov lck = true; 466f404220eSIgor Mammedov } else { 467f404220eSIgor Mammedov lck = false; 468f404220eSIgor Mammedov } 469f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, lck); 470f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, lck); 471f404220eSIgor Mammedov memory_region_transaction_commit(); 472f404220eSIgor Mammedov } 473f404220eSIgor Mammedov 474c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 475c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 476c0907c9eSPaolo Bonzini { 477c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 478c0907c9eSPaolo Bonzini 479c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 480c0907c9eSPaolo Bonzini 481c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 482c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 483c0907c9eSPaolo Bonzini mch_update_pam(mch); 484c0907c9eSPaolo Bonzini } 485c0907c9eSPaolo Bonzini 486c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 487c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 488c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 489c0907c9eSPaolo Bonzini } 490c0907c9eSPaolo Bonzini 491263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 492263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 493c0907c9eSPaolo Bonzini mch_update_smram(mch); 494c0907c9eSPaolo Bonzini } 4952f295167SLaszlo Ersek 4962f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4972f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4982f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4992f295167SLaszlo Ersek } 500f404220eSIgor Mammedov 501f404220eSIgor Mammedov if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 502f404220eSIgor Mammedov mch_update_smbase_smram(mch); 503f404220eSIgor Mammedov } 504c0907c9eSPaolo Bonzini } 505c0907c9eSPaolo Bonzini 506c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 507c0907c9eSPaolo Bonzini { 508c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 509c0907c9eSPaolo Bonzini mch_update_pam(mch); 510c0907c9eSPaolo Bonzini mch_update_smram(mch); 5112f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 512f404220eSIgor Mammedov mch_update_smbase_smram(mch); 5134a441836SGerd Hoffmann 5144a441836SGerd Hoffmann /* 5154a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 5164a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 5174a441836SGerd Hoffmann */ 5184a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 5194a441836SGerd Hoffmann mch->below_4g_mem_size, 5204a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 521c0907c9eSPaolo Bonzini } 522c0907c9eSPaolo Bonzini 523c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 524c0907c9eSPaolo Bonzini { 525c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 526c0907c9eSPaolo Bonzini mch_update(mch); 527c0907c9eSPaolo Bonzini return 0; 528c0907c9eSPaolo Bonzini } 529c0907c9eSPaolo Bonzini 530c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 531c0907c9eSPaolo Bonzini .name = "mch", 532c0907c9eSPaolo Bonzini .version_id = 1, 533c0907c9eSPaolo Bonzini .minimum_version_id = 1, 534c0907c9eSPaolo Bonzini .post_load = mch_post_load, 535c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 536ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 537f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 538f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 539f809c605SPaolo Bonzini */ 540f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 541c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 542c0907c9eSPaolo Bonzini } 543c0907c9eSPaolo Bonzini }; 544c0907c9eSPaolo Bonzini 545c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 546c0907c9eSPaolo Bonzini { 547c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 548c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 549c0907c9eSPaolo Bonzini 550c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 551c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 552c0907c9eSPaolo Bonzini 553263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 55477447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 555b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 556b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 557c0907c9eSPaolo Bonzini 5582f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5592f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5602f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5612f295167SLaszlo Ersek } 5622f295167SLaszlo Ersek 563f404220eSIgor Mammedov d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 564f404220eSIgor Mammedov d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 565f404220eSIgor Mammedov 566c0907c9eSPaolo Bonzini mch_update(mch); 567c0907c9eSPaolo Bonzini } 568c0907c9eSPaolo Bonzini 5699af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 570c0907c9eSPaolo Bonzini { 571c0907c9eSPaolo Bonzini int i; 572c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 573c0907c9eSPaolo Bonzini 5742f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5752f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5762f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5772f295167SLaszlo Ersek return; 5782f295167SLaszlo Ersek } 5792f295167SLaszlo Ersek 58083d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 58183d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 58283d08f26SMichael S. Tsirkin mch->pci_address_space); 58339848901SIgor Mammedov 584fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 58540c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 586dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 587dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 588dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 589c0907c9eSPaolo Bonzini &mch->smram_region, 1); 590fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 591fe6567d5SPaolo Bonzini 59264130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 593dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 594dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 59564130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 59664130fa4SPaolo Bonzini &mch->open_high_smram, 1); 59764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 59864130fa4SPaolo Bonzini 599fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 600fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 601fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 602fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 603dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 604dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 605fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 606dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 607dda53ee9SZihan Yang &mch->low_smram); 60864130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 609dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 610dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 61164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 61264130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 613bafc90bdSGerd Hoffmann 614bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 615f404220eSIgor Mammedov &blackhole_ops, NULL, 616bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 617bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 618bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 619bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 620bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 621bafc90bdSGerd Hoffmann 622bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 623bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 624bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 625bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 626bafc90bdSGerd Hoffmann &mch->tseg_window); 627f404220eSIgor Mammedov 628f404220eSIgor Mammedov /* 629f404220eSIgor Mammedov * This is not what hardware does, so it's QEMU specific hack. 630f404220eSIgor Mammedov * See commit message for details. 631f404220eSIgor Mammedov */ 632f404220eSIgor Mammedov memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 633f404220eSIgor Mammedov NULL, "smbase-blackhole", 634f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 635f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, false); 636f404220eSIgor Mammedov memory_region_add_subregion_overlap(mch->system_memory, 637f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 638f404220eSIgor Mammedov &mch->smbase_blackhole, 1); 639f404220eSIgor Mammedov 640f404220eSIgor Mammedov memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 641f404220eSIgor Mammedov "smbase-window", mch->ram_memory, 642f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 643f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 644f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, false); 645f404220eSIgor Mammedov memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 646f404220eSIgor Mammedov &mch->smbase_window); 647f404220eSIgor Mammedov 648fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 649fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 650fe6567d5SPaolo Bonzini 651ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 652ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 653ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 654c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 655ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 656ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 657ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 658c0907c9eSPaolo Bonzini } 659c0907c9eSPaolo Bonzini } 660c0907c9eSPaolo Bonzini 6616f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 6626f1426abSMichael S. Tsirkin { 6636f1426abSMichael S. Tsirkin bool ambiguous; 6646f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 6656f1426abSMichael S. Tsirkin if (!o) { 6666f1426abSMichael S. Tsirkin return 0; 6676f1426abSMichael S. Tsirkin } 6686f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 6696f1426abSMichael S. Tsirkin } 6706f1426abSMichael S. Tsirkin 6712f295167SLaszlo Ersek static Property mch_props[] = { 6722f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6732f295167SLaszlo Ersek 16), 674f404220eSIgor Mammedov DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 6752f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6762f295167SLaszlo Ersek }; 6772f295167SLaszlo Ersek 678c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 679c0907c9eSPaolo Bonzini { 680c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 681c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 682c0907c9eSPaolo Bonzini 6839af21dbeSMarkus Armbruster k->realize = mch_realize; 684c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 685c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6864f67d30bSMarc-André Lureau device_class_set_props(dc, mch_props); 687125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 688c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 689c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 690c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 691d4715481SDaniel P. Berrangé /* 692d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 693d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 694d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 695d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 696d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 697d4715481SDaniel P. Berrangé * chipset. 698d4715481SDaniel P. Berrangé */ 699d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 700451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 701c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 70208c58f92SMarkus Armbruster /* 70308c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 70408c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 70508c58f92SMarkus Armbruster */ 706e90f2a8cSEduardo Habkost dc->user_creatable = false; 707c0907c9eSPaolo Bonzini } 708c0907c9eSPaolo Bonzini 709c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 710c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 711c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 712c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 713c0907c9eSPaolo Bonzini .class_init = mch_class_init, 714fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 715fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 716fd3b02c8SEduardo Habkost { }, 717fd3b02c8SEduardo Habkost }, 718c0907c9eSPaolo Bonzini }; 719c0907c9eSPaolo Bonzini 720c0907c9eSPaolo Bonzini static void q35_register(void) 721c0907c9eSPaolo Bonzini { 722c0907c9eSPaolo Bonzini type_register_static(&mch_info); 723c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 724c0907c9eSPaolo Bonzini } 725c0907c9eSPaolo Bonzini 726c0907c9eSPaolo Bonzini type_init(q35_register); 727