xref: /qemu/hw/pci-host/q35.c (revision a8de0115)
1c0907c9eSPaolo Bonzini /*
2c0907c9eSPaolo Bonzini  * QEMU MCH/ICH9 PCI Bridge Emulation
3c0907c9eSPaolo Bonzini  *
4c0907c9eSPaolo Bonzini  * Copyright (c) 2006 Fabrice Bellard
5c0907c9eSPaolo Bonzini  * Copyright (c) 2009, 2010, 2011
6c0907c9eSPaolo Bonzini  *               Isaku Yamahata <yamahata at valinux co jp>
7c0907c9eSPaolo Bonzini  *               VA Linux Systems Japan K.K.
8c0907c9eSPaolo Bonzini  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9c0907c9eSPaolo Bonzini  *
10ef9f7b58SGonglei  * This is based on piix.c, but heavily modified.
11c0907c9eSPaolo Bonzini  *
12c0907c9eSPaolo Bonzini  * Permission is hereby granted, free of charge, to any person obtaining a copy
13c0907c9eSPaolo Bonzini  * of this software and associated documentation files (the "Software"), to deal
14c0907c9eSPaolo Bonzini  * in the Software without restriction, including without limitation the rights
15c0907c9eSPaolo Bonzini  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16c0907c9eSPaolo Bonzini  * copies of the Software, and to permit persons to whom the Software is
17c0907c9eSPaolo Bonzini  * furnished to do so, subject to the following conditions:
18c0907c9eSPaolo Bonzini  *
19c0907c9eSPaolo Bonzini  * The above copyright notice and this permission notice shall be included in
20c0907c9eSPaolo Bonzini  * all copies or substantial portions of the Software.
21c0907c9eSPaolo Bonzini  *
22c0907c9eSPaolo Bonzini  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23c0907c9eSPaolo Bonzini  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24c0907c9eSPaolo Bonzini  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25c0907c9eSPaolo Bonzini  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26c0907c9eSPaolo Bonzini  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27c0907c9eSPaolo Bonzini  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28c0907c9eSPaolo Bonzini  * THE SOFTWARE.
29c0907c9eSPaolo Bonzini  */
30b6a0aa05SPeter Maydell #include "qemu/osdep.h"
31c0907c9eSPaolo Bonzini #include "hw/hw.h"
32c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h"
33da34e65cSMarkus Armbruster #include "qapi/error.h"
3439848901SIgor Mammedov #include "qapi/visitor.h"
35c0907c9eSPaolo Bonzini 
36c0907c9eSPaolo Bonzini /****************************************************************************
37c0907c9eSPaolo Bonzini  * Q35 host
38c0907c9eSPaolo Bonzini  */
39c0907c9eSPaolo Bonzini 
409fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35)
419fa99d25SMarcel Apfelbaum 
4262d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp)
43c0907c9eSPaolo Bonzini {
44ce88812fSHu Tao     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
45ce88812fSHu Tao     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
4662d92e43SHu Tao     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
47c0907c9eSPaolo Bonzini 
4862d92e43SHu Tao     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
4962d92e43SHu Tao     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
50c0907c9eSPaolo Bonzini 
5162d92e43SHu Tao     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
5262d92e43SHu Tao     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
53c0907c9eSPaolo Bonzini 
54*a8de0115SPeng Hao     /* register q35 0xcf8 port as coalesced pio */
55*a8de0115SPeng Hao     memory_region_set_flush_coalesced(&pci->data_mem);
56*a8de0115SPeng Hao     memory_region_add_coalescing(&pci->conf_mem, 0, 4);
57*a8de0115SPeng Hao 
581115ff6dSDavid Gibson     pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0",
591115ff6dSDavid Gibson                                 s->mch.pci_address_space,
601115ff6dSDavid Gibson                                 s->mch.address_space_io,
61c0907c9eSPaolo Bonzini                                 0, TYPE_PCIE_BUS);
62621d983aSMarcel Apfelbaum     PC_MACHINE(qdev_get_machine())->bus = pci->bus;
63ce88812fSHu Tao     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
64c0907c9eSPaolo Bonzini     qdev_init_nofail(DEVICE(&s->mch));
65c0907c9eSPaolo Bonzini }
66c0907c9eSPaolo Bonzini 
67568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
68568f0690SDavid Gibson                                           PCIBus *rootbus)
69568f0690SDavid Gibson {
7004c7d8b8SCole Robinson     Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
7104c7d8b8SCole Robinson 
72568f0690SDavid Gibson      /* For backwards compat with old device paths */
7304c7d8b8SCole Robinson     if (s->mch.short_root_bus) {
74568f0690SDavid Gibson         return "0000";
75568f0690SDavid Gibson     }
7604c7d8b8SCole Robinson     return "0000:00";
7704c7d8b8SCole Robinson }
78568f0690SDavid Gibson 
7939848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
80d7bce999SEric Blake                                         const char *name, void *opaque,
8139848901SIgor Mammedov                                         Error **errp)
8239848901SIgor Mammedov {
8339848901SIgor Mammedov     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
84a0efbf16SMarkus Armbruster     uint64_t val64;
85a0efbf16SMarkus Armbruster     uint32_t value;
8639848901SIgor Mammedov 
87a0efbf16SMarkus Armbruster     val64 = range_is_empty(&s->mch.pci_hole)
88a0efbf16SMarkus Armbruster         ? 0 : range_lob(&s->mch.pci_hole);
89a0efbf16SMarkus Armbruster     value = val64;
90a0efbf16SMarkus Armbruster     assert(value == val64);
9151e72bc1SEric Blake     visit_type_uint32(v, name, &value, errp);
9239848901SIgor Mammedov }
9339848901SIgor Mammedov 
9439848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
95d7bce999SEric Blake                                       const char *name, void *opaque,
9639848901SIgor Mammedov                                       Error **errp)
9739848901SIgor Mammedov {
9839848901SIgor Mammedov     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
99a0efbf16SMarkus Armbruster     uint64_t val64;
100a0efbf16SMarkus Armbruster     uint32_t value;
10139848901SIgor Mammedov 
102a0efbf16SMarkus Armbruster     val64 = range_is_empty(&s->mch.pci_hole)
103a0efbf16SMarkus Armbruster         ? 0 : range_upb(&s->mch.pci_hole) + 1;
104a0efbf16SMarkus Armbruster     value = val64;
105a0efbf16SMarkus Armbruster     assert(value == val64);
10651e72bc1SEric Blake     visit_type_uint32(v, name, &value, errp);
10739848901SIgor Mammedov }
10839848901SIgor Mammedov 
1099fa99d25SMarcel Apfelbaum /*
1109fa99d25SMarcel Apfelbaum  * The 64bit PCI hole start is set by the Guest firmware
1119fa99d25SMarcel Apfelbaum  * as the address of the first 64bit PCI MEM resource.
1129fa99d25SMarcel Apfelbaum  * If no PCI device has resources on the 64bit area,
1139fa99d25SMarcel Apfelbaum  * the 64bit PCI hole will start after "over 4G RAM" and the
1149fa99d25SMarcel Apfelbaum  * reserved space for memory hotplug if any.
1159fa99d25SMarcel Apfelbaum  */
11639848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
117d7bce999SEric Blake                                           const char *name, void *opaque,
11839848901SIgor Mammedov                                           Error **errp)
11939848901SIgor Mammedov {
1208b42d730SMichael S. Tsirkin     PCIHostState *h = PCI_HOST_BRIDGE(obj);
1219fa99d25SMarcel Apfelbaum     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
1228b42d730SMichael S. Tsirkin     Range w64;
123a0efbf16SMarkus Armbruster     uint64_t value;
12439848901SIgor Mammedov 
1258b42d730SMichael S. Tsirkin     pci_bus_get_w64_range(h->bus, &w64);
126a0efbf16SMarkus Armbruster     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
1279fa99d25SMarcel Apfelbaum     if (!value && s->pci_hole64_fix) {
1289fa99d25SMarcel Apfelbaum         value = pc_pci_hole64_start();
1299fa99d25SMarcel Apfelbaum     }
130a0efbf16SMarkus Armbruster     visit_type_uint64(v, name, &value, errp);
13139848901SIgor Mammedov }
13239848901SIgor Mammedov 
1339fa99d25SMarcel Apfelbaum /*
1349fa99d25SMarcel Apfelbaum  * The 64bit PCI hole end is set by the Guest firmware
1359fa99d25SMarcel Apfelbaum  * as the address of the last 64bit PCI MEM resource.
1369fa99d25SMarcel Apfelbaum  * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
1379fa99d25SMarcel Apfelbaum  * that can be configured by the user.
1389fa99d25SMarcel Apfelbaum  */
13939848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
140d7bce999SEric Blake                                         const char *name, void *opaque,
14139848901SIgor Mammedov                                         Error **errp)
14239848901SIgor Mammedov {
1438b42d730SMichael S. Tsirkin     PCIHostState *h = PCI_HOST_BRIDGE(obj);
1449fa99d25SMarcel Apfelbaum     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
1459fa99d25SMarcel Apfelbaum     uint64_t hole64_start = pc_pci_hole64_start();
1468b42d730SMichael S. Tsirkin     Range w64;
1479fa99d25SMarcel Apfelbaum     uint64_t value, hole64_end;
14839848901SIgor Mammedov 
1498b42d730SMichael S. Tsirkin     pci_bus_get_w64_range(h->bus, &w64);
150a0efbf16SMarkus Armbruster     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
1519fa99d25SMarcel Apfelbaum     hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
1529fa99d25SMarcel Apfelbaum     if (s->pci_hole64_fix && value < hole64_end) {
1539fa99d25SMarcel Apfelbaum         value = hole64_end;
1549fa99d25SMarcel Apfelbaum     }
155a0efbf16SMarkus Armbruster     visit_type_uint64(v, name, &value, errp);
15639848901SIgor Mammedov }
15739848901SIgor Mammedov 
158d7bce999SEric Blake static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
159d7bce999SEric Blake                                     void *opaque, Error **errp)
160cbcaf79eSMichael S. Tsirkin {
161cbcaf79eSMichael S. Tsirkin     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
162cbcaf79eSMichael S. Tsirkin 
163d015c4eaSMarc-André Lureau     visit_type_uint64(v, name, &e->size, errp);
164cbcaf79eSMichael S. Tsirkin }
165cbcaf79eSMichael S. Tsirkin 
1669fa99d25SMarcel Apfelbaum /*
1679fa99d25SMarcel Apfelbaum  * NOTE: setting defaults for the mch.* fields in this table
1689fa99d25SMarcel Apfelbaum  * doesn't work, because mch is a separate QOM object that is
1699fa99d25SMarcel Apfelbaum  * zeroed by the object_initialize(&s->mch, ...) call inside
1709fa99d25SMarcel Apfelbaum  * q35_host_initfn().  The default values for those
1719fa99d25SMarcel Apfelbaum  * properties need to be initialized manually by
1729fa99d25SMarcel Apfelbaum  * q35_host_initfn() after the object_initialize() call.
1739fa99d25SMarcel Apfelbaum  */
1742f295167SLaszlo Ersek static Property q35_host_props[] = {
17587f65245SMichael S. Tsirkin     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
176c0907c9eSPaolo Bonzini                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
17739848901SIgor Mammedov     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
1789fa99d25SMarcel Apfelbaum                      mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT),
17904c7d8b8SCole Robinson     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
180401f2f3eSEfimov Vasily     DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
181401f2f3eSEfimov Vasily                      mch.below_4g_mem_size, 0),
182401f2f3eSEfimov Vasily     DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
183401f2f3eSEfimov Vasily                      mch.above_4g_mem_size, 0),
1849fa99d25SMarcel Apfelbaum     DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true),
185c0907c9eSPaolo Bonzini     DEFINE_PROP_END_OF_LIST(),
186c0907c9eSPaolo Bonzini };
187c0907c9eSPaolo Bonzini 
188c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data)
189c0907c9eSPaolo Bonzini {
190c0907c9eSPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
191568f0690SDavid Gibson     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
192c0907c9eSPaolo Bonzini 
193568f0690SDavid Gibson     hc->root_bus_path = q35_host_root_bus_path;
19462d92e43SHu Tao     dc->realize = q35_host_realize;
1952f295167SLaszlo Ersek     dc->props = q35_host_props;
196bf8d4924SMarcel Apfelbaum     /* Reason: needs to be wired up by pc_q35_init */
197e90f2a8cSEduardo Habkost     dc->user_creatable = false;
198125ee0edSMarcel Apfelbaum     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
19968c0e134SMichael S. Tsirkin     dc->fw_name = "pci";
200c0907c9eSPaolo Bonzini }
201c0907c9eSPaolo Bonzini 
202c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj)
203c0907c9eSPaolo Bonzini {
204c0907c9eSPaolo Bonzini     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
20562d92e43SHu Tao     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
20662d92e43SHu Tao 
20762d92e43SHu Tao     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
20862d92e43SHu Tao                           "pci-conf-idx", 4);
20962d92e43SHu Tao     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
21062d92e43SHu Tao                           "pci-conf-data", 4);
211c0907c9eSPaolo Bonzini 
212213f0c4fSAndreas Färber     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
213c0907c9eSPaolo Bonzini     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
214446de8b6SMarc-André Lureau     qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
215c0907c9eSPaolo Bonzini     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
2169fa99d25SMarcel Apfelbaum     /* mch's object_initialize resets the default value, set it again */
2179fa99d25SMarcel Apfelbaum     qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE,
2189fa99d25SMarcel Apfelbaum                          Q35_PCI_HOST_HOLE64_SIZE_DEFAULT);
2191e507bb0SMarc-André Lureau     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
22039848901SIgor Mammedov                         q35_host_get_pci_hole_start,
22139848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
22239848901SIgor Mammedov 
2231e507bb0SMarc-André Lureau     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
22439848901SIgor Mammedov                         q35_host_get_pci_hole_end,
22539848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
22639848901SIgor Mammedov 
2271e507bb0SMarc-André Lureau     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
22839848901SIgor Mammedov                         q35_host_get_pci_hole64_start,
22939848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
23039848901SIgor Mammedov 
2311e507bb0SMarc-André Lureau     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
23239848901SIgor Mammedov                         q35_host_get_pci_hole64_end,
23339848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
23439848901SIgor Mammedov 
2351e507bb0SMarc-André Lureau     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64",
236cbcaf79eSMichael S. Tsirkin                         q35_host_get_mmcfg_size,
237cbcaf79eSMichael S. Tsirkin                         NULL, NULL, NULL, NULL);
238cbcaf79eSMichael S. Tsirkin 
239401f2f3eSEfimov Vasily     object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
240401f2f3eSEfimov Vasily                              (Object **) &s->mch.ram_memory,
241401f2f3eSEfimov Vasily                              qdev_prop_allow_set_link_before_realize, 0, NULL);
242401f2f3eSEfimov Vasily 
243401f2f3eSEfimov Vasily     object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
244401f2f3eSEfimov Vasily                              (Object **) &s->mch.pci_address_space,
245401f2f3eSEfimov Vasily                              qdev_prop_allow_set_link_before_realize, 0, NULL);
246401f2f3eSEfimov Vasily 
247401f2f3eSEfimov Vasily     object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
248401f2f3eSEfimov Vasily                              (Object **) &s->mch.system_memory,
249401f2f3eSEfimov Vasily                              qdev_prop_allow_set_link_before_realize, 0, NULL);
250401f2f3eSEfimov Vasily 
251401f2f3eSEfimov Vasily     object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
252401f2f3eSEfimov Vasily                              (Object **) &s->mch.address_space_io,
253401f2f3eSEfimov Vasily                              qdev_prop_allow_set_link_before_realize, 0, NULL);
254401f2f3eSEfimov Vasily 
25539848901SIgor Mammedov     /* Leave enough space for the biggest MCFG BAR */
25639848901SIgor Mammedov     /* TODO: this matches current bios behaviour, but
25739848901SIgor Mammedov      * it's not a power of two, which means an MTRR
25839848901SIgor Mammedov      * can't cover it exactly.
25939848901SIgor Mammedov      */
260a0efbf16SMarkus Armbruster     range_set_bounds(&s->mch.pci_hole,
261a0efbf16SMarkus Armbruster             MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX,
262a0efbf16SMarkus Armbruster             IO_APIC_DEFAULT_ADDRESS - 1);
263c0907c9eSPaolo Bonzini }
264c0907c9eSPaolo Bonzini 
265c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = {
266c0907c9eSPaolo Bonzini     .name       = TYPE_Q35_HOST_DEVICE,
267c0907c9eSPaolo Bonzini     .parent     = TYPE_PCIE_HOST_BRIDGE,
268c0907c9eSPaolo Bonzini     .instance_size = sizeof(Q35PCIHost),
269c0907c9eSPaolo Bonzini     .instance_init = q35_host_initfn,
270c0907c9eSPaolo Bonzini     .class_init = q35_host_class_init,
271c0907c9eSPaolo Bonzini };
272c0907c9eSPaolo Bonzini 
273c0907c9eSPaolo Bonzini /****************************************************************************
274c0907c9eSPaolo Bonzini  * MCH D0:F0
275c0907c9eSPaolo Bonzini  */
276c0907c9eSPaolo Bonzini 
277bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
278bafc90bdSGerd Hoffmann {
279bafc90bdSGerd Hoffmann     return 0xffffffff;
280bafc90bdSGerd Hoffmann }
281bafc90bdSGerd Hoffmann 
282bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
283bafc90bdSGerd Hoffmann                                  unsigned width)
284bafc90bdSGerd Hoffmann {
285bafc90bdSGerd Hoffmann     /* nothing */
286bafc90bdSGerd Hoffmann }
287bafc90bdSGerd Hoffmann 
288bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = {
289bafc90bdSGerd Hoffmann     .read = tseg_blackhole_read,
290bafc90bdSGerd Hoffmann     .write = tseg_blackhole_write,
291bafc90bdSGerd Hoffmann     .endianness = DEVICE_NATIVE_ENDIAN,
292bafc90bdSGerd Hoffmann     .valid.min_access_size = 1,
293bafc90bdSGerd Hoffmann     .valid.max_access_size = 4,
294bafc90bdSGerd Hoffmann     .impl.min_access_size = 4,
295bafc90bdSGerd Hoffmann     .impl.max_access_size = 4,
296bafc90bdSGerd Hoffmann     .endianness = DEVICE_LITTLE_ENDIAN,
297bafc90bdSGerd Hoffmann };
298bafc90bdSGerd Hoffmann 
299c0907c9eSPaolo Bonzini /* PCIe MMCFG */
300c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch)
301c0907c9eSPaolo Bonzini {
302ce88812fSHu Tao     PCIDevice *pci_dev = PCI_DEVICE(mch);
303ce88812fSHu Tao     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
304ce88812fSHu Tao     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
305c0907c9eSPaolo Bonzini 
306c0907c9eSPaolo Bonzini     uint64_t pciexbar;
307c0907c9eSPaolo Bonzini     int enable;
308c0907c9eSPaolo Bonzini     uint64_t addr;
309c0907c9eSPaolo Bonzini     uint64_t addr_mask;
310c0907c9eSPaolo Bonzini     uint32_t length;
311c0907c9eSPaolo Bonzini 
312c0907c9eSPaolo Bonzini     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
313c0907c9eSPaolo Bonzini     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
314c0907c9eSPaolo Bonzini     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
315c0907c9eSPaolo Bonzini     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
316c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
317c0907c9eSPaolo Bonzini         length = 256 * 1024 * 1024;
318c0907c9eSPaolo Bonzini         break;
319c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
320c0907c9eSPaolo Bonzini         length = 128 * 1024 * 1024;
321c0907c9eSPaolo Bonzini         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
322c0907c9eSPaolo Bonzini             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
323c0907c9eSPaolo Bonzini         break;
324c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
325c0907c9eSPaolo Bonzini         length = 64 * 1024 * 1024;
326c0907c9eSPaolo Bonzini         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
327c0907c9eSPaolo Bonzini         break;
328c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
329c0907c9eSPaolo Bonzini     default:
330c0907c9eSPaolo Bonzini         abort();
331c0907c9eSPaolo Bonzini     }
332c0907c9eSPaolo Bonzini     addr = pciexbar & addr_mask;
333ce88812fSHu Tao     pcie_host_mmcfg_update(pehb, enable, addr, length);
334636228a8SMichael S. Tsirkin     /* Leave enough space for the MCFG BAR */
335636228a8SMichael S. Tsirkin     /*
336636228a8SMichael S. Tsirkin      * TODO: this matches current bios behaviour, but it's not a power of two,
337636228a8SMichael S. Tsirkin      * which means an MTRR can't cover it exactly.
338636228a8SMichael S. Tsirkin      */
339636228a8SMichael S. Tsirkin     if (enable) {
340a0efbf16SMarkus Armbruster         range_set_bounds(&mch->pci_hole,
341a0efbf16SMarkus Armbruster                          addr + length,
342a0efbf16SMarkus Armbruster                          IO_APIC_DEFAULT_ADDRESS - 1);
343636228a8SMichael S. Tsirkin     } else {
344a0efbf16SMarkus Armbruster         range_set_bounds(&mch->pci_hole,
345a0efbf16SMarkus Armbruster                          MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT,
346a0efbf16SMarkus Armbruster                          IO_APIC_DEFAULT_ADDRESS - 1);
347636228a8SMichael S. Tsirkin     }
348c0907c9eSPaolo Bonzini }
349c0907c9eSPaolo Bonzini 
350c0907c9eSPaolo Bonzini /* PAM */
351c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch)
352c0907c9eSPaolo Bonzini {
353ce88812fSHu Tao     PCIDevice *pd = PCI_DEVICE(mch);
354c0907c9eSPaolo Bonzini     int i;
355c0907c9eSPaolo Bonzini 
356c0907c9eSPaolo Bonzini     memory_region_transaction_begin();
357c0907c9eSPaolo Bonzini     for (i = 0; i < 13; i++) {
358c0907c9eSPaolo Bonzini         pam_update(&mch->pam_regions[i], i,
359fa141081SMarc-André Lureau                    pd->config[MCH_HOST_BRIDGE_PAM0 + (DIV_ROUND_UP(i, 2))]);
360c0907c9eSPaolo Bonzini     }
361c0907c9eSPaolo Bonzini     memory_region_transaction_commit();
362c0907c9eSPaolo Bonzini }
363c0907c9eSPaolo Bonzini 
364c0907c9eSPaolo Bonzini /* SMRAM */
365c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch)
366c0907c9eSPaolo Bonzini {
367ce88812fSHu Tao     PCIDevice *pd = PCI_DEVICE(mch);
36864130fa4SPaolo Bonzini     bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
369bafc90bdSGerd Hoffmann     uint32_t tseg_size;
370ce88812fSHu Tao 
37168c77acfSGerd Hoffmann     /* implement SMRAM.D_LCK */
37268c77acfSGerd Hoffmann     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
37368c77acfSGerd Hoffmann         pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
37468c77acfSGerd Hoffmann         pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
37568c77acfSGerd Hoffmann         pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
37668c77acfSGerd Hoffmann     }
37768c77acfSGerd Hoffmann 
378c0907c9eSPaolo Bonzini     memory_region_transaction_begin();
37964130fa4SPaolo Bonzini 
38064130fa4SPaolo Bonzini     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
38164130fa4SPaolo Bonzini         /* Hide (!) low SMRAM if H_SMRAME = 1 */
38264130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->smram_region, h_smrame);
38364130fa4SPaolo Bonzini         /* Show high SMRAM if H_SMRAME = 1 */
38464130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->open_high_smram, h_smrame);
38564130fa4SPaolo Bonzini     } else {
38664130fa4SPaolo Bonzini         /* Hide high SMRAM and low SMRAM */
38764130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->smram_region, true);
38864130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->open_high_smram, false);
38964130fa4SPaolo Bonzini     }
39064130fa4SPaolo Bonzini 
39164130fa4SPaolo Bonzini     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
39264130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->low_smram, !h_smrame);
39364130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->high_smram, h_smrame);
39464130fa4SPaolo Bonzini     } else {
39564130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->low_smram, false);
39664130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->high_smram, false);
39764130fa4SPaolo Bonzini     }
39864130fa4SPaolo Bonzini 
399bafc90bdSGerd Hoffmann     if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
400bafc90bdSGerd Hoffmann         switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
401bafc90bdSGerd Hoffmann                 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
402bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
403bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024;
404bafc90bdSGerd Hoffmann             break;
405bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
406bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024 * 2;
407bafc90bdSGerd Hoffmann             break;
408bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
409bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024 * 8;
410bafc90bdSGerd Hoffmann             break;
411bafc90bdSGerd Hoffmann         default:
4122f295167SLaszlo Ersek             tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
413bafc90bdSGerd Hoffmann             break;
414bafc90bdSGerd Hoffmann         }
415bafc90bdSGerd Hoffmann     } else {
416bafc90bdSGerd Hoffmann         tseg_size = 0;
417bafc90bdSGerd Hoffmann     }
418bafc90bdSGerd Hoffmann     memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
419bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
420bafc90bdSGerd Hoffmann     memory_region_set_size(&mch->tseg_blackhole, tseg_size);
421bafc90bdSGerd Hoffmann     memory_region_add_subregion_overlap(mch->system_memory,
422bafc90bdSGerd Hoffmann                                         mch->below_4g_mem_size - tseg_size,
423bafc90bdSGerd Hoffmann                                         &mch->tseg_blackhole, 1);
424bafc90bdSGerd Hoffmann 
425bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_window, tseg_size);
426bafc90bdSGerd Hoffmann     memory_region_set_size(&mch->tseg_window, tseg_size);
427bafc90bdSGerd Hoffmann     memory_region_set_address(&mch->tseg_window,
428bafc90bdSGerd Hoffmann                               mch->below_4g_mem_size - tseg_size);
429bafc90bdSGerd Hoffmann     memory_region_set_alias_offset(&mch->tseg_window,
430bafc90bdSGerd Hoffmann                                    mch->below_4g_mem_size - tseg_size);
431bafc90bdSGerd Hoffmann 
432c0907c9eSPaolo Bonzini     memory_region_transaction_commit();
433c0907c9eSPaolo Bonzini }
434c0907c9eSPaolo Bonzini 
4352f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch)
4362f295167SLaszlo Ersek {
4372f295167SLaszlo Ersek     PCIDevice *pd = PCI_DEVICE(mch);
4382f295167SLaszlo Ersek     uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES;
4392f295167SLaszlo Ersek 
4402f295167SLaszlo Ersek     if (mch->ext_tseg_mbytes > 0 &&
4412f295167SLaszlo Ersek         pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) {
4422f295167SLaszlo Ersek         pci_set_word(reg, mch->ext_tseg_mbytes);
4432f295167SLaszlo Ersek     }
4442f295167SLaszlo Ersek }
4452f295167SLaszlo Ersek 
446c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d,
447c0907c9eSPaolo Bonzini                               uint32_t address, uint32_t val, int len)
448c0907c9eSPaolo Bonzini {
449c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
450c0907c9eSPaolo Bonzini 
451c0907c9eSPaolo Bonzini     pci_default_write_config(d, address, val, len);
452c0907c9eSPaolo Bonzini 
453c0907c9eSPaolo Bonzini     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
454c0907c9eSPaolo Bonzini                        MCH_HOST_BRIDGE_PAM_SIZE)) {
455c0907c9eSPaolo Bonzini         mch_update_pam(mch);
456c0907c9eSPaolo Bonzini     }
457c0907c9eSPaolo Bonzini 
458c0907c9eSPaolo Bonzini     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
459c0907c9eSPaolo Bonzini                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
460c0907c9eSPaolo Bonzini         mch_update_pciexbar(mch);
461c0907c9eSPaolo Bonzini     }
462c0907c9eSPaolo Bonzini 
463263cf436SBALATON Zoltan     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
464263cf436SBALATON Zoltan                        MCH_HOST_BRIDGE_SMRAM_SIZE)) {
465c0907c9eSPaolo Bonzini         mch_update_smram(mch);
466c0907c9eSPaolo Bonzini     }
4672f295167SLaszlo Ersek 
4682f295167SLaszlo Ersek     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
4692f295167SLaszlo Ersek                        MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {
4702f295167SLaszlo Ersek         mch_update_ext_tseg_mbytes(mch);
4712f295167SLaszlo Ersek     }
472c0907c9eSPaolo Bonzini }
473c0907c9eSPaolo Bonzini 
474c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch)
475c0907c9eSPaolo Bonzini {
476c0907c9eSPaolo Bonzini     mch_update_pciexbar(mch);
477c0907c9eSPaolo Bonzini     mch_update_pam(mch);
478c0907c9eSPaolo Bonzini     mch_update_smram(mch);
4792f295167SLaszlo Ersek     mch_update_ext_tseg_mbytes(mch);
480c0907c9eSPaolo Bonzini }
481c0907c9eSPaolo Bonzini 
482c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id)
483c0907c9eSPaolo Bonzini {
484c0907c9eSPaolo Bonzini     MCHPCIState *mch = opaque;
485c0907c9eSPaolo Bonzini     mch_update(mch);
486c0907c9eSPaolo Bonzini     return 0;
487c0907c9eSPaolo Bonzini }
488c0907c9eSPaolo Bonzini 
489c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = {
490c0907c9eSPaolo Bonzini     .name = "mch",
491c0907c9eSPaolo Bonzini     .version_id = 1,
492c0907c9eSPaolo Bonzini     .minimum_version_id = 1,
493c0907c9eSPaolo Bonzini     .post_load = mch_post_load,
494c0907c9eSPaolo Bonzini     .fields = (VMStateField[]) {
495ce88812fSHu Tao         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
496f809c605SPaolo Bonzini         /* Used to be smm_enabled, which was basically always zero because
497f809c605SPaolo Bonzini          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
498f809c605SPaolo Bonzini          */
499f809c605SPaolo Bonzini         VMSTATE_UNUSED(1),
500c0907c9eSPaolo Bonzini         VMSTATE_END_OF_LIST()
501c0907c9eSPaolo Bonzini     }
502c0907c9eSPaolo Bonzini };
503c0907c9eSPaolo Bonzini 
504c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev)
505c0907c9eSPaolo Bonzini {
506c0907c9eSPaolo Bonzini     PCIDevice *d = PCI_DEVICE(qdev);
507c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
508c0907c9eSPaolo Bonzini 
509c0907c9eSPaolo Bonzini     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
510c0907c9eSPaolo Bonzini                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
511c0907c9eSPaolo Bonzini 
512263cf436SBALATON Zoltan     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
51377447524SGerd Hoffmann     d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
514b66a67d7SGerd Hoffmann     d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
515b66a67d7SGerd Hoffmann     d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
516c0907c9eSPaolo Bonzini 
5172f295167SLaszlo Ersek     if (mch->ext_tseg_mbytes > 0) {
5182f295167SLaszlo Ersek         pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
5192f295167SLaszlo Ersek                      MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
5202f295167SLaszlo Ersek     }
5212f295167SLaszlo Ersek 
522c0907c9eSPaolo Bonzini     mch_update(mch);
523c0907c9eSPaolo Bonzini }
524c0907c9eSPaolo Bonzini 
5259af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp)
526c0907c9eSPaolo Bonzini {
527c0907c9eSPaolo Bonzini     int i;
528c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
529c0907c9eSPaolo Bonzini 
5302f295167SLaszlo Ersek     if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {
5312f295167SLaszlo Ersek         error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,
5322f295167SLaszlo Ersek                    mch->ext_tseg_mbytes);
5332f295167SLaszlo Ersek         return;
5342f295167SLaszlo Ersek     }
5352f295167SLaszlo Ersek 
53683d08f26SMichael S. Tsirkin     /* setup pci memory mapping */
53783d08f26SMichael S. Tsirkin     pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
53883d08f26SMichael S. Tsirkin                            mch->pci_address_space);
53939848901SIgor Mammedov 
540fe6567d5SPaolo Bonzini     /* if *disabled* show SMRAM to all CPUs */
54140c5dce9SPaolo Bonzini     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
542dda53ee9SZihan Yang                              mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE,
543dda53ee9SZihan Yang                              MCH_HOST_BRIDGE_SMRAM_C_SIZE);
544dda53ee9SZihan Yang     memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
545c0907c9eSPaolo Bonzini                                         &mch->smram_region, 1);
546fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->smram_region, true);
547fe6567d5SPaolo Bonzini 
54864130fa4SPaolo Bonzini     memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
549dda53ee9SZihan Yang                              mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
550dda53ee9SZihan Yang                              MCH_HOST_BRIDGE_SMRAM_C_SIZE);
55164130fa4SPaolo Bonzini     memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
55264130fa4SPaolo Bonzini                                         &mch->open_high_smram, 1);
55364130fa4SPaolo Bonzini     memory_region_set_enabled(&mch->open_high_smram, false);
55464130fa4SPaolo Bonzini 
555fe6567d5SPaolo Bonzini     /* smram, as seen by SMM CPUs */
556fe6567d5SPaolo Bonzini     memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
557fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->smram, true);
558fe6567d5SPaolo Bonzini     memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
559dda53ee9SZihan Yang                              mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
560dda53ee9SZihan Yang                              MCH_HOST_BRIDGE_SMRAM_C_SIZE);
561fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->low_smram, true);
562dda53ee9SZihan Yang     memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE,
563dda53ee9SZihan Yang                                 &mch->low_smram);
56464130fa4SPaolo Bonzini     memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
565dda53ee9SZihan Yang                              mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
566dda53ee9SZihan Yang                              MCH_HOST_BRIDGE_SMRAM_C_SIZE);
56764130fa4SPaolo Bonzini     memory_region_set_enabled(&mch->high_smram, true);
56864130fa4SPaolo Bonzini     memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
569bafc90bdSGerd Hoffmann 
570bafc90bdSGerd Hoffmann     memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
571bafc90bdSGerd Hoffmann                           &tseg_blackhole_ops, NULL,
572bafc90bdSGerd Hoffmann                           "tseg-blackhole", 0);
573bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_blackhole, false);
574bafc90bdSGerd Hoffmann     memory_region_add_subregion_overlap(mch->system_memory,
575bafc90bdSGerd Hoffmann                                         mch->below_4g_mem_size,
576bafc90bdSGerd Hoffmann                                         &mch->tseg_blackhole, 1);
577bafc90bdSGerd Hoffmann 
578bafc90bdSGerd Hoffmann     memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
579bafc90bdSGerd Hoffmann                              mch->ram_memory, mch->below_4g_mem_size, 0);
580bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_window, false);
581bafc90bdSGerd Hoffmann     memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
582bafc90bdSGerd Hoffmann                                 &mch->tseg_window);
583fe6567d5SPaolo Bonzini     object_property_add_const_link(qdev_get_machine(), "smram",
584fe6567d5SPaolo Bonzini                                    OBJECT(&mch->smram), &error_abort);
585fe6567d5SPaolo Bonzini 
586ac40aa15SLe Tan     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
587ac40aa15SLe Tan              mch->pci_address_space, &mch->pam_regions[0],
588ac40aa15SLe Tan              PAM_BIOS_BASE, PAM_BIOS_SIZE);
589c0907c9eSPaolo Bonzini     for (i = 0; i < 12; ++i) {
590ac40aa15SLe Tan         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
591ac40aa15SLe Tan                  mch->pci_address_space, &mch->pam_regions[i+1],
592ac40aa15SLe Tan                  PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
593c0907c9eSPaolo Bonzini     }
594c0907c9eSPaolo Bonzini }
595c0907c9eSPaolo Bonzini 
5966f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void)
5976f1426abSMichael S. Tsirkin {
5986f1426abSMichael S. Tsirkin     bool ambiguous;
5996f1426abSMichael S. Tsirkin     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
6006f1426abSMichael S. Tsirkin     if (!o) {
6016f1426abSMichael S. Tsirkin         return 0;
6026f1426abSMichael S. Tsirkin     }
6036f1426abSMichael S. Tsirkin     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
6046f1426abSMichael S. Tsirkin }
6056f1426abSMichael S. Tsirkin 
6062f295167SLaszlo Ersek static Property mch_props[] = {
6072f295167SLaszlo Ersek     DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
6082f295167SLaszlo Ersek                        16),
6092f295167SLaszlo Ersek     DEFINE_PROP_END_OF_LIST(),
6102f295167SLaszlo Ersek };
6112f295167SLaszlo Ersek 
612c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data)
613c0907c9eSPaolo Bonzini {
614c0907c9eSPaolo Bonzini     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
615c0907c9eSPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
616c0907c9eSPaolo Bonzini 
6179af21dbeSMarkus Armbruster     k->realize = mch_realize;
618c0907c9eSPaolo Bonzini     k->config_write = mch_write_config;
619c0907c9eSPaolo Bonzini     dc->reset = mch_reset;
6202f295167SLaszlo Ersek     dc->props = mch_props;
621125ee0edSMarcel Apfelbaum     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
622c0907c9eSPaolo Bonzini     dc->desc = "Host bridge";
623c0907c9eSPaolo Bonzini     dc->vmsd = &vmstate_mch;
624c0907c9eSPaolo Bonzini     k->vendor_id = PCI_VENDOR_ID_INTEL;
625c0907c9eSPaolo Bonzini     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
626451f7846SRichard W.M. Jones     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
627c0907c9eSPaolo Bonzini     k->class_id = PCI_CLASS_BRIDGE_HOST;
62808c58f92SMarkus Armbruster     /*
62908c58f92SMarkus Armbruster      * PCI-facing part of the host bridge, not usable without the
63008c58f92SMarkus Armbruster      * host-facing part, which can't be device_add'ed, yet.
63108c58f92SMarkus Armbruster      */
632e90f2a8cSEduardo Habkost     dc->user_creatable = false;
633c0907c9eSPaolo Bonzini }
634c0907c9eSPaolo Bonzini 
635c0907c9eSPaolo Bonzini static const TypeInfo mch_info = {
636c0907c9eSPaolo Bonzini     .name = TYPE_MCH_PCI_DEVICE,
637c0907c9eSPaolo Bonzini     .parent = TYPE_PCI_DEVICE,
638c0907c9eSPaolo Bonzini     .instance_size = sizeof(MCHPCIState),
639c0907c9eSPaolo Bonzini     .class_init = mch_class_init,
640fd3b02c8SEduardo Habkost     .interfaces = (InterfaceInfo[]) {
641fd3b02c8SEduardo Habkost         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
642fd3b02c8SEduardo Habkost         { },
643fd3b02c8SEduardo Habkost     },
644c0907c9eSPaolo Bonzini };
645c0907c9eSPaolo Bonzini 
646c0907c9eSPaolo Bonzini static void q35_register(void)
647c0907c9eSPaolo Bonzini {
648c0907c9eSPaolo Bonzini     type_register_static(&mch_info);
649c0907c9eSPaolo Bonzini     type_register_static(&q35_host_info);
650c0907c9eSPaolo Bonzini }
651c0907c9eSPaolo Bonzini 
652c0907c9eSPaolo Bonzini type_init(q35_register);
653