xref: /qemu/hw/pci-host/q35.c (revision bafc90bd)
1c0907c9eSPaolo Bonzini /*
2c0907c9eSPaolo Bonzini  * QEMU MCH/ICH9 PCI Bridge Emulation
3c0907c9eSPaolo Bonzini  *
4c0907c9eSPaolo Bonzini  * Copyright (c) 2006 Fabrice Bellard
5c0907c9eSPaolo Bonzini  * Copyright (c) 2009, 2010, 2011
6c0907c9eSPaolo Bonzini  *               Isaku Yamahata <yamahata at valinux co jp>
7c0907c9eSPaolo Bonzini  *               VA Linux Systems Japan K.K.
8c0907c9eSPaolo Bonzini  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9c0907c9eSPaolo Bonzini  *
10ef9f7b58SGonglei  * This is based on piix.c, but heavily modified.
11c0907c9eSPaolo Bonzini  *
12c0907c9eSPaolo Bonzini  * Permission is hereby granted, free of charge, to any person obtaining a copy
13c0907c9eSPaolo Bonzini  * of this software and associated documentation files (the "Software"), to deal
14c0907c9eSPaolo Bonzini  * in the Software without restriction, including without limitation the rights
15c0907c9eSPaolo Bonzini  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16c0907c9eSPaolo Bonzini  * copies of the Software, and to permit persons to whom the Software is
17c0907c9eSPaolo Bonzini  * furnished to do so, subject to the following conditions:
18c0907c9eSPaolo Bonzini  *
19c0907c9eSPaolo Bonzini  * The above copyright notice and this permission notice shall be included in
20c0907c9eSPaolo Bonzini  * all copies or substantial portions of the Software.
21c0907c9eSPaolo Bonzini  *
22c0907c9eSPaolo Bonzini  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23c0907c9eSPaolo Bonzini  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24c0907c9eSPaolo Bonzini  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25c0907c9eSPaolo Bonzini  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26c0907c9eSPaolo Bonzini  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27c0907c9eSPaolo Bonzini  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28c0907c9eSPaolo Bonzini  * THE SOFTWARE.
29c0907c9eSPaolo Bonzini  */
30c0907c9eSPaolo Bonzini #include "hw/hw.h"
31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h"
3239848901SIgor Mammedov #include "qapi/visitor.h"
33c0907c9eSPaolo Bonzini 
34c0907c9eSPaolo Bonzini /****************************************************************************
35c0907c9eSPaolo Bonzini  * Q35 host
36c0907c9eSPaolo Bonzini  */
37c0907c9eSPaolo Bonzini 
3862d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp)
39c0907c9eSPaolo Bonzini {
40ce88812fSHu Tao     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
41ce88812fSHu Tao     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
4262d92e43SHu Tao     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
43c0907c9eSPaolo Bonzini 
4462d92e43SHu Tao     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
4562d92e43SHu Tao     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
46c0907c9eSPaolo Bonzini 
4762d92e43SHu Tao     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
4862d92e43SHu Tao     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
49c0907c9eSPaolo Bonzini 
50ce88812fSHu Tao     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
51c0907c9eSPaolo Bonzini                            s->mch.pci_address_space, s->mch.address_space_io,
52c0907c9eSPaolo Bonzini                            0, TYPE_PCIE_BUS);
53ce88812fSHu Tao     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
54c0907c9eSPaolo Bonzini     qdev_init_nofail(DEVICE(&s->mch));
55c0907c9eSPaolo Bonzini }
56c0907c9eSPaolo Bonzini 
57568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
58568f0690SDavid Gibson                                           PCIBus *rootbus)
59568f0690SDavid Gibson {
6004c7d8b8SCole Robinson     Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
6104c7d8b8SCole Robinson 
62568f0690SDavid Gibson      /* For backwards compat with old device paths */
6304c7d8b8SCole Robinson     if (s->mch.short_root_bus) {
64568f0690SDavid Gibson         return "0000";
65568f0690SDavid Gibson     }
6604c7d8b8SCole Robinson     return "0000:00";
6704c7d8b8SCole Robinson }
68568f0690SDavid Gibson 
6939848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
7039848901SIgor Mammedov                                         void *opaque, const char *name,
7139848901SIgor Mammedov                                         Error **errp)
7239848901SIgor Mammedov {
7339848901SIgor Mammedov     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
7439848901SIgor Mammedov     uint32_t value = s->mch.pci_info.w32.begin;
7539848901SIgor Mammedov 
7639848901SIgor Mammedov     visit_type_uint32(v, &value, name, errp);
7739848901SIgor Mammedov }
7839848901SIgor Mammedov 
7939848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
8039848901SIgor Mammedov                                       void *opaque, const char *name,
8139848901SIgor Mammedov                                       Error **errp)
8239848901SIgor Mammedov {
8339848901SIgor Mammedov     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
8439848901SIgor Mammedov     uint32_t value = s->mch.pci_info.w32.end;
8539848901SIgor Mammedov 
8639848901SIgor Mammedov     visit_type_uint32(v, &value, name, errp);
8739848901SIgor Mammedov }
8839848901SIgor Mammedov 
8939848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
9039848901SIgor Mammedov                                           void *opaque, const char *name,
9139848901SIgor Mammedov                                           Error **errp)
9239848901SIgor Mammedov {
938b42d730SMichael S. Tsirkin     PCIHostState *h = PCI_HOST_BRIDGE(obj);
948b42d730SMichael S. Tsirkin     Range w64;
9539848901SIgor Mammedov 
968b42d730SMichael S. Tsirkin     pci_bus_get_w64_range(h->bus, &w64);
978b42d730SMichael S. Tsirkin 
988b42d730SMichael S. Tsirkin     visit_type_uint64(v, &w64.begin, name, errp);
9939848901SIgor Mammedov }
10039848901SIgor Mammedov 
10139848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
10239848901SIgor Mammedov                                         void *opaque, const char *name,
10339848901SIgor Mammedov                                         Error **errp)
10439848901SIgor Mammedov {
1058b42d730SMichael S. Tsirkin     PCIHostState *h = PCI_HOST_BRIDGE(obj);
1068b42d730SMichael S. Tsirkin     Range w64;
10739848901SIgor Mammedov 
1088b42d730SMichael S. Tsirkin     pci_bus_get_w64_range(h->bus, &w64);
1098b42d730SMichael S. Tsirkin 
1108b42d730SMichael S. Tsirkin     visit_type_uint64(v, &w64.end, name, errp);
11139848901SIgor Mammedov }
11239848901SIgor Mammedov 
113cbcaf79eSMichael S. Tsirkin static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
114cbcaf79eSMichael S. Tsirkin                                     void *opaque, const char *name,
115cbcaf79eSMichael S. Tsirkin                                     Error **errp)
116cbcaf79eSMichael S. Tsirkin {
117cbcaf79eSMichael S. Tsirkin     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
118cbcaf79eSMichael S. Tsirkin     uint32_t value = e->size;
119cbcaf79eSMichael S. Tsirkin 
120cbcaf79eSMichael S. Tsirkin     visit_type_uint32(v, &value, name, errp);
121cbcaf79eSMichael S. Tsirkin }
122cbcaf79eSMichael S. Tsirkin 
123c0907c9eSPaolo Bonzini static Property mch_props[] = {
12487f65245SMichael S. Tsirkin     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
125c0907c9eSPaolo Bonzini                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
12639848901SIgor Mammedov     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
12739848901SIgor Mammedov                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
12804c7d8b8SCole Robinson     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
129c0907c9eSPaolo Bonzini     DEFINE_PROP_END_OF_LIST(),
130c0907c9eSPaolo Bonzini };
131c0907c9eSPaolo Bonzini 
132c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data)
133c0907c9eSPaolo Bonzini {
134c0907c9eSPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
135568f0690SDavid Gibson     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
136c0907c9eSPaolo Bonzini 
137568f0690SDavid Gibson     hc->root_bus_path = q35_host_root_bus_path;
13862d92e43SHu Tao     dc->realize = q35_host_realize;
139c0907c9eSPaolo Bonzini     dc->props = mch_props;
140125ee0edSMarcel Apfelbaum     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
14168c0e134SMichael S. Tsirkin     dc->fw_name = "pci";
142c0907c9eSPaolo Bonzini }
143c0907c9eSPaolo Bonzini 
144c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj)
145c0907c9eSPaolo Bonzini {
146c0907c9eSPaolo Bonzini     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
14762d92e43SHu Tao     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
14862d92e43SHu Tao 
14962d92e43SHu Tao     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
15062d92e43SHu Tao                           "pci-conf-idx", 4);
15162d92e43SHu Tao     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
15262d92e43SHu Tao                           "pci-conf-data", 4);
153c0907c9eSPaolo Bonzini 
154213f0c4fSAndreas Färber     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
155c0907c9eSPaolo Bonzini     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
156c0907c9eSPaolo Bonzini     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
157c0907c9eSPaolo Bonzini     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
15839848901SIgor Mammedov 
15939848901SIgor Mammedov     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
16039848901SIgor Mammedov                         q35_host_get_pci_hole_start,
16139848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
16239848901SIgor Mammedov 
16339848901SIgor Mammedov     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
16439848901SIgor Mammedov                         q35_host_get_pci_hole_end,
16539848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
16639848901SIgor Mammedov 
16739848901SIgor Mammedov     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
16839848901SIgor Mammedov                         q35_host_get_pci_hole64_start,
16939848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
17039848901SIgor Mammedov 
17139848901SIgor Mammedov     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
17239848901SIgor Mammedov                         q35_host_get_pci_hole64_end,
17339848901SIgor Mammedov                         NULL, NULL, NULL, NULL);
17439848901SIgor Mammedov 
175cbcaf79eSMichael S. Tsirkin     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
176cbcaf79eSMichael S. Tsirkin                         q35_host_get_mmcfg_size,
177cbcaf79eSMichael S. Tsirkin                         NULL, NULL, NULL, NULL);
178cbcaf79eSMichael S. Tsirkin 
17939848901SIgor Mammedov     /* Leave enough space for the biggest MCFG BAR */
18039848901SIgor Mammedov     /* TODO: this matches current bios behaviour, but
18139848901SIgor Mammedov      * it's not a power of two, which means an MTRR
18239848901SIgor Mammedov      * can't cover it exactly.
18339848901SIgor Mammedov      */
18439848901SIgor Mammedov     s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
18539848901SIgor Mammedov         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
18639848901SIgor Mammedov     s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
187c0907c9eSPaolo Bonzini }
188c0907c9eSPaolo Bonzini 
189c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = {
190c0907c9eSPaolo Bonzini     .name       = TYPE_Q35_HOST_DEVICE,
191c0907c9eSPaolo Bonzini     .parent     = TYPE_PCIE_HOST_BRIDGE,
192c0907c9eSPaolo Bonzini     .instance_size = sizeof(Q35PCIHost),
193c0907c9eSPaolo Bonzini     .instance_init = q35_host_initfn,
194c0907c9eSPaolo Bonzini     .class_init = q35_host_class_init,
195c0907c9eSPaolo Bonzini };
196c0907c9eSPaolo Bonzini 
197c0907c9eSPaolo Bonzini /****************************************************************************
198c0907c9eSPaolo Bonzini  * MCH D0:F0
199c0907c9eSPaolo Bonzini  */
200c0907c9eSPaolo Bonzini 
201*bafc90bdSGerd Hoffmann static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
202*bafc90bdSGerd Hoffmann {
203*bafc90bdSGerd Hoffmann     return 0xffffffff;
204*bafc90bdSGerd Hoffmann }
205*bafc90bdSGerd Hoffmann 
206*bafc90bdSGerd Hoffmann static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
207*bafc90bdSGerd Hoffmann                                  unsigned width)
208*bafc90bdSGerd Hoffmann {
209*bafc90bdSGerd Hoffmann     /* nothing */
210*bafc90bdSGerd Hoffmann }
211*bafc90bdSGerd Hoffmann 
212*bafc90bdSGerd Hoffmann static const MemoryRegionOps tseg_blackhole_ops = {
213*bafc90bdSGerd Hoffmann     .read = tseg_blackhole_read,
214*bafc90bdSGerd Hoffmann     .write = tseg_blackhole_write,
215*bafc90bdSGerd Hoffmann     .endianness = DEVICE_NATIVE_ENDIAN,
216*bafc90bdSGerd Hoffmann     .valid.min_access_size = 1,
217*bafc90bdSGerd Hoffmann     .valid.max_access_size = 4,
218*bafc90bdSGerd Hoffmann     .impl.min_access_size = 4,
219*bafc90bdSGerd Hoffmann     .impl.max_access_size = 4,
220*bafc90bdSGerd Hoffmann     .endianness = DEVICE_LITTLE_ENDIAN,
221*bafc90bdSGerd Hoffmann };
222*bafc90bdSGerd Hoffmann 
223c0907c9eSPaolo Bonzini /* PCIe MMCFG */
224c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch)
225c0907c9eSPaolo Bonzini {
226ce88812fSHu Tao     PCIDevice *pci_dev = PCI_DEVICE(mch);
227ce88812fSHu Tao     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
228ce88812fSHu Tao     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
229c0907c9eSPaolo Bonzini 
230c0907c9eSPaolo Bonzini     uint64_t pciexbar;
231c0907c9eSPaolo Bonzini     int enable;
232c0907c9eSPaolo Bonzini     uint64_t addr;
233c0907c9eSPaolo Bonzini     uint64_t addr_mask;
234c0907c9eSPaolo Bonzini     uint32_t length;
235c0907c9eSPaolo Bonzini 
236c0907c9eSPaolo Bonzini     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
237c0907c9eSPaolo Bonzini     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
238c0907c9eSPaolo Bonzini     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
239c0907c9eSPaolo Bonzini     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
240c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
241c0907c9eSPaolo Bonzini         length = 256 * 1024 * 1024;
242c0907c9eSPaolo Bonzini         break;
243c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
244c0907c9eSPaolo Bonzini         length = 128 * 1024 * 1024;
245c0907c9eSPaolo Bonzini         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
246c0907c9eSPaolo Bonzini             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
247c0907c9eSPaolo Bonzini         break;
248c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
249c0907c9eSPaolo Bonzini         length = 64 * 1024 * 1024;
250c0907c9eSPaolo Bonzini         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
251c0907c9eSPaolo Bonzini         break;
252c0907c9eSPaolo Bonzini     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
253c0907c9eSPaolo Bonzini     default:
254c0907c9eSPaolo Bonzini         enable = 0;
255c0907c9eSPaolo Bonzini         length = 0;
256c0907c9eSPaolo Bonzini         abort();
257c0907c9eSPaolo Bonzini         break;
258c0907c9eSPaolo Bonzini     }
259c0907c9eSPaolo Bonzini     addr = pciexbar & addr_mask;
260ce88812fSHu Tao     pcie_host_mmcfg_update(pehb, enable, addr, length);
261636228a8SMichael S. Tsirkin     /* Leave enough space for the MCFG BAR */
262636228a8SMichael S. Tsirkin     /*
263636228a8SMichael S. Tsirkin      * TODO: this matches current bios behaviour, but it's not a power of two,
264636228a8SMichael S. Tsirkin      * which means an MTRR can't cover it exactly.
265636228a8SMichael S. Tsirkin      */
266636228a8SMichael S. Tsirkin     if (enable) {
267636228a8SMichael S. Tsirkin         mch->pci_info.w32.begin = addr + length;
268636228a8SMichael S. Tsirkin     } else {
269636228a8SMichael S. Tsirkin         mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
270636228a8SMichael S. Tsirkin     }
271c0907c9eSPaolo Bonzini }
272c0907c9eSPaolo Bonzini 
273c0907c9eSPaolo Bonzini /* PAM */
274c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch)
275c0907c9eSPaolo Bonzini {
276ce88812fSHu Tao     PCIDevice *pd = PCI_DEVICE(mch);
277c0907c9eSPaolo Bonzini     int i;
278c0907c9eSPaolo Bonzini 
279c0907c9eSPaolo Bonzini     memory_region_transaction_begin();
280c0907c9eSPaolo Bonzini     for (i = 0; i < 13; i++) {
281c0907c9eSPaolo Bonzini         pam_update(&mch->pam_regions[i], i,
282ce88812fSHu Tao                    pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
283c0907c9eSPaolo Bonzini     }
284c0907c9eSPaolo Bonzini     memory_region_transaction_commit();
285c0907c9eSPaolo Bonzini }
286c0907c9eSPaolo Bonzini 
287c0907c9eSPaolo Bonzini /* SMRAM */
288c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch)
289c0907c9eSPaolo Bonzini {
290ce88812fSHu Tao     PCIDevice *pd = PCI_DEVICE(mch);
29164130fa4SPaolo Bonzini     bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
292*bafc90bdSGerd Hoffmann     uint32_t tseg_size;
293ce88812fSHu Tao 
29468c77acfSGerd Hoffmann     /* implement SMRAM.D_LCK */
29568c77acfSGerd Hoffmann     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
29668c77acfSGerd Hoffmann         pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
29768c77acfSGerd Hoffmann         pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
29868c77acfSGerd Hoffmann         pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
29968c77acfSGerd Hoffmann     }
30068c77acfSGerd Hoffmann 
301c0907c9eSPaolo Bonzini     memory_region_transaction_begin();
30264130fa4SPaolo Bonzini 
30364130fa4SPaolo Bonzini     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
30464130fa4SPaolo Bonzini         /* Hide (!) low SMRAM if H_SMRAME = 1 */
30564130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->smram_region, h_smrame);
30664130fa4SPaolo Bonzini         /* Show high SMRAM if H_SMRAME = 1 */
30764130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->open_high_smram, h_smrame);
30864130fa4SPaolo Bonzini     } else {
30964130fa4SPaolo Bonzini         /* Hide high SMRAM and low SMRAM */
31064130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->smram_region, true);
31164130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->open_high_smram, false);
31264130fa4SPaolo Bonzini     }
31364130fa4SPaolo Bonzini 
31464130fa4SPaolo Bonzini     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
31564130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->low_smram, !h_smrame);
31664130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->high_smram, h_smrame);
31764130fa4SPaolo Bonzini     } else {
31864130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->low_smram, false);
31964130fa4SPaolo Bonzini         memory_region_set_enabled(&mch->high_smram, false);
32064130fa4SPaolo Bonzini     }
32164130fa4SPaolo Bonzini 
322*bafc90bdSGerd Hoffmann     if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
323*bafc90bdSGerd Hoffmann         switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
324*bafc90bdSGerd Hoffmann                 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
325*bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
326*bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024;
327*bafc90bdSGerd Hoffmann             break;
328*bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
329*bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024 * 2;
330*bafc90bdSGerd Hoffmann             break;
331*bafc90bdSGerd Hoffmann         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
332*bafc90bdSGerd Hoffmann             tseg_size = 1024 * 1024 * 8;
333*bafc90bdSGerd Hoffmann             break;
334*bafc90bdSGerd Hoffmann         default:
335*bafc90bdSGerd Hoffmann             tseg_size = 0;
336*bafc90bdSGerd Hoffmann             break;
337*bafc90bdSGerd Hoffmann         }
338*bafc90bdSGerd Hoffmann     } else {
339*bafc90bdSGerd Hoffmann         tseg_size = 0;
340*bafc90bdSGerd Hoffmann     }
341*bafc90bdSGerd Hoffmann     memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
342*bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
343*bafc90bdSGerd Hoffmann     memory_region_set_size(&mch->tseg_blackhole, tseg_size);
344*bafc90bdSGerd Hoffmann     memory_region_add_subregion_overlap(mch->system_memory,
345*bafc90bdSGerd Hoffmann                                         mch->below_4g_mem_size - tseg_size,
346*bafc90bdSGerd Hoffmann                                         &mch->tseg_blackhole, 1);
347*bafc90bdSGerd Hoffmann 
348*bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_window, tseg_size);
349*bafc90bdSGerd Hoffmann     memory_region_set_size(&mch->tseg_window, tseg_size);
350*bafc90bdSGerd Hoffmann     memory_region_set_address(&mch->tseg_window,
351*bafc90bdSGerd Hoffmann                               mch->below_4g_mem_size - tseg_size);
352*bafc90bdSGerd Hoffmann     memory_region_set_alias_offset(&mch->tseg_window,
353*bafc90bdSGerd Hoffmann                                    mch->below_4g_mem_size - tseg_size);
354*bafc90bdSGerd Hoffmann 
355c0907c9eSPaolo Bonzini     memory_region_transaction_commit();
356c0907c9eSPaolo Bonzini }
357c0907c9eSPaolo Bonzini 
358c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d,
359c0907c9eSPaolo Bonzini                               uint32_t address, uint32_t val, int len)
360c0907c9eSPaolo Bonzini {
361c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
362c0907c9eSPaolo Bonzini 
363c0907c9eSPaolo Bonzini     pci_default_write_config(d, address, val, len);
364c0907c9eSPaolo Bonzini 
365c0907c9eSPaolo Bonzini     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
366c0907c9eSPaolo Bonzini                        MCH_HOST_BRIDGE_PAM_SIZE)) {
367c0907c9eSPaolo Bonzini         mch_update_pam(mch);
368c0907c9eSPaolo Bonzini     }
369c0907c9eSPaolo Bonzini 
370c0907c9eSPaolo Bonzini     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
371c0907c9eSPaolo Bonzini                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
372c0907c9eSPaolo Bonzini         mch_update_pciexbar(mch);
373c0907c9eSPaolo Bonzini     }
374c0907c9eSPaolo Bonzini 
375263cf436SBALATON Zoltan     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
376263cf436SBALATON Zoltan                        MCH_HOST_BRIDGE_SMRAM_SIZE)) {
377c0907c9eSPaolo Bonzini         mch_update_smram(mch);
378c0907c9eSPaolo Bonzini     }
379c0907c9eSPaolo Bonzini }
380c0907c9eSPaolo Bonzini 
381c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch)
382c0907c9eSPaolo Bonzini {
383c0907c9eSPaolo Bonzini     mch_update_pciexbar(mch);
384c0907c9eSPaolo Bonzini     mch_update_pam(mch);
385c0907c9eSPaolo Bonzini     mch_update_smram(mch);
386c0907c9eSPaolo Bonzini }
387c0907c9eSPaolo Bonzini 
388c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id)
389c0907c9eSPaolo Bonzini {
390c0907c9eSPaolo Bonzini     MCHPCIState *mch = opaque;
391c0907c9eSPaolo Bonzini     mch_update(mch);
392c0907c9eSPaolo Bonzini     return 0;
393c0907c9eSPaolo Bonzini }
394c0907c9eSPaolo Bonzini 
395c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = {
396c0907c9eSPaolo Bonzini     .name = "mch",
397c0907c9eSPaolo Bonzini     .version_id = 1,
398c0907c9eSPaolo Bonzini     .minimum_version_id = 1,
399c0907c9eSPaolo Bonzini     .post_load = mch_post_load,
400c0907c9eSPaolo Bonzini     .fields = (VMStateField[]) {
401ce88812fSHu Tao         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
402f809c605SPaolo Bonzini         /* Used to be smm_enabled, which was basically always zero because
403f809c605SPaolo Bonzini          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
404f809c605SPaolo Bonzini          */
405f809c605SPaolo Bonzini         VMSTATE_UNUSED(1),
406c0907c9eSPaolo Bonzini         VMSTATE_END_OF_LIST()
407c0907c9eSPaolo Bonzini     }
408c0907c9eSPaolo Bonzini };
409c0907c9eSPaolo Bonzini 
410c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev)
411c0907c9eSPaolo Bonzini {
412c0907c9eSPaolo Bonzini     PCIDevice *d = PCI_DEVICE(qdev);
413c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
414c0907c9eSPaolo Bonzini 
415c0907c9eSPaolo Bonzini     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
416c0907c9eSPaolo Bonzini                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
417c0907c9eSPaolo Bonzini 
418263cf436SBALATON Zoltan     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
41977447524SGerd Hoffmann     d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
420b66a67d7SGerd Hoffmann     d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
421b66a67d7SGerd Hoffmann     d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
422c0907c9eSPaolo Bonzini 
423c0907c9eSPaolo Bonzini     mch_update(mch);
424c0907c9eSPaolo Bonzini }
425c0907c9eSPaolo Bonzini 
426a52a7fdfSLe Tan static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
427a52a7fdfSLe Tan {
428a52a7fdfSLe Tan     IntelIOMMUState *s = opaque;
429a52a7fdfSLe Tan     VTDAddressSpace **pvtd_as;
430a52a7fdfSLe Tan     int bus_num = pci_bus_num(bus);
431a52a7fdfSLe Tan 
432a52a7fdfSLe Tan     assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
433a52a7fdfSLe Tan     assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
434a52a7fdfSLe Tan 
435a52a7fdfSLe Tan     pvtd_as = s->address_spaces[bus_num];
436a52a7fdfSLe Tan     if (!pvtd_as) {
437a52a7fdfSLe Tan         /* No corresponding free() */
438a52a7fdfSLe Tan         pvtd_as = g_malloc0(sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX);
439a52a7fdfSLe Tan         s->address_spaces[bus_num] = pvtd_as;
440a52a7fdfSLe Tan     }
441a52a7fdfSLe Tan     if (!pvtd_as[devfn]) {
442a52a7fdfSLe Tan         pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace));
443a52a7fdfSLe Tan 
444a52a7fdfSLe Tan         pvtd_as[devfn]->bus_num = (uint8_t)bus_num;
445a52a7fdfSLe Tan         pvtd_as[devfn]->devfn = (uint8_t)devfn;
446a52a7fdfSLe Tan         pvtd_as[devfn]->iommu_state = s;
447d92fa2dcSLe Tan         pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0;
448a52a7fdfSLe Tan         memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s),
449a52a7fdfSLe Tan                                  &s->iommu_ops, "intel_iommu", UINT64_MAX);
450a52a7fdfSLe Tan         address_space_init(&pvtd_as[devfn]->as,
451a52a7fdfSLe Tan                            &pvtd_as[devfn]->iommu, "intel_iommu");
452a52a7fdfSLe Tan     }
453a52a7fdfSLe Tan     return &pvtd_as[devfn]->as;
454a52a7fdfSLe Tan }
455a52a7fdfSLe Tan 
456a52a7fdfSLe Tan static void mch_init_dmar(MCHPCIState *mch)
457a52a7fdfSLe Tan {
458a52a7fdfSLe Tan     PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));
459a52a7fdfSLe Tan 
460a52a7fdfSLe Tan     mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
461a52a7fdfSLe Tan     object_property_add_child(OBJECT(mch), "intel-iommu",
462a52a7fdfSLe Tan                               OBJECT(mch->iommu), NULL);
463a52a7fdfSLe Tan     qdev_init_nofail(DEVICE(mch->iommu));
464a52a7fdfSLe Tan     sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
465a52a7fdfSLe Tan 
466a52a7fdfSLe Tan     pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
467a52a7fdfSLe Tan }
468a52a7fdfSLe Tan 
4699af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp)
470c0907c9eSPaolo Bonzini {
471c0907c9eSPaolo Bonzini     int i;
472c0907c9eSPaolo Bonzini     MCHPCIState *mch = MCH_PCI_DEVICE(d);
473c0907c9eSPaolo Bonzini 
47483d08f26SMichael S. Tsirkin     /* setup pci memory mapping */
47583d08f26SMichael S. Tsirkin     pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
47683d08f26SMichael S. Tsirkin                            mch->pci_address_space);
47739848901SIgor Mammedov 
478fe6567d5SPaolo Bonzini     /* if *disabled* show SMRAM to all CPUs */
47940c5dce9SPaolo Bonzini     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
480c0907c9eSPaolo Bonzini                              mch->pci_address_space, 0xa0000, 0x20000);
481c0907c9eSPaolo Bonzini     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
482c0907c9eSPaolo Bonzini                                         &mch->smram_region, 1);
483fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->smram_region, true);
484fe6567d5SPaolo Bonzini 
48564130fa4SPaolo Bonzini     memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
48664130fa4SPaolo Bonzini                              mch->ram_memory, 0xa0000, 0x20000);
48764130fa4SPaolo Bonzini     memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
48864130fa4SPaolo Bonzini                                         &mch->open_high_smram, 1);
48964130fa4SPaolo Bonzini     memory_region_set_enabled(&mch->open_high_smram, false);
49064130fa4SPaolo Bonzini 
491fe6567d5SPaolo Bonzini     /* smram, as seen by SMM CPUs */
492fe6567d5SPaolo Bonzini     memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
493fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->smram, true);
494fe6567d5SPaolo Bonzini     memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
495f809c605SPaolo Bonzini                              mch->ram_memory, 0xa0000, 0x20000);
496fe6567d5SPaolo Bonzini     memory_region_set_enabled(&mch->low_smram, true);
497fe6567d5SPaolo Bonzini     memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
49864130fa4SPaolo Bonzini     memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
49964130fa4SPaolo Bonzini                              mch->ram_memory, 0xa0000, 0x20000);
50064130fa4SPaolo Bonzini     memory_region_set_enabled(&mch->high_smram, true);
50164130fa4SPaolo Bonzini     memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
502*bafc90bdSGerd Hoffmann 
503*bafc90bdSGerd Hoffmann     memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
504*bafc90bdSGerd Hoffmann                           &tseg_blackhole_ops, NULL,
505*bafc90bdSGerd Hoffmann                           "tseg-blackhole", 0);
506*bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_blackhole, false);
507*bafc90bdSGerd Hoffmann     memory_region_add_subregion_overlap(mch->system_memory,
508*bafc90bdSGerd Hoffmann                                         mch->below_4g_mem_size,
509*bafc90bdSGerd Hoffmann                                         &mch->tseg_blackhole, 1);
510*bafc90bdSGerd Hoffmann 
511*bafc90bdSGerd Hoffmann     memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
512*bafc90bdSGerd Hoffmann                              mch->ram_memory, mch->below_4g_mem_size, 0);
513*bafc90bdSGerd Hoffmann     memory_region_set_enabled(&mch->tseg_window, false);
514*bafc90bdSGerd Hoffmann     memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
515*bafc90bdSGerd Hoffmann                                 &mch->tseg_window);
516fe6567d5SPaolo Bonzini     object_property_add_const_link(qdev_get_machine(), "smram",
517fe6567d5SPaolo Bonzini                                    OBJECT(&mch->smram), &error_abort);
518fe6567d5SPaolo Bonzini 
519ac40aa15SLe Tan     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
520ac40aa15SLe Tan              mch->pci_address_space, &mch->pam_regions[0],
521ac40aa15SLe Tan              PAM_BIOS_BASE, PAM_BIOS_SIZE);
522c0907c9eSPaolo Bonzini     for (i = 0; i < 12; ++i) {
523ac40aa15SLe Tan         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
524ac40aa15SLe Tan                  mch->pci_address_space, &mch->pam_regions[i+1],
525ac40aa15SLe Tan                  PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
526c0907c9eSPaolo Bonzini     }
527a52a7fdfSLe Tan     /* Intel IOMMU (VT-d) */
5288caff636SMarcel Apfelbaum     if (machine_iommu(current_machine)) {
529a52a7fdfSLe Tan         mch_init_dmar(mch);
530a52a7fdfSLe Tan     }
531c0907c9eSPaolo Bonzini }
532c0907c9eSPaolo Bonzini 
5336f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void)
5346f1426abSMichael S. Tsirkin {
5356f1426abSMichael S. Tsirkin     bool ambiguous;
5366f1426abSMichael S. Tsirkin     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
5376f1426abSMichael S. Tsirkin     if (!o) {
5386f1426abSMichael S. Tsirkin         return 0;
5396f1426abSMichael S. Tsirkin     }
5406f1426abSMichael S. Tsirkin     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
5416f1426abSMichael S. Tsirkin }
5426f1426abSMichael S. Tsirkin 
543c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data)
544c0907c9eSPaolo Bonzini {
545c0907c9eSPaolo Bonzini     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
546c0907c9eSPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
547c0907c9eSPaolo Bonzini 
5489af21dbeSMarkus Armbruster     k->realize = mch_realize;
549c0907c9eSPaolo Bonzini     k->config_write = mch_write_config;
550c0907c9eSPaolo Bonzini     dc->reset = mch_reset;
551125ee0edSMarcel Apfelbaum     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
552c0907c9eSPaolo Bonzini     dc->desc = "Host bridge";
553c0907c9eSPaolo Bonzini     dc->vmsd = &vmstate_mch;
554c0907c9eSPaolo Bonzini     k->vendor_id = PCI_VENDOR_ID_INTEL;
555c0907c9eSPaolo Bonzini     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
556451f7846SRichard W.M. Jones     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
557c0907c9eSPaolo Bonzini     k->class_id = PCI_CLASS_BRIDGE_HOST;
55808c58f92SMarkus Armbruster     /*
55908c58f92SMarkus Armbruster      * PCI-facing part of the host bridge, not usable without the
56008c58f92SMarkus Armbruster      * host-facing part, which can't be device_add'ed, yet.
56108c58f92SMarkus Armbruster      */
56208c58f92SMarkus Armbruster     dc->cannot_instantiate_with_device_add_yet = true;
563c0907c9eSPaolo Bonzini }
564c0907c9eSPaolo Bonzini 
565c0907c9eSPaolo Bonzini static const TypeInfo mch_info = {
566c0907c9eSPaolo Bonzini     .name = TYPE_MCH_PCI_DEVICE,
567c0907c9eSPaolo Bonzini     .parent = TYPE_PCI_DEVICE,
568c0907c9eSPaolo Bonzini     .instance_size = sizeof(MCHPCIState),
569c0907c9eSPaolo Bonzini     .class_init = mch_class_init,
570c0907c9eSPaolo Bonzini };
571c0907c9eSPaolo Bonzini 
572c0907c9eSPaolo Bonzini static void q35_register(void)
573c0907c9eSPaolo Bonzini {
574c0907c9eSPaolo Bonzini     type_register_static(&mch_info);
575c0907c9eSPaolo Bonzini     type_register_static(&q35_host_info);
576c0907c9eSPaolo Bonzini }
577c0907c9eSPaolo Bonzini 
578c0907c9eSPaolo Bonzini type_init(q35_register);
579