1*c0907c9eSPaolo Bonzini /* 2*c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3*c0907c9eSPaolo Bonzini * 4*c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5*c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6*c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7*c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8*c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9*c0907c9eSPaolo Bonzini * 10*c0907c9eSPaolo Bonzini * This is based on piix_pci.c, but heavily modified. 11*c0907c9eSPaolo Bonzini * 12*c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13*c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14*c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15*c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16*c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17*c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18*c0907c9eSPaolo Bonzini * 19*c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20*c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21*c0907c9eSPaolo Bonzini * 22*c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23*c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24*c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25*c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26*c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27*c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28*c0907c9eSPaolo Bonzini * THE SOFTWARE. 29*c0907c9eSPaolo Bonzini */ 30*c0907c9eSPaolo Bonzini #include "hw/hw.h" 31*c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 32*c0907c9eSPaolo Bonzini 33*c0907c9eSPaolo Bonzini /**************************************************************************** 34*c0907c9eSPaolo Bonzini * Q35 host 35*c0907c9eSPaolo Bonzini */ 36*c0907c9eSPaolo Bonzini 37*c0907c9eSPaolo Bonzini static int q35_host_init(SysBusDevice *dev) 38*c0907c9eSPaolo Bonzini { 39*c0907c9eSPaolo Bonzini PCIBus *b; 40*c0907c9eSPaolo Bonzini PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); 41*c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); 42*c0907c9eSPaolo Bonzini 43*c0907c9eSPaolo Bonzini memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, 44*c0907c9eSPaolo Bonzini "pci-conf-idx", 4); 45*c0907c9eSPaolo Bonzini sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 46*c0907c9eSPaolo Bonzini sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 47*c0907c9eSPaolo Bonzini 48*c0907c9eSPaolo Bonzini memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, 49*c0907c9eSPaolo Bonzini "pci-conf-data", 4); 50*c0907c9eSPaolo Bonzini sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 51*c0907c9eSPaolo Bonzini sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 52*c0907c9eSPaolo Bonzini 53*c0907c9eSPaolo Bonzini if (pcie_host_init(&s->host) < 0) { 54*c0907c9eSPaolo Bonzini return -1; 55*c0907c9eSPaolo Bonzini } 56*c0907c9eSPaolo Bonzini b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", 57*c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 58*c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 59*c0907c9eSPaolo Bonzini s->host.pci.bus = b; 60*c0907c9eSPaolo Bonzini qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); 61*c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 62*c0907c9eSPaolo Bonzini 63*c0907c9eSPaolo Bonzini return 0; 64*c0907c9eSPaolo Bonzini } 65*c0907c9eSPaolo Bonzini 66*c0907c9eSPaolo Bonzini static Property mch_props[] = { 67*c0907c9eSPaolo Bonzini DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, 68*c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 69*c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 70*c0907c9eSPaolo Bonzini }; 71*c0907c9eSPaolo Bonzini 72*c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 73*c0907c9eSPaolo Bonzini { 74*c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 75*c0907c9eSPaolo Bonzini SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 76*c0907c9eSPaolo Bonzini 77*c0907c9eSPaolo Bonzini k->init = q35_host_init; 78*c0907c9eSPaolo Bonzini dc->props = mch_props; 79*c0907c9eSPaolo Bonzini } 80*c0907c9eSPaolo Bonzini 81*c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 82*c0907c9eSPaolo Bonzini { 83*c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 84*c0907c9eSPaolo Bonzini 85*c0907c9eSPaolo Bonzini object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 86*c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 87*c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 88*c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 89*c0907c9eSPaolo Bonzini } 90*c0907c9eSPaolo Bonzini 91*c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 92*c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 93*c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 94*c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 95*c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 96*c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 97*c0907c9eSPaolo Bonzini }; 98*c0907c9eSPaolo Bonzini 99*c0907c9eSPaolo Bonzini /**************************************************************************** 100*c0907c9eSPaolo Bonzini * MCH D0:F0 101*c0907c9eSPaolo Bonzini */ 102*c0907c9eSPaolo Bonzini 103*c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 104*c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 105*c0907c9eSPaolo Bonzini { 106*c0907c9eSPaolo Bonzini PCIDevice *pci_dev = &mch->d; 107*c0907c9eSPaolo Bonzini BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 108*c0907c9eSPaolo Bonzini DeviceState *qdev = bus->parent; 109*c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(qdev); 110*c0907c9eSPaolo Bonzini 111*c0907c9eSPaolo Bonzini uint64_t pciexbar; 112*c0907c9eSPaolo Bonzini int enable; 113*c0907c9eSPaolo Bonzini uint64_t addr; 114*c0907c9eSPaolo Bonzini uint64_t addr_mask; 115*c0907c9eSPaolo Bonzini uint32_t length; 116*c0907c9eSPaolo Bonzini 117*c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 118*c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 119*c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 120*c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 121*c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 122*c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 123*c0907c9eSPaolo Bonzini break; 124*c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 125*c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 126*c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 127*c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 128*c0907c9eSPaolo Bonzini break; 129*c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 130*c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 131*c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 132*c0907c9eSPaolo Bonzini break; 133*c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 134*c0907c9eSPaolo Bonzini default: 135*c0907c9eSPaolo Bonzini enable = 0; 136*c0907c9eSPaolo Bonzini length = 0; 137*c0907c9eSPaolo Bonzini abort(); 138*c0907c9eSPaolo Bonzini break; 139*c0907c9eSPaolo Bonzini } 140*c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 141*c0907c9eSPaolo Bonzini pcie_host_mmcfg_update(&s->host, enable, addr, length); 142*c0907c9eSPaolo Bonzini } 143*c0907c9eSPaolo Bonzini 144*c0907c9eSPaolo Bonzini /* PAM */ 145*c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 146*c0907c9eSPaolo Bonzini { 147*c0907c9eSPaolo Bonzini int i; 148*c0907c9eSPaolo Bonzini 149*c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 150*c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 151*c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 152*c0907c9eSPaolo Bonzini mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 153*c0907c9eSPaolo Bonzini } 154*c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 155*c0907c9eSPaolo Bonzini } 156*c0907c9eSPaolo Bonzini 157*c0907c9eSPaolo Bonzini /* SMRAM */ 158*c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 159*c0907c9eSPaolo Bonzini { 160*c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 161*c0907c9eSPaolo Bonzini smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM], 162*c0907c9eSPaolo Bonzini mch->smm_enabled); 163*c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 164*c0907c9eSPaolo Bonzini } 165*c0907c9eSPaolo Bonzini 166*c0907c9eSPaolo Bonzini static void mch_set_smm(int smm, void *arg) 167*c0907c9eSPaolo Bonzini { 168*c0907c9eSPaolo Bonzini MCHPCIState *mch = arg; 169*c0907c9eSPaolo Bonzini 170*c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 171*c0907c9eSPaolo Bonzini smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM], 172*c0907c9eSPaolo Bonzini &mch->smram_region); 173*c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 174*c0907c9eSPaolo Bonzini } 175*c0907c9eSPaolo Bonzini 176*c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 177*c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 178*c0907c9eSPaolo Bonzini { 179*c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 180*c0907c9eSPaolo Bonzini 181*c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 182*c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 183*c0907c9eSPaolo Bonzini 184*c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 185*c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 186*c0907c9eSPaolo Bonzini mch_update_pam(mch); 187*c0907c9eSPaolo Bonzini } 188*c0907c9eSPaolo Bonzini 189*c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 190*c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 191*c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 192*c0907c9eSPaolo Bonzini } 193*c0907c9eSPaolo Bonzini 194*c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 195*c0907c9eSPaolo Bonzini MCH_HOST_BRDIGE_SMRAM_SIZE)) { 196*c0907c9eSPaolo Bonzini mch_update_smram(mch); 197*c0907c9eSPaolo Bonzini } 198*c0907c9eSPaolo Bonzini } 199*c0907c9eSPaolo Bonzini 200*c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 201*c0907c9eSPaolo Bonzini { 202*c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 203*c0907c9eSPaolo Bonzini mch_update_pam(mch); 204*c0907c9eSPaolo Bonzini mch_update_smram(mch); 205*c0907c9eSPaolo Bonzini } 206*c0907c9eSPaolo Bonzini 207*c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 208*c0907c9eSPaolo Bonzini { 209*c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 210*c0907c9eSPaolo Bonzini mch_update(mch); 211*c0907c9eSPaolo Bonzini return 0; 212*c0907c9eSPaolo Bonzini } 213*c0907c9eSPaolo Bonzini 214*c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 215*c0907c9eSPaolo Bonzini .name = "mch", 216*c0907c9eSPaolo Bonzini .version_id = 1, 217*c0907c9eSPaolo Bonzini .minimum_version_id = 1, 218*c0907c9eSPaolo Bonzini .minimum_version_id_old = 1, 219*c0907c9eSPaolo Bonzini .post_load = mch_post_load, 220*c0907c9eSPaolo Bonzini .fields = (VMStateField []) { 221*c0907c9eSPaolo Bonzini VMSTATE_PCI_DEVICE(d, MCHPCIState), 222*c0907c9eSPaolo Bonzini VMSTATE_UINT8(smm_enabled, MCHPCIState), 223*c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 224*c0907c9eSPaolo Bonzini } 225*c0907c9eSPaolo Bonzini }; 226*c0907c9eSPaolo Bonzini 227*c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 228*c0907c9eSPaolo Bonzini { 229*c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 230*c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 231*c0907c9eSPaolo Bonzini 232*c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 233*c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 234*c0907c9eSPaolo Bonzini 235*c0907c9eSPaolo Bonzini d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 236*c0907c9eSPaolo Bonzini 237*c0907c9eSPaolo Bonzini mch_update(mch); 238*c0907c9eSPaolo Bonzini } 239*c0907c9eSPaolo Bonzini 240*c0907c9eSPaolo Bonzini static int mch_init(PCIDevice *d) 241*c0907c9eSPaolo Bonzini { 242*c0907c9eSPaolo Bonzini int i; 243*c0907c9eSPaolo Bonzini hwaddr pci_hole64_size; 244*c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 245*c0907c9eSPaolo Bonzini 246*c0907c9eSPaolo Bonzini /* setup pci memory regions */ 247*c0907c9eSPaolo Bonzini memory_region_init_alias(&mch->pci_hole, "pci-hole", 248*c0907c9eSPaolo Bonzini mch->pci_address_space, 249*c0907c9eSPaolo Bonzini mch->below_4g_mem_size, 250*c0907c9eSPaolo Bonzini 0x100000000ULL - mch->below_4g_mem_size); 251*c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 252*c0907c9eSPaolo Bonzini &mch->pci_hole); 253*c0907c9eSPaolo Bonzini pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : 254*c0907c9eSPaolo Bonzini ((uint64_t)1 << 62)); 255*c0907c9eSPaolo Bonzini memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64", 256*c0907c9eSPaolo Bonzini mch->pci_address_space, 257*c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 258*c0907c9eSPaolo Bonzini pci_hole64_size); 259*c0907c9eSPaolo Bonzini if (pci_hole64_size) { 260*c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, 261*c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 262*c0907c9eSPaolo Bonzini &mch->pci_hole_64bit); 263*c0907c9eSPaolo Bonzini } 264*c0907c9eSPaolo Bonzini /* smram */ 265*c0907c9eSPaolo Bonzini cpu_smm_register(&mch_set_smm, mch); 266*c0907c9eSPaolo Bonzini memory_region_init_alias(&mch->smram_region, "smram-region", 267*c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 268*c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 269*c0907c9eSPaolo Bonzini &mch->smram_region, 1); 270*c0907c9eSPaolo Bonzini memory_region_set_enabled(&mch->smram_region, false); 271*c0907c9eSPaolo Bonzini init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, 272*c0907c9eSPaolo Bonzini &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 273*c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 274*c0907c9eSPaolo Bonzini init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, 275*c0907c9eSPaolo Bonzini &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 276*c0907c9eSPaolo Bonzini PAM_EXPAN_SIZE); 277*c0907c9eSPaolo Bonzini } 278*c0907c9eSPaolo Bonzini return 0; 279*c0907c9eSPaolo Bonzini } 280*c0907c9eSPaolo Bonzini 281*c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 282*c0907c9eSPaolo Bonzini { 283*c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 284*c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 285*c0907c9eSPaolo Bonzini 286*c0907c9eSPaolo Bonzini k->init = mch_init; 287*c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 288*c0907c9eSPaolo Bonzini dc->reset = mch_reset; 289*c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 290*c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 291*c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 292*c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 293*c0907c9eSPaolo Bonzini k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 294*c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 295*c0907c9eSPaolo Bonzini } 296*c0907c9eSPaolo Bonzini 297*c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 298*c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 299*c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 300*c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 301*c0907c9eSPaolo Bonzini .class_init = mch_class_init, 302*c0907c9eSPaolo Bonzini }; 303*c0907c9eSPaolo Bonzini 304*c0907c9eSPaolo Bonzini static void q35_register(void) 305*c0907c9eSPaolo Bonzini { 306*c0907c9eSPaolo Bonzini type_register_static(&mch_info); 307*c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 308*c0907c9eSPaolo Bonzini } 309*c0907c9eSPaolo Bonzini 310*c0907c9eSPaolo Bonzini type_init(q35_register); 311