1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10c0907c9eSPaolo Bonzini * This is based on piix_pci.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30c0907c9eSPaolo Bonzini #include "hw/hw.h" 31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 3239848901SIgor Mammedov #include "qapi/visitor.h" 33c0907c9eSPaolo Bonzini 34c0907c9eSPaolo Bonzini /**************************************************************************** 35c0907c9eSPaolo Bonzini * Q35 host 36c0907c9eSPaolo Bonzini */ 37c0907c9eSPaolo Bonzini 3862d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 39c0907c9eSPaolo Bonzini { 40ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 41ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4262d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 43c0907c9eSPaolo Bonzini 4462d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4562d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46c0907c9eSPaolo Bonzini 4762d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 4862d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 49c0907c9eSPaolo Bonzini 50ce88812fSHu Tao if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 5162d92e43SHu Tao error_setg(errp, "failed to initialize pcie host"); 5262d92e43SHu Tao return; 53c0907c9eSPaolo Bonzini } 54ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 55c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 56c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 57ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 58c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 59c0907c9eSPaolo Bonzini } 60c0907c9eSPaolo Bonzini 61568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 62568f0690SDavid Gibson PCIBus *rootbus) 63568f0690SDavid Gibson { 64568f0690SDavid Gibson /* For backwards compat with old device paths */ 65568f0690SDavid Gibson return "0000"; 66568f0690SDavid Gibson } 67568f0690SDavid Gibson 6839848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 6939848901SIgor Mammedov void *opaque, const char *name, 7039848901SIgor Mammedov Error **errp) 7139848901SIgor Mammedov { 7239848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 7339848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.begin; 7439848901SIgor Mammedov 7539848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 7639848901SIgor Mammedov } 7739848901SIgor Mammedov 7839848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 7939848901SIgor Mammedov void *opaque, const char *name, 8039848901SIgor Mammedov Error **errp) 8139848901SIgor Mammedov { 8239848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 8339848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.end; 8439848901SIgor Mammedov 8539848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 8639848901SIgor Mammedov } 8739848901SIgor Mammedov 8839848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 8939848901SIgor Mammedov void *opaque, const char *name, 9039848901SIgor Mammedov Error **errp) 9139848901SIgor Mammedov { 928b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 938b42d730SMichael S. Tsirkin Range w64; 9439848901SIgor Mammedov 958b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 968b42d730SMichael S. Tsirkin 978b42d730SMichael S. Tsirkin visit_type_uint64(v, &w64.begin, name, errp); 9839848901SIgor Mammedov } 9939848901SIgor Mammedov 10039848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 10139848901SIgor Mammedov void *opaque, const char *name, 10239848901SIgor Mammedov Error **errp) 10339848901SIgor Mammedov { 1048b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1058b42d730SMichael S. Tsirkin Range w64; 10639848901SIgor Mammedov 1078b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 1088b42d730SMichael S. Tsirkin 1098b42d730SMichael S. Tsirkin visit_type_uint64(v, &w64.end, name, errp); 11039848901SIgor Mammedov } 11139848901SIgor Mammedov 112*cbcaf79eSMichael S. Tsirkin static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, 113*cbcaf79eSMichael S. Tsirkin void *opaque, const char *name, 114*cbcaf79eSMichael S. Tsirkin Error **errp) 115*cbcaf79eSMichael S. Tsirkin { 116*cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 117*cbcaf79eSMichael S. Tsirkin uint32_t value = e->size; 118*cbcaf79eSMichael S. Tsirkin 119*cbcaf79eSMichael S. Tsirkin visit_type_uint32(v, &value, name, errp); 120*cbcaf79eSMichael S. Tsirkin } 121*cbcaf79eSMichael S. Tsirkin 122c0907c9eSPaolo Bonzini static Property mch_props[] = { 12387f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 124c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 12539848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 12639848901SIgor Mammedov mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 127c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 128c0907c9eSPaolo Bonzini }; 129c0907c9eSPaolo Bonzini 130c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 131c0907c9eSPaolo Bonzini { 132c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 133568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 134c0907c9eSPaolo Bonzini 135568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 13662d92e43SHu Tao dc->realize = q35_host_realize; 137c0907c9eSPaolo Bonzini dc->props = mch_props; 138125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 13968c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 140c0907c9eSPaolo Bonzini } 141c0907c9eSPaolo Bonzini 142c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 143c0907c9eSPaolo Bonzini { 144c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 14562d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 14662d92e43SHu Tao 14762d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 14862d92e43SHu Tao "pci-conf-idx", 4); 14962d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 15062d92e43SHu Tao "pci-conf-data", 4); 151c0907c9eSPaolo Bonzini 152213f0c4fSAndreas Färber object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 153c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 154c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 155c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 15639848901SIgor Mammedov 15739848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 15839848901SIgor Mammedov q35_host_get_pci_hole_start, 15939848901SIgor Mammedov NULL, NULL, NULL, NULL); 16039848901SIgor Mammedov 16139848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 16239848901SIgor Mammedov q35_host_get_pci_hole_end, 16339848901SIgor Mammedov NULL, NULL, NULL, NULL); 16439848901SIgor Mammedov 16539848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 16639848901SIgor Mammedov q35_host_get_pci_hole64_start, 16739848901SIgor Mammedov NULL, NULL, NULL, NULL); 16839848901SIgor Mammedov 16939848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 17039848901SIgor Mammedov q35_host_get_pci_hole64_end, 17139848901SIgor Mammedov NULL, NULL, NULL, NULL); 17239848901SIgor Mammedov 173*cbcaf79eSMichael S. Tsirkin object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 174*cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 175*cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 176*cbcaf79eSMichael S. Tsirkin 17739848901SIgor Mammedov /* Leave enough space for the biggest MCFG BAR */ 17839848901SIgor Mammedov /* TODO: this matches current bios behaviour, but 17939848901SIgor Mammedov * it's not a power of two, which means an MTRR 18039848901SIgor Mammedov * can't cover it exactly. 18139848901SIgor Mammedov */ 18239848901SIgor Mammedov s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 18339848901SIgor Mammedov MCH_HOST_BRIDGE_PCIEXBAR_MAX; 18439848901SIgor Mammedov s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 185c0907c9eSPaolo Bonzini } 186c0907c9eSPaolo Bonzini 187c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 188c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 189c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 190c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 191c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 192c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 193c0907c9eSPaolo Bonzini }; 194c0907c9eSPaolo Bonzini 195c0907c9eSPaolo Bonzini /**************************************************************************** 196c0907c9eSPaolo Bonzini * MCH D0:F0 197c0907c9eSPaolo Bonzini */ 198c0907c9eSPaolo Bonzini 199c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 200c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 201c0907c9eSPaolo Bonzini { 202ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 203ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 204ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 205c0907c9eSPaolo Bonzini 206c0907c9eSPaolo Bonzini uint64_t pciexbar; 207c0907c9eSPaolo Bonzini int enable; 208c0907c9eSPaolo Bonzini uint64_t addr; 209c0907c9eSPaolo Bonzini uint64_t addr_mask; 210c0907c9eSPaolo Bonzini uint32_t length; 211c0907c9eSPaolo Bonzini 212c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 213c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 214c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 215c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 216c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 217c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 218c0907c9eSPaolo Bonzini break; 219c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 220c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 221c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 222c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 223c0907c9eSPaolo Bonzini break; 224c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 225c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 226c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 227c0907c9eSPaolo Bonzini break; 228c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 229c0907c9eSPaolo Bonzini default: 230c0907c9eSPaolo Bonzini enable = 0; 231c0907c9eSPaolo Bonzini length = 0; 232c0907c9eSPaolo Bonzini abort(); 233c0907c9eSPaolo Bonzini break; 234c0907c9eSPaolo Bonzini } 235c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 236ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 237636228a8SMichael S. Tsirkin /* Leave enough space for the MCFG BAR */ 238636228a8SMichael S. Tsirkin /* 239636228a8SMichael S. Tsirkin * TODO: this matches current bios behaviour, but it's not a power of two, 240636228a8SMichael S. Tsirkin * which means an MTRR can't cover it exactly. 241636228a8SMichael S. Tsirkin */ 242636228a8SMichael S. Tsirkin if (enable) { 243636228a8SMichael S. Tsirkin mch->pci_info.w32.begin = addr + length; 244636228a8SMichael S. Tsirkin } else { 245636228a8SMichael S. Tsirkin mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 246636228a8SMichael S. Tsirkin } 247c0907c9eSPaolo Bonzini } 248c0907c9eSPaolo Bonzini 249c0907c9eSPaolo Bonzini /* PAM */ 250c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 251c0907c9eSPaolo Bonzini { 252ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 253c0907c9eSPaolo Bonzini int i; 254c0907c9eSPaolo Bonzini 255c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 256c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 257c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 258ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 259c0907c9eSPaolo Bonzini } 260c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 261c0907c9eSPaolo Bonzini } 262c0907c9eSPaolo Bonzini 263c0907c9eSPaolo Bonzini /* SMRAM */ 264c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 265c0907c9eSPaolo Bonzini { 266ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 267ce88812fSHu Tao 268c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 269ce88812fSHu Tao smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 270c0907c9eSPaolo Bonzini mch->smm_enabled); 271c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 272c0907c9eSPaolo Bonzini } 273c0907c9eSPaolo Bonzini 274c0907c9eSPaolo Bonzini static void mch_set_smm(int smm, void *arg) 275c0907c9eSPaolo Bonzini { 276c0907c9eSPaolo Bonzini MCHPCIState *mch = arg; 277ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 278c0907c9eSPaolo Bonzini 279c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 280ce88812fSHu Tao smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 281c0907c9eSPaolo Bonzini &mch->smram_region); 282c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 283c0907c9eSPaolo Bonzini } 284c0907c9eSPaolo Bonzini 285c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 286c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 287c0907c9eSPaolo Bonzini { 288c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 289c0907c9eSPaolo Bonzini 290c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 291c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 292c0907c9eSPaolo Bonzini 293c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 294c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 295c0907c9eSPaolo Bonzini mch_update_pam(mch); 296c0907c9eSPaolo Bonzini } 297c0907c9eSPaolo Bonzini 298c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 299c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 300c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 301c0907c9eSPaolo Bonzini } 302c0907c9eSPaolo Bonzini 303c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 304c0907c9eSPaolo Bonzini MCH_HOST_BRDIGE_SMRAM_SIZE)) { 305c0907c9eSPaolo Bonzini mch_update_smram(mch); 306c0907c9eSPaolo Bonzini } 307c0907c9eSPaolo Bonzini } 308c0907c9eSPaolo Bonzini 309c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 310c0907c9eSPaolo Bonzini { 311c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 312c0907c9eSPaolo Bonzini mch_update_pam(mch); 313c0907c9eSPaolo Bonzini mch_update_smram(mch); 314c0907c9eSPaolo Bonzini } 315c0907c9eSPaolo Bonzini 316c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 317c0907c9eSPaolo Bonzini { 318c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 319c0907c9eSPaolo Bonzini mch_update(mch); 320c0907c9eSPaolo Bonzini return 0; 321c0907c9eSPaolo Bonzini } 322c0907c9eSPaolo Bonzini 323c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 324c0907c9eSPaolo Bonzini .name = "mch", 325c0907c9eSPaolo Bonzini .version_id = 1, 326c0907c9eSPaolo Bonzini .minimum_version_id = 1, 327c0907c9eSPaolo Bonzini .minimum_version_id_old = 1, 328c0907c9eSPaolo Bonzini .post_load = mch_post_load, 329c0907c9eSPaolo Bonzini .fields = (VMStateField []) { 330ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 331c0907c9eSPaolo Bonzini VMSTATE_UINT8(smm_enabled, MCHPCIState), 332c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 333c0907c9eSPaolo Bonzini } 334c0907c9eSPaolo Bonzini }; 335c0907c9eSPaolo Bonzini 336c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 337c0907c9eSPaolo Bonzini { 338c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 339c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 340c0907c9eSPaolo Bonzini 341c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 342c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 343c0907c9eSPaolo Bonzini 344c0907c9eSPaolo Bonzini d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 345c0907c9eSPaolo Bonzini 346c0907c9eSPaolo Bonzini mch_update(mch); 347c0907c9eSPaolo Bonzini } 348c0907c9eSPaolo Bonzini 349c0907c9eSPaolo Bonzini static int mch_init(PCIDevice *d) 350c0907c9eSPaolo Bonzini { 351c0907c9eSPaolo Bonzini int i; 352c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 3531466cef3SMichael S. Tsirkin uint64_t pci_hole64_size; 354c0907c9eSPaolo Bonzini 355c0907c9eSPaolo Bonzini /* setup pci memory regions */ 35640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 357c0907c9eSPaolo Bonzini mch->pci_address_space, 358c0907c9eSPaolo Bonzini mch->below_4g_mem_size, 359c0907c9eSPaolo Bonzini 0x100000000ULL - mch->below_4g_mem_size); 360c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 361c0907c9eSPaolo Bonzini &mch->pci_hole); 36239848901SIgor Mammedov 3631466cef3SMichael S. Tsirkin pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size); 36439848901SIgor Mammedov pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, 3651466cef3SMichael S. Tsirkin pci_hole64_size); 36640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 367c0907c9eSPaolo Bonzini mch->pci_address_space, 36839848901SIgor Mammedov mch->pci_info.w64.begin, 3691466cef3SMichael S. Tsirkin pci_hole64_size); 3701466cef3SMichael S. Tsirkin if (pci_hole64_size) { 371c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, 37239848901SIgor Mammedov mch->pci_info.w64.begin, 373c0907c9eSPaolo Bonzini &mch->pci_hole_64bit); 374c0907c9eSPaolo Bonzini } 375c0907c9eSPaolo Bonzini /* smram */ 376c0907c9eSPaolo Bonzini cpu_smm_register(&mch_set_smm, mch); 37740c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 378c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 379c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 380c0907c9eSPaolo Bonzini &mch->smram_region, 1); 381c0907c9eSPaolo Bonzini memory_region_set_enabled(&mch->smram_region, false); 3823cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 383c0907c9eSPaolo Bonzini &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 384c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 3853cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 386c0907c9eSPaolo Bonzini &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 387c0907c9eSPaolo Bonzini PAM_EXPAN_SIZE); 388c0907c9eSPaolo Bonzini } 389c0907c9eSPaolo Bonzini return 0; 390c0907c9eSPaolo Bonzini } 391c0907c9eSPaolo Bonzini 392c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 393c0907c9eSPaolo Bonzini { 394c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 395c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 396c0907c9eSPaolo Bonzini 397c0907c9eSPaolo Bonzini k->init = mch_init; 398c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 399c0907c9eSPaolo Bonzini dc->reset = mch_reset; 400125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 401c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 402c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 403c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 404c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 405c0907c9eSPaolo Bonzini k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 406c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 407c0907c9eSPaolo Bonzini } 408c0907c9eSPaolo Bonzini 409c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 410c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 411c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 412c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 413c0907c9eSPaolo Bonzini .class_init = mch_class_init, 414c0907c9eSPaolo Bonzini }; 415c0907c9eSPaolo Bonzini 416c0907c9eSPaolo Bonzini static void q35_register(void) 417c0907c9eSPaolo Bonzini { 418c0907c9eSPaolo Bonzini type_register_static(&mch_info); 419c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 420c0907c9eSPaolo Bonzini } 421c0907c9eSPaolo Bonzini 422c0907c9eSPaolo Bonzini type_init(q35_register); 423