1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10c0907c9eSPaolo Bonzini * This is based on piix_pci.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30c0907c9eSPaolo Bonzini #include "hw/hw.h" 31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 32c0907c9eSPaolo Bonzini 33c0907c9eSPaolo Bonzini /**************************************************************************** 34c0907c9eSPaolo Bonzini * Q35 host 35c0907c9eSPaolo Bonzini */ 36c0907c9eSPaolo Bonzini 37c0907c9eSPaolo Bonzini static int q35_host_init(SysBusDevice *dev) 38c0907c9eSPaolo Bonzini { 39*ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 40*ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 41c0907c9eSPaolo Bonzini 4240c5dce9SPaolo Bonzini memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci, 43c0907c9eSPaolo Bonzini "pci-conf-idx", 4); 44c0907c9eSPaolo Bonzini sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 45*ce88812fSHu Tao sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46c0907c9eSPaolo Bonzini 4740c5dce9SPaolo Bonzini memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci, 48c0907c9eSPaolo Bonzini "pci-conf-data", 4); 49c0907c9eSPaolo Bonzini sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50*ce88812fSHu Tao sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51c0907c9eSPaolo Bonzini 52*ce88812fSHu Tao if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 53c0907c9eSPaolo Bonzini return -1; 54c0907c9eSPaolo Bonzini } 55*ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 56c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 57c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 58*ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 59c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 60c0907c9eSPaolo Bonzini 61c0907c9eSPaolo Bonzini return 0; 62c0907c9eSPaolo Bonzini } 63c0907c9eSPaolo Bonzini 64568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 65568f0690SDavid Gibson PCIBus *rootbus) 66568f0690SDavid Gibson { 67568f0690SDavid Gibson /* For backwards compat with old device paths */ 68568f0690SDavid Gibson return "0000"; 69568f0690SDavid Gibson } 70568f0690SDavid Gibson 71c0907c9eSPaolo Bonzini static Property mch_props[] = { 72*ce88812fSHu Tao DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 73c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 74c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 75c0907c9eSPaolo Bonzini }; 76c0907c9eSPaolo Bonzini 77c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 78c0907c9eSPaolo Bonzini { 79c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 80c0907c9eSPaolo Bonzini SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 81568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 82c0907c9eSPaolo Bonzini 83568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 84c0907c9eSPaolo Bonzini k->init = q35_host_init; 85c0907c9eSPaolo Bonzini dc->props = mch_props; 8668c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 87c0907c9eSPaolo Bonzini } 88c0907c9eSPaolo Bonzini 89c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 90c0907c9eSPaolo Bonzini { 91c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 92c0907c9eSPaolo Bonzini 93c0907c9eSPaolo Bonzini object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 94c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 95c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 96c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 97c0907c9eSPaolo Bonzini } 98c0907c9eSPaolo Bonzini 99c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 100c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 101c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 102c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 103c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 104c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 105c0907c9eSPaolo Bonzini }; 106c0907c9eSPaolo Bonzini 107c0907c9eSPaolo Bonzini /**************************************************************************** 108c0907c9eSPaolo Bonzini * MCH D0:F0 109c0907c9eSPaolo Bonzini */ 110c0907c9eSPaolo Bonzini 111c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 112c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 113c0907c9eSPaolo Bonzini { 114*ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 115*ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 116*ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 117c0907c9eSPaolo Bonzini 118c0907c9eSPaolo Bonzini uint64_t pciexbar; 119c0907c9eSPaolo Bonzini int enable; 120c0907c9eSPaolo Bonzini uint64_t addr; 121c0907c9eSPaolo Bonzini uint64_t addr_mask; 122c0907c9eSPaolo Bonzini uint32_t length; 123c0907c9eSPaolo Bonzini 124c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 125c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 126c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 127c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 128c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 129c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 130c0907c9eSPaolo Bonzini break; 131c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 132c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 133c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 134c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 135c0907c9eSPaolo Bonzini break; 136c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 137c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 138c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 139c0907c9eSPaolo Bonzini break; 140c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 141c0907c9eSPaolo Bonzini default: 142c0907c9eSPaolo Bonzini enable = 0; 143c0907c9eSPaolo Bonzini length = 0; 144c0907c9eSPaolo Bonzini abort(); 145c0907c9eSPaolo Bonzini break; 146c0907c9eSPaolo Bonzini } 147c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 148*ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 149c0907c9eSPaolo Bonzini } 150c0907c9eSPaolo Bonzini 151c0907c9eSPaolo Bonzini /* PAM */ 152c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 153c0907c9eSPaolo Bonzini { 154*ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 155c0907c9eSPaolo Bonzini int i; 156c0907c9eSPaolo Bonzini 157c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 158c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 159c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 160*ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 161c0907c9eSPaolo Bonzini } 162c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 163c0907c9eSPaolo Bonzini } 164c0907c9eSPaolo Bonzini 165c0907c9eSPaolo Bonzini /* SMRAM */ 166c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 167c0907c9eSPaolo Bonzini { 168*ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 169*ce88812fSHu Tao 170c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 171*ce88812fSHu Tao smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 172c0907c9eSPaolo Bonzini mch->smm_enabled); 173c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 174c0907c9eSPaolo Bonzini } 175c0907c9eSPaolo Bonzini 176c0907c9eSPaolo Bonzini static void mch_set_smm(int smm, void *arg) 177c0907c9eSPaolo Bonzini { 178c0907c9eSPaolo Bonzini MCHPCIState *mch = arg; 179*ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 180c0907c9eSPaolo Bonzini 181c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 182*ce88812fSHu Tao smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 183c0907c9eSPaolo Bonzini &mch->smram_region); 184c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 185c0907c9eSPaolo Bonzini } 186c0907c9eSPaolo Bonzini 187c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 188c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 189c0907c9eSPaolo Bonzini { 190c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 191c0907c9eSPaolo Bonzini 192c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 193c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 194c0907c9eSPaolo Bonzini 195c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 196c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 197c0907c9eSPaolo Bonzini mch_update_pam(mch); 198c0907c9eSPaolo Bonzini } 199c0907c9eSPaolo Bonzini 200c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 201c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 202c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 203c0907c9eSPaolo Bonzini } 204c0907c9eSPaolo Bonzini 205c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 206c0907c9eSPaolo Bonzini MCH_HOST_BRDIGE_SMRAM_SIZE)) { 207c0907c9eSPaolo Bonzini mch_update_smram(mch); 208c0907c9eSPaolo Bonzini } 209c0907c9eSPaolo Bonzini } 210c0907c9eSPaolo Bonzini 211c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 212c0907c9eSPaolo Bonzini { 213c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 214c0907c9eSPaolo Bonzini mch_update_pam(mch); 215c0907c9eSPaolo Bonzini mch_update_smram(mch); 216c0907c9eSPaolo Bonzini } 217c0907c9eSPaolo Bonzini 218c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 219c0907c9eSPaolo Bonzini { 220c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 221c0907c9eSPaolo Bonzini mch_update(mch); 222c0907c9eSPaolo Bonzini return 0; 223c0907c9eSPaolo Bonzini } 224c0907c9eSPaolo Bonzini 225c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 226c0907c9eSPaolo Bonzini .name = "mch", 227c0907c9eSPaolo Bonzini .version_id = 1, 228c0907c9eSPaolo Bonzini .minimum_version_id = 1, 229c0907c9eSPaolo Bonzini .minimum_version_id_old = 1, 230c0907c9eSPaolo Bonzini .post_load = mch_post_load, 231c0907c9eSPaolo Bonzini .fields = (VMStateField []) { 232*ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 233c0907c9eSPaolo Bonzini VMSTATE_UINT8(smm_enabled, MCHPCIState), 234c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 235c0907c9eSPaolo Bonzini } 236c0907c9eSPaolo Bonzini }; 237c0907c9eSPaolo Bonzini 238c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 239c0907c9eSPaolo Bonzini { 240c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 241c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 242c0907c9eSPaolo Bonzini 243c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 244c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 245c0907c9eSPaolo Bonzini 246c0907c9eSPaolo Bonzini d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 247c0907c9eSPaolo Bonzini 248c0907c9eSPaolo Bonzini mch_update(mch); 249c0907c9eSPaolo Bonzini } 250c0907c9eSPaolo Bonzini 251c0907c9eSPaolo Bonzini static int mch_init(PCIDevice *d) 252c0907c9eSPaolo Bonzini { 253c0907c9eSPaolo Bonzini int i; 254c0907c9eSPaolo Bonzini hwaddr pci_hole64_size; 255c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 256c0907c9eSPaolo Bonzini 2573459a625SMichael S. Tsirkin /* Leave enough space for the biggest MCFG BAR */ 2583459a625SMichael S. Tsirkin /* TODO: this matches current bios behaviour, but 2593459a625SMichael S. Tsirkin * it's not a power of two, which means an MTRR 2603459a625SMichael S. Tsirkin * can't cover it exactly. 2613459a625SMichael S. Tsirkin */ 2623459a625SMichael S. Tsirkin mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 2633459a625SMichael S. Tsirkin MCH_HOST_BRIDGE_PCIEXBAR_MAX; 2643459a625SMichael S. Tsirkin 265c0907c9eSPaolo Bonzini /* setup pci memory regions */ 26640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 267c0907c9eSPaolo Bonzini mch->pci_address_space, 268c0907c9eSPaolo Bonzini mch->below_4g_mem_size, 269c0907c9eSPaolo Bonzini 0x100000000ULL - mch->below_4g_mem_size); 270c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 271c0907c9eSPaolo Bonzini &mch->pci_hole); 272c0907c9eSPaolo Bonzini pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : 273c0907c9eSPaolo Bonzini ((uint64_t)1 << 62)); 27440c5dce9SPaolo Bonzini memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 275c0907c9eSPaolo Bonzini mch->pci_address_space, 276c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 277c0907c9eSPaolo Bonzini pci_hole64_size); 278c0907c9eSPaolo Bonzini if (pci_hole64_size) { 279c0907c9eSPaolo Bonzini memory_region_add_subregion(mch->system_memory, 280c0907c9eSPaolo Bonzini 0x100000000ULL + mch->above_4g_mem_size, 281c0907c9eSPaolo Bonzini &mch->pci_hole_64bit); 282c0907c9eSPaolo Bonzini } 283c0907c9eSPaolo Bonzini /* smram */ 284c0907c9eSPaolo Bonzini cpu_smm_register(&mch_set_smm, mch); 28540c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 286c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 287c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 288c0907c9eSPaolo Bonzini &mch->smram_region, 1); 289c0907c9eSPaolo Bonzini memory_region_set_enabled(&mch->smram_region, false); 2903cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 291c0907c9eSPaolo Bonzini &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 292c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 2933cd2cf43SPaolo Bonzini init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 294c0907c9eSPaolo Bonzini &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 295c0907c9eSPaolo Bonzini PAM_EXPAN_SIZE); 296c0907c9eSPaolo Bonzini } 297c0907c9eSPaolo Bonzini return 0; 298c0907c9eSPaolo Bonzini } 299c0907c9eSPaolo Bonzini 300c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 301c0907c9eSPaolo Bonzini { 302c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 303c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 304c0907c9eSPaolo Bonzini 305c0907c9eSPaolo Bonzini k->init = mch_init; 306c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 307c0907c9eSPaolo Bonzini dc->reset = mch_reset; 308c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 309c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 310c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 311c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 312c0907c9eSPaolo Bonzini k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 313c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 314c0907c9eSPaolo Bonzini } 315c0907c9eSPaolo Bonzini 316c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 317c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 318c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 319c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 320c0907c9eSPaolo Bonzini .class_init = mch_class_init, 321c0907c9eSPaolo Bonzini }; 322c0907c9eSPaolo Bonzini 323c0907c9eSPaolo Bonzini static void q35_register(void) 324c0907c9eSPaolo Bonzini { 325c0907c9eSPaolo Bonzini type_register_static(&mch_info); 326c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 327c0907c9eSPaolo Bonzini } 328c0907c9eSPaolo Bonzini 329c0907c9eSPaolo Bonzini type_init(q35_register); 330