1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 3271adf91aSPhilippe Mathieu-Daudé #include "hw/i386/pc.h" 33c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 34a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 35d6454270SMarkus Armbruster #include "migration/vmstate.h" 36da34e65cSMarkus Armbruster #include "qapi/error.h" 3739848901SIgor Mammedov #include "qapi/visitor.h" 380b8fa32fSMarkus Armbruster #include "qemu/module.h" 39c0907c9eSPaolo Bonzini 40c0907c9eSPaolo Bonzini /**************************************************************************** 41c0907c9eSPaolo Bonzini * Q35 host 42c0907c9eSPaolo Bonzini */ 43c0907c9eSPaolo Bonzini 449fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 459fa99d25SMarcel Apfelbaum 4662d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 47c0907c9eSPaolo Bonzini { 48ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 49ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 5062d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 51c0907c9eSPaolo Bonzini 5262d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5362d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 54c0907c9eSPaolo Bonzini 5562d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5662d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 57c0907c9eSPaolo Bonzini 58a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 59a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 60a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 61a8de0115SPeng Hao 621115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 631115ff6dSDavid Gibson s->mch.pci_address_space, 641115ff6dSDavid Gibson s->mch.address_space_io, 65c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 66621d983aSMarcel Apfelbaum PC_MACHINE(qdev_get_machine())->bus = pci->bus; 67ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 68c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 69c0907c9eSPaolo Bonzini } 70c0907c9eSPaolo Bonzini 71568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 72568f0690SDavid Gibson PCIBus *rootbus) 73568f0690SDavid Gibson { 7404c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 7504c7d8b8SCole Robinson 76568f0690SDavid Gibson /* For backwards compat with old device paths */ 7704c7d8b8SCole Robinson if (s->mch.short_root_bus) { 78568f0690SDavid Gibson return "0000"; 79568f0690SDavid Gibson } 8004c7d8b8SCole Robinson return "0000:00"; 8104c7d8b8SCole Robinson } 82568f0690SDavid Gibson 8339848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 84d7bce999SEric Blake const char *name, void *opaque, 8539848901SIgor Mammedov Error **errp) 8639848901SIgor Mammedov { 8739848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 88a0efbf16SMarkus Armbruster uint64_t val64; 89a0efbf16SMarkus Armbruster uint32_t value; 9039848901SIgor Mammedov 91a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 92a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 93a0efbf16SMarkus Armbruster value = val64; 94a0efbf16SMarkus Armbruster assert(value == val64); 9551e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9639848901SIgor Mammedov } 9739848901SIgor Mammedov 9839848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 99d7bce999SEric Blake const char *name, void *opaque, 10039848901SIgor Mammedov Error **errp) 10139848901SIgor Mammedov { 10239848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 103a0efbf16SMarkus Armbruster uint64_t val64; 104a0efbf16SMarkus Armbruster uint32_t value; 10539848901SIgor Mammedov 106a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 107a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 108a0efbf16SMarkus Armbruster value = val64; 109a0efbf16SMarkus Armbruster assert(value == val64); 11051e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 11139848901SIgor Mammedov } 11239848901SIgor Mammedov 1139fa99d25SMarcel Apfelbaum /* 1149fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1159fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1169fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1179fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1189fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1199fa99d25SMarcel Apfelbaum */ 120ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 12139848901SIgor Mammedov { 1228b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1239fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1248b42d730SMichael S. Tsirkin Range w64; 125a0efbf16SMarkus Armbruster uint64_t value; 12639848901SIgor Mammedov 1278b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 128a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1299fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1309fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1319fa99d25SMarcel Apfelbaum } 132ccef5b1fSLaszlo Ersek return value; 133ccef5b1fSLaszlo Ersek } 134ccef5b1fSLaszlo Ersek 135ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 136ccef5b1fSLaszlo Ersek const char *name, void *opaque, 137ccef5b1fSLaszlo Ersek Error **errp) 138ccef5b1fSLaszlo Ersek { 139ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 140ccef5b1fSLaszlo Ersek 141ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 14239848901SIgor Mammedov } 14339848901SIgor Mammedov 1449fa99d25SMarcel Apfelbaum /* 1459fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1469fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1479fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1489fa99d25SMarcel Apfelbaum * that can be configured by the user. 1499fa99d25SMarcel Apfelbaum */ 15039848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 151d7bce999SEric Blake const char *name, void *opaque, 15239848901SIgor Mammedov Error **errp) 15339848901SIgor Mammedov { 1548b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1559fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 156ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1578b42d730SMichael S. Tsirkin Range w64; 1589fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 15939848901SIgor Mammedov 1608b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 161a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1629fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1639fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1649fa99d25SMarcel Apfelbaum value = hole64_end; 1659fa99d25SMarcel Apfelbaum } 166a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16739848901SIgor Mammedov } 16839848901SIgor Mammedov 1699fa99d25SMarcel Apfelbaum /* 1709fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1719fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1729fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1739fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1749fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1759fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1769fa99d25SMarcel Apfelbaum */ 1772f295167SLaszlo Ersek static Property q35_host_props[] = { 17887f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 179c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 18039848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1819fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 18204c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 183401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 184401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 185401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 186401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1879fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 188c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 189c0907c9eSPaolo Bonzini }; 190c0907c9eSPaolo Bonzini 191c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 192c0907c9eSPaolo Bonzini { 193c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 194568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 195c0907c9eSPaolo Bonzini 196568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 19762d92e43SHu Tao dc->realize = q35_host_realize; 1984f67d30bSMarc-André Lureau device_class_set_props(dc, q35_host_props); 199bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 200e90f2a8cSEduardo Habkost dc->user_creatable = false; 201125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 20268c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 203c0907c9eSPaolo Bonzini } 204c0907c9eSPaolo Bonzini 205c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 206c0907c9eSPaolo Bonzini { 207c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 20862d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 20964a7b8deSFelipe Franciosi PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); 21062d92e43SHu Tao 21162d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 21262d92e43SHu Tao "pci-conf-idx", 4); 21362d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 21462d92e43SHu Tao "pci-conf-data", 4); 215c0907c9eSPaolo Bonzini 216aff39be0SThomas Huth object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 217aff39be0SThomas Huth TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 218446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 219c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2209fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2219fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2229fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2231e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 22439848901SIgor Mammedov q35_host_get_pci_hole_start, 225*d2623129SMarkus Armbruster NULL, NULL, NULL); 22639848901SIgor Mammedov 2271e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 22839848901SIgor Mammedov q35_host_get_pci_hole_end, 229*d2623129SMarkus Armbruster NULL, NULL, NULL); 23039848901SIgor Mammedov 2311e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 23239848901SIgor Mammedov q35_host_get_pci_hole64_start, 233*d2623129SMarkus Armbruster NULL, NULL, NULL); 23439848901SIgor Mammedov 2351e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 23639848901SIgor Mammedov q35_host_get_pci_hole64_end, 237*d2623129SMarkus Armbruster NULL, NULL, NULL); 23839848901SIgor Mammedov 23964a7b8deSFelipe Franciosi object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, 240*d2623129SMarkus Armbruster &pehb->size, OBJ_PROP_FLAG_READ); 241cbcaf79eSMichael S. Tsirkin 242401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 243401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 244*d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 245401f2f3eSEfimov Vasily 246401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 247401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 248*d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 249401f2f3eSEfimov Vasily 250401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 251401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 252*d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 253401f2f3eSEfimov Vasily 254401f2f3eSEfimov Vasily object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 255401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 256*d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 257c0907c9eSPaolo Bonzini } 258c0907c9eSPaolo Bonzini 259c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 260c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 261c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 262c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 263c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 264c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 265c0907c9eSPaolo Bonzini }; 266c0907c9eSPaolo Bonzini 267c0907c9eSPaolo Bonzini /**************************************************************************** 268c0907c9eSPaolo Bonzini * MCH D0:F0 269c0907c9eSPaolo Bonzini */ 270c0907c9eSPaolo Bonzini 271f404220eSIgor Mammedov static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 272bafc90bdSGerd Hoffmann { 273bafc90bdSGerd Hoffmann return 0xffffffff; 274bafc90bdSGerd Hoffmann } 275bafc90bdSGerd Hoffmann 276f404220eSIgor Mammedov static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 277bafc90bdSGerd Hoffmann unsigned width) 278bafc90bdSGerd Hoffmann { 279bafc90bdSGerd Hoffmann /* nothing */ 280bafc90bdSGerd Hoffmann } 281bafc90bdSGerd Hoffmann 282f404220eSIgor Mammedov static const MemoryRegionOps blackhole_ops = { 283f404220eSIgor Mammedov .read = blackhole_read, 284f404220eSIgor Mammedov .write = blackhole_write, 285bafc90bdSGerd Hoffmann .endianness = DEVICE_NATIVE_ENDIAN, 286bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 287bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 288bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 289bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 290bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 291bafc90bdSGerd Hoffmann }; 292bafc90bdSGerd Hoffmann 293c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 294c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 295c0907c9eSPaolo Bonzini { 296ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 297ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 298ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 299c0907c9eSPaolo Bonzini 300c0907c9eSPaolo Bonzini uint64_t pciexbar; 301c0907c9eSPaolo Bonzini int enable; 302c0907c9eSPaolo Bonzini uint64_t addr; 303c0907c9eSPaolo Bonzini uint64_t addr_mask; 304c0907c9eSPaolo Bonzini uint32_t length; 305c0907c9eSPaolo Bonzini 306c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 307c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 308c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 309c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 310c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 311c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 312c0907c9eSPaolo Bonzini break; 313c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 314c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 315c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 316c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 317c0907c9eSPaolo Bonzini break; 318c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 319c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 320c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 321c0907c9eSPaolo Bonzini break; 322c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 323c0907c9eSPaolo Bonzini default: 324c0907c9eSPaolo Bonzini abort(); 325c0907c9eSPaolo Bonzini } 326c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 327ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 328c0907c9eSPaolo Bonzini } 329c0907c9eSPaolo Bonzini 330c0907c9eSPaolo Bonzini /* PAM */ 331c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 332c0907c9eSPaolo Bonzini { 333ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 334c0907c9eSPaolo Bonzini int i; 335c0907c9eSPaolo Bonzini 336c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 337c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 338c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 33966175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 340c0907c9eSPaolo Bonzini } 341c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 342c0907c9eSPaolo Bonzini } 343c0907c9eSPaolo Bonzini 344c0907c9eSPaolo Bonzini /* SMRAM */ 345c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 346c0907c9eSPaolo Bonzini { 347ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 34864130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 349bafc90bdSGerd Hoffmann uint32_t tseg_size; 350ce88812fSHu Tao 35168c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 35268c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 35368c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 35468c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 35568c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 35668c77acfSGerd Hoffmann } 35768c77acfSGerd Hoffmann 358c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 35964130fa4SPaolo Bonzini 36064130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 36164130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 36264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 36364130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 36464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 36564130fa4SPaolo Bonzini } else { 36664130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 36764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 36864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 36964130fa4SPaolo Bonzini } 37064130fa4SPaolo Bonzini 37164130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 37264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 37364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 37464130fa4SPaolo Bonzini } else { 37564130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 37664130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 37764130fa4SPaolo Bonzini } 37864130fa4SPaolo Bonzini 379bafc90bdSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 380bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 381bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 382bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 383bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 384bafc90bdSGerd Hoffmann break; 385bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 386bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 387bafc90bdSGerd Hoffmann break; 388bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 389bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 390bafc90bdSGerd Hoffmann break; 391bafc90bdSGerd Hoffmann default: 3922f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 393bafc90bdSGerd Hoffmann break; 394bafc90bdSGerd Hoffmann } 395bafc90bdSGerd Hoffmann } else { 396bafc90bdSGerd Hoffmann tseg_size = 0; 397bafc90bdSGerd Hoffmann } 398bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 399bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 400bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 401bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 402bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 403bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 404bafc90bdSGerd Hoffmann 405bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 406bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 407bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 408bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 409bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 410bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 411bafc90bdSGerd Hoffmann 412c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 413c0907c9eSPaolo Bonzini } 414c0907c9eSPaolo Bonzini 4152f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4162f295167SLaszlo Ersek { 4172f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4182f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4192f295167SLaszlo Ersek 4202f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4212f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4222f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4232f295167SLaszlo Ersek } 4242f295167SLaszlo Ersek } 4252f295167SLaszlo Ersek 426f404220eSIgor Mammedov static void mch_update_smbase_smram(MCHPCIState *mch) 427f404220eSIgor Mammedov { 428f404220eSIgor Mammedov PCIDevice *pd = PCI_DEVICE(mch); 429f404220eSIgor Mammedov uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 430f404220eSIgor Mammedov bool lck; 431f404220eSIgor Mammedov 432f404220eSIgor Mammedov if (!mch->has_smram_at_smbase) { 433f404220eSIgor Mammedov return; 434f404220eSIgor Mammedov } 435f404220eSIgor Mammedov 436f404220eSIgor Mammedov if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 437f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 438f404220eSIgor Mammedov MCH_HOST_BRIDGE_F_SMBASE_LCK; 439f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 440f404220eSIgor Mammedov return; 441f404220eSIgor Mammedov } 442f404220eSIgor Mammedov 443f404220eSIgor Mammedov /* 444f404220eSIgor Mammedov * default/reset state, discard written value 445f404220eSIgor Mammedov * which will disable SMRAM balackhole at SMBASE 446f404220eSIgor Mammedov */ 447f404220eSIgor Mammedov if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 448f404220eSIgor Mammedov *reg = 0x00; 449f404220eSIgor Mammedov } 450f404220eSIgor Mammedov 451f404220eSIgor Mammedov memory_region_transaction_begin(); 452f404220eSIgor Mammedov if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 453f404220eSIgor Mammedov /* disable all writes */ 454f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 455f404220eSIgor Mammedov ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 456f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 457f404220eSIgor Mammedov lck = true; 458f404220eSIgor Mammedov } else { 459f404220eSIgor Mammedov lck = false; 460f404220eSIgor Mammedov } 461f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, lck); 462f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, lck); 463f404220eSIgor Mammedov memory_region_transaction_commit(); 464f404220eSIgor Mammedov } 465f404220eSIgor Mammedov 466c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 467c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 468c0907c9eSPaolo Bonzini { 469c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 470c0907c9eSPaolo Bonzini 471c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 472c0907c9eSPaolo Bonzini 473c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 474c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 475c0907c9eSPaolo Bonzini mch_update_pam(mch); 476c0907c9eSPaolo Bonzini } 477c0907c9eSPaolo Bonzini 478c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 479c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 480c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 481c0907c9eSPaolo Bonzini } 482c0907c9eSPaolo Bonzini 483263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 484263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 485c0907c9eSPaolo Bonzini mch_update_smram(mch); 486c0907c9eSPaolo Bonzini } 4872f295167SLaszlo Ersek 4882f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4892f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4902f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4912f295167SLaszlo Ersek } 492f404220eSIgor Mammedov 493f404220eSIgor Mammedov if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 494f404220eSIgor Mammedov mch_update_smbase_smram(mch); 495f404220eSIgor Mammedov } 496c0907c9eSPaolo Bonzini } 497c0907c9eSPaolo Bonzini 498c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 499c0907c9eSPaolo Bonzini { 500c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 501c0907c9eSPaolo Bonzini mch_update_pam(mch); 502c0907c9eSPaolo Bonzini mch_update_smram(mch); 5032f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 504f404220eSIgor Mammedov mch_update_smbase_smram(mch); 5054a441836SGerd Hoffmann 5064a441836SGerd Hoffmann /* 5074a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 5084a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 5094a441836SGerd Hoffmann */ 5104a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 5114a441836SGerd Hoffmann mch->below_4g_mem_size, 5124a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 513c0907c9eSPaolo Bonzini } 514c0907c9eSPaolo Bonzini 515c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 516c0907c9eSPaolo Bonzini { 517c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 518c0907c9eSPaolo Bonzini mch_update(mch); 519c0907c9eSPaolo Bonzini return 0; 520c0907c9eSPaolo Bonzini } 521c0907c9eSPaolo Bonzini 522c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 523c0907c9eSPaolo Bonzini .name = "mch", 524c0907c9eSPaolo Bonzini .version_id = 1, 525c0907c9eSPaolo Bonzini .minimum_version_id = 1, 526c0907c9eSPaolo Bonzini .post_load = mch_post_load, 527c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 528ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 529f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 530f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 531f809c605SPaolo Bonzini */ 532f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 533c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 534c0907c9eSPaolo Bonzini } 535c0907c9eSPaolo Bonzini }; 536c0907c9eSPaolo Bonzini 537c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 538c0907c9eSPaolo Bonzini { 539c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 540c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 541c0907c9eSPaolo Bonzini 542c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 543c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 544c0907c9eSPaolo Bonzini 545263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 54677447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 547b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 548b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 549c0907c9eSPaolo Bonzini 5502f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5512f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5522f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5532f295167SLaszlo Ersek } 5542f295167SLaszlo Ersek 555f404220eSIgor Mammedov d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 556f404220eSIgor Mammedov d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 557f404220eSIgor Mammedov 558c0907c9eSPaolo Bonzini mch_update(mch); 559c0907c9eSPaolo Bonzini } 560c0907c9eSPaolo Bonzini 5619af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 562c0907c9eSPaolo Bonzini { 563c0907c9eSPaolo Bonzini int i; 564c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 565c0907c9eSPaolo Bonzini 5662f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5672f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5682f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5692f295167SLaszlo Ersek return; 5702f295167SLaszlo Ersek } 5712f295167SLaszlo Ersek 57283d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 57383d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 57483d08f26SMichael S. Tsirkin mch->pci_address_space); 57539848901SIgor Mammedov 576fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 57740c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 578dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 579dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 580dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 581c0907c9eSPaolo Bonzini &mch->smram_region, 1); 582fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 583fe6567d5SPaolo Bonzini 58464130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 585dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 586dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 58764130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 58864130fa4SPaolo Bonzini &mch->open_high_smram, 1); 58964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 59064130fa4SPaolo Bonzini 591fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 592fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 593fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 594fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 595dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 596dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 597fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 598dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 599dda53ee9SZihan Yang &mch->low_smram); 60064130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 601dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 602dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 60364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 60464130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 605bafc90bdSGerd Hoffmann 606bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 607f404220eSIgor Mammedov &blackhole_ops, NULL, 608bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 609bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 610bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 611bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 612bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 613bafc90bdSGerd Hoffmann 614bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 615bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 616bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 617bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 618bafc90bdSGerd Hoffmann &mch->tseg_window); 619f404220eSIgor Mammedov 620f404220eSIgor Mammedov /* 621f404220eSIgor Mammedov * This is not what hardware does, so it's QEMU specific hack. 622f404220eSIgor Mammedov * See commit message for details. 623f404220eSIgor Mammedov */ 624f404220eSIgor Mammedov memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 625f404220eSIgor Mammedov NULL, "smbase-blackhole", 626f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 627f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, false); 628f404220eSIgor Mammedov memory_region_add_subregion_overlap(mch->system_memory, 629f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 630f404220eSIgor Mammedov &mch->smbase_blackhole, 1); 631f404220eSIgor Mammedov 632f404220eSIgor Mammedov memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 633f404220eSIgor Mammedov "smbase-window", mch->ram_memory, 634f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 635f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 636f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, false); 637f404220eSIgor Mammedov memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 638f404220eSIgor Mammedov &mch->smbase_window); 639f404220eSIgor Mammedov 640fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 641*d2623129SMarkus Armbruster OBJECT(&mch->smram)); 642fe6567d5SPaolo Bonzini 643ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 644ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 645ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 646c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 647ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 648ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 649ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 650c0907c9eSPaolo Bonzini } 651c0907c9eSPaolo Bonzini } 652c0907c9eSPaolo Bonzini 6536f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 6546f1426abSMichael S. Tsirkin { 6556f1426abSMichael S. Tsirkin bool ambiguous; 6566f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 6576f1426abSMichael S. Tsirkin if (!o) { 6586f1426abSMichael S. Tsirkin return 0; 6596f1426abSMichael S. Tsirkin } 6606f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 6616f1426abSMichael S. Tsirkin } 6626f1426abSMichael S. Tsirkin 6632f295167SLaszlo Ersek static Property mch_props[] = { 6642f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6652f295167SLaszlo Ersek 16), 666f404220eSIgor Mammedov DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 6672f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6682f295167SLaszlo Ersek }; 6692f295167SLaszlo Ersek 670c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 671c0907c9eSPaolo Bonzini { 672c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 673c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 674c0907c9eSPaolo Bonzini 6759af21dbeSMarkus Armbruster k->realize = mch_realize; 676c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 677c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6784f67d30bSMarc-André Lureau device_class_set_props(dc, mch_props); 679125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 680c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 681c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 682c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 683d4715481SDaniel P. Berrangé /* 684d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 685d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 686d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 687d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 688d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 689d4715481SDaniel P. Berrangé * chipset. 690d4715481SDaniel P. Berrangé */ 691d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 692451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 693c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 69408c58f92SMarkus Armbruster /* 69508c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 69608c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 69708c58f92SMarkus Armbruster */ 698e90f2a8cSEduardo Habkost dc->user_creatable = false; 699c0907c9eSPaolo Bonzini } 700c0907c9eSPaolo Bonzini 701c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 702c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 703c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 704c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 705c0907c9eSPaolo Bonzini .class_init = mch_class_init, 706fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 707fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 708fd3b02c8SEduardo Habkost { }, 709fd3b02c8SEduardo Habkost }, 710c0907c9eSPaolo Bonzini }; 711c0907c9eSPaolo Bonzini 712c0907c9eSPaolo Bonzini static void q35_register(void) 713c0907c9eSPaolo Bonzini { 714c0907c9eSPaolo Bonzini type_register_static(&mch_info); 715c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 716c0907c9eSPaolo Bonzini } 717c0907c9eSPaolo Bonzini 718c0907c9eSPaolo Bonzini type_init(q35_register); 719