1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 300b8fa32fSMarkus Armbruster 31b6a0aa05SPeter Maydell #include "qemu/osdep.h" 329b0ca75eSPhilippe Mathieu-Daudé #include "qemu/log.h" 3371adf91aSPhilippe Mathieu-Daudé #include "hw/i386/pc.h" 34c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 35a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 36d6454270SMarkus Armbruster #include "migration/vmstate.h" 37da34e65cSMarkus Armbruster #include "qapi/error.h" 3839848901SIgor Mammedov #include "qapi/visitor.h" 390b8fa32fSMarkus Armbruster #include "qemu/module.h" 40c0907c9eSPaolo Bonzini 41c0907c9eSPaolo Bonzini /**************************************************************************** 42c0907c9eSPaolo Bonzini * Q35 host 43c0907c9eSPaolo Bonzini */ 44c0907c9eSPaolo Bonzini 459fa99d25SMarcel Apfelbaum #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 469fa99d25SMarcel Apfelbaum 4762d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 48c0907c9eSPaolo Bonzini { 49ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 50ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 5162d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 52c0907c9eSPaolo Bonzini 5367b4a74aSBernhard Beschow memory_region_add_subregion(s->mch.address_space_io, 5467b4a74aSBernhard Beschow MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 5562d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 56c0907c9eSPaolo Bonzini 5767b4a74aSBernhard Beschow memory_region_add_subregion(s->mch.address_space_io, 5867b4a74aSBernhard Beschow MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 5962d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 60c0907c9eSPaolo Bonzini 61a8de0115SPeng Hao /* register q35 0xcf8 port as coalesced pio */ 62a8de0115SPeng Hao memory_region_set_flush_coalesced(&pci->data_mem); 63a8de0115SPeng Hao memory_region_add_coalescing(&pci->conf_mem, 0, 4); 64a8de0115SPeng Hao 651115ff6dSDavid Gibson pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 661115ff6dSDavid Gibson s->mch.pci_address_space, 671115ff6dSDavid Gibson s->mch.address_space_io, 68c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 69e36102cbSBernhard Beschow 7099ba777eSMarkus Armbruster qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); 71c0907c9eSPaolo Bonzini } 72c0907c9eSPaolo Bonzini 73568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 74568f0690SDavid Gibson PCIBus *rootbus) 75568f0690SDavid Gibson { 7604c7d8b8SCole Robinson return "0000:00"; 7704c7d8b8SCole Robinson } 78568f0690SDavid Gibson 7939848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 80d7bce999SEric Blake const char *name, void *opaque, 8139848901SIgor Mammedov Error **errp) 8239848901SIgor Mammedov { 8339848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 84a0efbf16SMarkus Armbruster uint64_t val64; 85a0efbf16SMarkus Armbruster uint32_t value; 8639848901SIgor Mammedov 87a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 88a0efbf16SMarkus Armbruster ? 0 : range_lob(&s->mch.pci_hole); 89a0efbf16SMarkus Armbruster value = val64; 90a0efbf16SMarkus Armbruster assert(value == val64); 9151e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 9239848901SIgor Mammedov } 9339848901SIgor Mammedov 9439848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 95d7bce999SEric Blake const char *name, void *opaque, 9639848901SIgor Mammedov Error **errp) 9739848901SIgor Mammedov { 9839848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 99a0efbf16SMarkus Armbruster uint64_t val64; 100a0efbf16SMarkus Armbruster uint32_t value; 10139848901SIgor Mammedov 102a0efbf16SMarkus Armbruster val64 = range_is_empty(&s->mch.pci_hole) 103a0efbf16SMarkus Armbruster ? 0 : range_upb(&s->mch.pci_hole) + 1; 104a0efbf16SMarkus Armbruster value = val64; 105a0efbf16SMarkus Armbruster assert(value == val64); 10651e72bc1SEric Blake visit_type_uint32(v, name, &value, errp); 10739848901SIgor Mammedov } 10839848901SIgor Mammedov 1099fa99d25SMarcel Apfelbaum /* 1109fa99d25SMarcel Apfelbaum * The 64bit PCI hole start is set by the Guest firmware 1119fa99d25SMarcel Apfelbaum * as the address of the first 64bit PCI MEM resource. 1129fa99d25SMarcel Apfelbaum * If no PCI device has resources on the 64bit area, 1139fa99d25SMarcel Apfelbaum * the 64bit PCI hole will start after "over 4G RAM" and the 1149fa99d25SMarcel Apfelbaum * reserved space for memory hotplug if any. 1159fa99d25SMarcel Apfelbaum */ 116ccef5b1fSLaszlo Ersek static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 11739848901SIgor Mammedov { 1188b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1199fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 1208b42d730SMichael S. Tsirkin Range w64; 121a0efbf16SMarkus Armbruster uint64_t value; 12239848901SIgor Mammedov 1238b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 124a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_lob(&w64); 1259fa99d25SMarcel Apfelbaum if (!value && s->pci_hole64_fix) { 1269fa99d25SMarcel Apfelbaum value = pc_pci_hole64_start(); 1279fa99d25SMarcel Apfelbaum } 128ccef5b1fSLaszlo Ersek return value; 129ccef5b1fSLaszlo Ersek } 130ccef5b1fSLaszlo Ersek 131ccef5b1fSLaszlo Ersek static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 132ccef5b1fSLaszlo Ersek const char *name, void *opaque, 133ccef5b1fSLaszlo Ersek Error **errp) 134ccef5b1fSLaszlo Ersek { 135ccef5b1fSLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 136ccef5b1fSLaszlo Ersek 137ccef5b1fSLaszlo Ersek visit_type_uint64(v, name, &hole64_start, errp); 13839848901SIgor Mammedov } 13939848901SIgor Mammedov 1409fa99d25SMarcel Apfelbaum /* 1419fa99d25SMarcel Apfelbaum * The 64bit PCI hole end is set by the Guest firmware 1429fa99d25SMarcel Apfelbaum * as the address of the last 64bit PCI MEM resource. 1439fa99d25SMarcel Apfelbaum * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 1449fa99d25SMarcel Apfelbaum * that can be configured by the user. 1459fa99d25SMarcel Apfelbaum */ 14639848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 147d7bce999SEric Blake const char *name, void *opaque, 14839848901SIgor Mammedov Error **errp) 14939848901SIgor Mammedov { 1508b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1519fa99d25SMarcel Apfelbaum Q35PCIHost *s = Q35_HOST_DEVICE(obj); 152ed6bb4b5SLaszlo Ersek uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 1538b42d730SMichael S. Tsirkin Range w64; 1549fa99d25SMarcel Apfelbaum uint64_t value, hole64_end; 15539848901SIgor Mammedov 1568b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 157a0efbf16SMarkus Armbruster value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 1589fa99d25SMarcel Apfelbaum hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 1599fa99d25SMarcel Apfelbaum if (s->pci_hole64_fix && value < hole64_end) { 1609fa99d25SMarcel Apfelbaum value = hole64_end; 1619fa99d25SMarcel Apfelbaum } 162a0efbf16SMarkus Armbruster visit_type_uint64(v, name, &value, errp); 16339848901SIgor Mammedov } 16439848901SIgor Mammedov 1659fa99d25SMarcel Apfelbaum /* 1669fa99d25SMarcel Apfelbaum * NOTE: setting defaults for the mch.* fields in this table 1679fa99d25SMarcel Apfelbaum * doesn't work, because mch is a separate QOM object that is 1689fa99d25SMarcel Apfelbaum * zeroed by the object_initialize(&s->mch, ...) call inside 1699fa99d25SMarcel Apfelbaum * q35_host_initfn(). The default values for those 1709fa99d25SMarcel Apfelbaum * properties need to be initialized manually by 1719fa99d25SMarcel Apfelbaum * q35_host_initfn() after the object_initialize() call. 1729fa99d25SMarcel Apfelbaum */ 1732f295167SLaszlo Ersek static Property q35_host_props[] = { 17487f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 175c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 17639848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 1779fa99d25SMarcel Apfelbaum mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 178401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 179401f2f3eSEfimov Vasily mch.below_4g_mem_size, 0), 180401f2f3eSEfimov Vasily DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 181401f2f3eSEfimov Vasily mch.above_4g_mem_size, 0), 1829fa99d25SMarcel Apfelbaum DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 183c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 184c0907c9eSPaolo Bonzini }; 185c0907c9eSPaolo Bonzini 186c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 187c0907c9eSPaolo Bonzini { 188c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 189568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 190c0907c9eSPaolo Bonzini 191568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 19262d92e43SHu Tao dc->realize = q35_host_realize; 1934f67d30bSMarc-André Lureau device_class_set_props(dc, q35_host_props); 194bf8d4924SMarcel Apfelbaum /* Reason: needs to be wired up by pc_q35_init */ 195e90f2a8cSEduardo Habkost dc->user_creatable = false; 196125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 19768c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 198c0907c9eSPaolo Bonzini } 199c0907c9eSPaolo Bonzini 200c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 201c0907c9eSPaolo Bonzini { 202c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 20362d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 20464a7b8deSFelipe Franciosi PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); 20562d92e43SHu Tao 20662d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 20762d92e43SHu Tao "pci-conf-idx", 4); 20862d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 20962d92e43SHu Tao "pci-conf-data", 4); 210c0907c9eSPaolo Bonzini 2119fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); 212446de8b6SMarc-André Lureau qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 213c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 2149fa99d25SMarcel Apfelbaum /* mch's object_initialize resets the default value, set it again */ 2159fa99d25SMarcel Apfelbaum qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 2169fa99d25SMarcel Apfelbaum Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 2171e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 21839848901SIgor Mammedov q35_host_get_pci_hole_start, 219d2623129SMarkus Armbruster NULL, NULL, NULL); 22039848901SIgor Mammedov 2211e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 22239848901SIgor Mammedov q35_host_get_pci_hole_end, 223d2623129SMarkus Armbruster NULL, NULL, NULL); 22439848901SIgor Mammedov 2251e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 22639848901SIgor Mammedov q35_host_get_pci_hole64_start, 227d2623129SMarkus Armbruster NULL, NULL, NULL); 22839848901SIgor Mammedov 2291e507bb0SMarc-André Lureau object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 23039848901SIgor Mammedov q35_host_get_pci_hole64_end, 231d2623129SMarkus Armbruster NULL, NULL, NULL); 23239848901SIgor Mammedov 23364a7b8deSFelipe Franciosi object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, 234d2623129SMarkus Armbruster &pehb->size, OBJ_PROP_FLAG_READ); 235cbcaf79eSMichael S. Tsirkin 2363d664a9aSBernhard Beschow object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 237401f2f3eSEfimov Vasily (Object **) &s->mch.ram_memory, 238d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 239401f2f3eSEfimov Vasily 2403d664a9aSBernhard Beschow object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 241401f2f3eSEfimov Vasily (Object **) &s->mch.pci_address_space, 242d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 243401f2f3eSEfimov Vasily 2443d664a9aSBernhard Beschow object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 245401f2f3eSEfimov Vasily (Object **) &s->mch.system_memory, 246d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 247401f2f3eSEfimov Vasily 2483d664a9aSBernhard Beschow object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 249401f2f3eSEfimov Vasily (Object **) &s->mch.address_space_io, 250d2623129SMarkus Armbruster qdev_prop_allow_set_link_before_realize, 0); 251c0907c9eSPaolo Bonzini } 252c0907c9eSPaolo Bonzini 253c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 254c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 255c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 256c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 257c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 258c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 259c0907c9eSPaolo Bonzini }; 260c0907c9eSPaolo Bonzini 261c0907c9eSPaolo Bonzini /**************************************************************************** 262c0907c9eSPaolo Bonzini * MCH D0:F0 263c0907c9eSPaolo Bonzini */ 264c0907c9eSPaolo Bonzini 265f404220eSIgor Mammedov static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 266bafc90bdSGerd Hoffmann { 267bafc90bdSGerd Hoffmann return 0xffffffff; 268bafc90bdSGerd Hoffmann } 269bafc90bdSGerd Hoffmann 270f404220eSIgor Mammedov static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 271bafc90bdSGerd Hoffmann unsigned width) 272bafc90bdSGerd Hoffmann { 273bafc90bdSGerd Hoffmann /* nothing */ 274bafc90bdSGerd Hoffmann } 275bafc90bdSGerd Hoffmann 276f404220eSIgor Mammedov static const MemoryRegionOps blackhole_ops = { 277f404220eSIgor Mammedov .read = blackhole_read, 278f404220eSIgor Mammedov .write = blackhole_write, 279bafc90bdSGerd Hoffmann .valid.min_access_size = 1, 280bafc90bdSGerd Hoffmann .valid.max_access_size = 4, 281bafc90bdSGerd Hoffmann .impl.min_access_size = 4, 282bafc90bdSGerd Hoffmann .impl.max_access_size = 4, 283bafc90bdSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 284bafc90bdSGerd Hoffmann }; 285bafc90bdSGerd Hoffmann 286c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 287c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 288c0907c9eSPaolo Bonzini { 289ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 290ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 291ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 292c0907c9eSPaolo Bonzini 293c0907c9eSPaolo Bonzini uint64_t pciexbar; 294c0907c9eSPaolo Bonzini int enable; 295c0907c9eSPaolo Bonzini uint64_t addr; 296c0907c9eSPaolo Bonzini uint64_t addr_mask; 297c0907c9eSPaolo Bonzini uint32_t length; 298c0907c9eSPaolo Bonzini 299c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 300c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 301c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 302c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 303c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 304c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 305c0907c9eSPaolo Bonzini break; 306c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 307c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 308c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 309c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 310c0907c9eSPaolo Bonzini break; 311c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 312c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 313c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 314c0907c9eSPaolo Bonzini break; 315c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 3169b0ca75eSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); 3179b0ca75eSPhilippe Mathieu-Daudé return; 318c0907c9eSPaolo Bonzini default: 319c0907c9eSPaolo Bonzini abort(); 320c0907c9eSPaolo Bonzini } 321c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 322ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 323c0907c9eSPaolo Bonzini } 324c0907c9eSPaolo Bonzini 325c0907c9eSPaolo Bonzini /* PAM */ 326c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 327c0907c9eSPaolo Bonzini { 328ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 329c0907c9eSPaolo Bonzini int i; 330c0907c9eSPaolo Bonzini 331c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 332c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 333c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 33466175626SPhilippe Mathieu-Daudé pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 335c0907c9eSPaolo Bonzini } 336c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 337c0907c9eSPaolo Bonzini } 338c0907c9eSPaolo Bonzini 339c0907c9eSPaolo Bonzini /* SMRAM */ 340c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 341c0907c9eSPaolo Bonzini { 342ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 34364130fa4SPaolo Bonzini bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 344bafc90bdSGerd Hoffmann uint32_t tseg_size; 345ce88812fSHu Tao 34668c77acfSGerd Hoffmann /* implement SMRAM.D_LCK */ 34768c77acfSGerd Hoffmann if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 34868c77acfSGerd Hoffmann pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 34968c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 35068c77acfSGerd Hoffmann pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 35168c77acfSGerd Hoffmann } 35268c77acfSGerd Hoffmann 353c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 35464130fa4SPaolo Bonzini 35564130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 35664130fa4SPaolo Bonzini /* Hide (!) low SMRAM if H_SMRAME = 1 */ 35764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, h_smrame); 35864130fa4SPaolo Bonzini /* Show high SMRAM if H_SMRAME = 1 */ 35964130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, h_smrame); 36064130fa4SPaolo Bonzini } else { 36164130fa4SPaolo Bonzini /* Hide high SMRAM and low SMRAM */ 36264130fa4SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 36364130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 36464130fa4SPaolo Bonzini } 36564130fa4SPaolo Bonzini 36664130fa4SPaolo Bonzini if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 36764130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, !h_smrame); 36864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, h_smrame); 36964130fa4SPaolo Bonzini } else { 37064130fa4SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, false); 37164130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, false); 37264130fa4SPaolo Bonzini } 37364130fa4SPaolo Bonzini 374766a9814SZhenzhong Duan if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && 375766a9814SZhenzhong Duan (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { 376bafc90bdSGerd Hoffmann switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 377bafc90bdSGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 378bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 379bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024; 380bafc90bdSGerd Hoffmann break; 381bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 382bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 2; 383bafc90bdSGerd Hoffmann break; 384bafc90bdSGerd Hoffmann case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 385bafc90bdSGerd Hoffmann tseg_size = 1024 * 1024 * 8; 386bafc90bdSGerd Hoffmann break; 387bafc90bdSGerd Hoffmann default: 3882f295167SLaszlo Ersek tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 389bafc90bdSGerd Hoffmann break; 390bafc90bdSGerd Hoffmann } 391bafc90bdSGerd Hoffmann } else { 392bafc90bdSGerd Hoffmann tseg_size = 0; 393bafc90bdSGerd Hoffmann } 394bafc90bdSGerd Hoffmann memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 395bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 396bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_blackhole, tseg_size); 397bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 398bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size, 399bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 400bafc90bdSGerd Hoffmann 401bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, tseg_size); 402bafc90bdSGerd Hoffmann memory_region_set_size(&mch->tseg_window, tseg_size); 403bafc90bdSGerd Hoffmann memory_region_set_address(&mch->tseg_window, 404bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 405bafc90bdSGerd Hoffmann memory_region_set_alias_offset(&mch->tseg_window, 406bafc90bdSGerd Hoffmann mch->below_4g_mem_size - tseg_size); 407bafc90bdSGerd Hoffmann 408c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 409c0907c9eSPaolo Bonzini } 410c0907c9eSPaolo Bonzini 4112f295167SLaszlo Ersek static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 4122f295167SLaszlo Ersek { 4132f295167SLaszlo Ersek PCIDevice *pd = PCI_DEVICE(mch); 4142f295167SLaszlo Ersek uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 4152f295167SLaszlo Ersek 4162f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0 && 4172f295167SLaszlo Ersek pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 4182f295167SLaszlo Ersek pci_set_word(reg, mch->ext_tseg_mbytes); 4192f295167SLaszlo Ersek } 4202f295167SLaszlo Ersek } 4212f295167SLaszlo Ersek 422f404220eSIgor Mammedov static void mch_update_smbase_smram(MCHPCIState *mch) 423f404220eSIgor Mammedov { 424f404220eSIgor Mammedov PCIDevice *pd = PCI_DEVICE(mch); 425f404220eSIgor Mammedov uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 426f404220eSIgor Mammedov bool lck; 427f404220eSIgor Mammedov 428f404220eSIgor Mammedov if (!mch->has_smram_at_smbase) { 429f404220eSIgor Mammedov return; 430f404220eSIgor Mammedov } 431f404220eSIgor Mammedov 432f404220eSIgor Mammedov if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 433f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 434f404220eSIgor Mammedov MCH_HOST_BRIDGE_F_SMBASE_LCK; 435f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 436f404220eSIgor Mammedov return; 437f404220eSIgor Mammedov } 438f404220eSIgor Mammedov 439f404220eSIgor Mammedov /* 440f404220eSIgor Mammedov * default/reset state, discard written value 441f404220eSIgor Mammedov * which will disable SMRAM balackhole at SMBASE 442f404220eSIgor Mammedov */ 443f404220eSIgor Mammedov if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 444f404220eSIgor Mammedov *reg = 0x00; 445f404220eSIgor Mammedov } 446f404220eSIgor Mammedov 447f404220eSIgor Mammedov memory_region_transaction_begin(); 448f404220eSIgor Mammedov if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 449f404220eSIgor Mammedov /* disable all writes */ 450f404220eSIgor Mammedov pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 451f404220eSIgor Mammedov ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 452f404220eSIgor Mammedov *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 453f404220eSIgor Mammedov lck = true; 454f404220eSIgor Mammedov } else { 455f404220eSIgor Mammedov lck = false; 456f404220eSIgor Mammedov } 457f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, lck); 458f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, lck); 459f404220eSIgor Mammedov memory_region_transaction_commit(); 460f404220eSIgor Mammedov } 461f404220eSIgor Mammedov 462c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 463c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 464c0907c9eSPaolo Bonzini { 465c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 466c0907c9eSPaolo Bonzini 467c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 468c0907c9eSPaolo Bonzini 469c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 470c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 471c0907c9eSPaolo Bonzini mch_update_pam(mch); 472c0907c9eSPaolo Bonzini } 473c0907c9eSPaolo Bonzini 474c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 475c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 476c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 477c0907c9eSPaolo Bonzini } 478c0907c9eSPaolo Bonzini 479263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 480263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 481c0907c9eSPaolo Bonzini mch_update_smram(mch); 482c0907c9eSPaolo Bonzini } 4832f295167SLaszlo Ersek 4842f295167SLaszlo Ersek if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 4852f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 4862f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 4872f295167SLaszlo Ersek } 488f404220eSIgor Mammedov 489f404220eSIgor Mammedov if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 490f404220eSIgor Mammedov mch_update_smbase_smram(mch); 491f404220eSIgor Mammedov } 492c0907c9eSPaolo Bonzini } 493c0907c9eSPaolo Bonzini 494c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 495c0907c9eSPaolo Bonzini { 496c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 497c0907c9eSPaolo Bonzini mch_update_pam(mch); 498c0907c9eSPaolo Bonzini mch_update_smram(mch); 4992f295167SLaszlo Ersek mch_update_ext_tseg_mbytes(mch); 500f404220eSIgor Mammedov mch_update_smbase_smram(mch); 5014a441836SGerd Hoffmann 5024a441836SGerd Hoffmann /* 5034a441836SGerd Hoffmann * pci hole goes from end-of-low-ram to io-apic. 5044a441836SGerd Hoffmann * mmconfig will be excluded by the dsdt builder. 5054a441836SGerd Hoffmann */ 5064a441836SGerd Hoffmann range_set_bounds(&mch->pci_hole, 5074a441836SGerd Hoffmann mch->below_4g_mem_size, 5084a441836SGerd Hoffmann IO_APIC_DEFAULT_ADDRESS - 1); 509c0907c9eSPaolo Bonzini } 510c0907c9eSPaolo Bonzini 511c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 512c0907c9eSPaolo Bonzini { 513c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 514c0907c9eSPaolo Bonzini mch_update(mch); 515c0907c9eSPaolo Bonzini return 0; 516c0907c9eSPaolo Bonzini } 517c0907c9eSPaolo Bonzini 518c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 519c0907c9eSPaolo Bonzini .name = "mch", 520c0907c9eSPaolo Bonzini .version_id = 1, 521c0907c9eSPaolo Bonzini .minimum_version_id = 1, 522c0907c9eSPaolo Bonzini .post_load = mch_post_load, 523*e2bd53a3SRichard Henderson .fields = (const VMStateField[]) { 524ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 525f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 526f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 527f809c605SPaolo Bonzini */ 528f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 529c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 530c0907c9eSPaolo Bonzini } 531c0907c9eSPaolo Bonzini }; 532c0907c9eSPaolo Bonzini 533c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 534c0907c9eSPaolo Bonzini { 535c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 536c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 537c0907c9eSPaolo Bonzini 538c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 539c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 540c0907c9eSPaolo Bonzini 541263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 54277447524SGerd Hoffmann d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 543b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 544b66a67d7SGerd Hoffmann d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 545c0907c9eSPaolo Bonzini 5462f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > 0) { 5472f295167SLaszlo Ersek pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 5482f295167SLaszlo Ersek MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 5492f295167SLaszlo Ersek } 5502f295167SLaszlo Ersek 551f404220eSIgor Mammedov d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 552f404220eSIgor Mammedov d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 553f404220eSIgor Mammedov 554c0907c9eSPaolo Bonzini mch_update(mch); 555c0907c9eSPaolo Bonzini } 556c0907c9eSPaolo Bonzini 5579af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 558c0907c9eSPaolo Bonzini { 559c0907c9eSPaolo Bonzini int i; 560c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 561c0907c9eSPaolo Bonzini 5622f295167SLaszlo Ersek if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 5632f295167SLaszlo Ersek error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 5642f295167SLaszlo Ersek mch->ext_tseg_mbytes); 5652f295167SLaszlo Ersek return; 5662f295167SLaszlo Ersek } 5672f295167SLaszlo Ersek 56883d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 56909aa7be1SPhilippe Mathieu-Daudé pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); 57039848901SIgor Mammedov 571fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 57240c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 573dda53ee9SZihan Yang mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 574dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 575dda53ee9SZihan Yang memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 576c0907c9eSPaolo Bonzini &mch->smram_region, 1); 577fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 578fe6567d5SPaolo Bonzini 57964130fa4SPaolo Bonzini memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 580dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 581dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 58264130fa4SPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 58364130fa4SPaolo Bonzini &mch->open_high_smram, 1); 58464130fa4SPaolo Bonzini memory_region_set_enabled(&mch->open_high_smram, false); 58564130fa4SPaolo Bonzini 586fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 58751eae1e7SPhilippe Mathieu-Daudé memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB); 588fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 589fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 590dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 591dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 592fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 593dda53ee9SZihan Yang memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 594dda53ee9SZihan Yang &mch->low_smram); 59564130fa4SPaolo Bonzini memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 596dda53ee9SZihan Yang mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 597dda53ee9SZihan Yang MCH_HOST_BRIDGE_SMRAM_C_SIZE); 59864130fa4SPaolo Bonzini memory_region_set_enabled(&mch->high_smram, true); 59964130fa4SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 600bafc90bdSGerd Hoffmann 601bafc90bdSGerd Hoffmann memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 602f404220eSIgor Mammedov &blackhole_ops, NULL, 603bafc90bdSGerd Hoffmann "tseg-blackhole", 0); 604bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_blackhole, false); 605bafc90bdSGerd Hoffmann memory_region_add_subregion_overlap(mch->system_memory, 606bafc90bdSGerd Hoffmann mch->below_4g_mem_size, 607bafc90bdSGerd Hoffmann &mch->tseg_blackhole, 1); 608bafc90bdSGerd Hoffmann 609bafc90bdSGerd Hoffmann memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 610bafc90bdSGerd Hoffmann mch->ram_memory, mch->below_4g_mem_size, 0); 611bafc90bdSGerd Hoffmann memory_region_set_enabled(&mch->tseg_window, false); 612bafc90bdSGerd Hoffmann memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 613bafc90bdSGerd Hoffmann &mch->tseg_window); 614f404220eSIgor Mammedov 615f404220eSIgor Mammedov /* 616f404220eSIgor Mammedov * This is not what hardware does, so it's QEMU specific hack. 617f404220eSIgor Mammedov * See commit message for details. 618f404220eSIgor Mammedov */ 619f404220eSIgor Mammedov memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 620f404220eSIgor Mammedov NULL, "smbase-blackhole", 621f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 622f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_blackhole, false); 623f404220eSIgor Mammedov memory_region_add_subregion_overlap(mch->system_memory, 624f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 625f404220eSIgor Mammedov &mch->smbase_blackhole, 1); 626f404220eSIgor Mammedov 627f404220eSIgor Mammedov memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 628f404220eSIgor Mammedov "smbase-window", mch->ram_memory, 629f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_ADDR, 630f404220eSIgor Mammedov MCH_HOST_BRIDGE_SMBASE_SIZE); 631f404220eSIgor Mammedov memory_region_set_enabled(&mch->smbase_window, false); 632f404220eSIgor Mammedov memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 633f404220eSIgor Mammedov &mch->smbase_window); 634f404220eSIgor Mammedov 635fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 636d2623129SMarkus Armbruster OBJECT(&mch->smram)); 637fe6567d5SPaolo Bonzini 6389e57b818SBernhard Beschow init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory, 6399e57b818SBernhard Beschow mch->system_memory, mch->pci_address_space, 640ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 641f6a3c86eSPhilippe Mathieu-Daudé for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { 6429e57b818SBernhard Beschow init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory, 6439e57b818SBernhard Beschow mch->system_memory, mch->pci_address_space, 644ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 645c0907c9eSPaolo Bonzini } 646c0907c9eSPaolo Bonzini } 647c0907c9eSPaolo Bonzini 6486f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 6496f1426abSMichael S. Tsirkin { 6506f1426abSMichael S. Tsirkin bool ambiguous; 6516f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 6526f1426abSMichael S. Tsirkin if (!o) { 6536f1426abSMichael S. Tsirkin return 0; 6546f1426abSMichael S. Tsirkin } 6556f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 6566f1426abSMichael S. Tsirkin } 6576f1426abSMichael S. Tsirkin 6582f295167SLaszlo Ersek static Property mch_props[] = { 6592f295167SLaszlo Ersek DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 6602f295167SLaszlo Ersek 16), 661f404220eSIgor Mammedov DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 6622f295167SLaszlo Ersek DEFINE_PROP_END_OF_LIST(), 6632f295167SLaszlo Ersek }; 6642f295167SLaszlo Ersek 665c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 666c0907c9eSPaolo Bonzini { 667c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 668c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 669c0907c9eSPaolo Bonzini 6709af21dbeSMarkus Armbruster k->realize = mch_realize; 671c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 672c0907c9eSPaolo Bonzini dc->reset = mch_reset; 6734f67d30bSMarc-André Lureau device_class_set_props(dc, mch_props); 674125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 675c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 676c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 677c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 678d4715481SDaniel P. Berrangé /* 679d4715481SDaniel P. Berrangé * The 'q35' machine type implements an Intel Series 3 chipset, 680d4715481SDaniel P. Berrangé * of which there are several variants. The key difference between 681d4715481SDaniel P. Berrangé * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 682d4715481SDaniel P. Berrangé * the latter has an integrated graphics adapter. QEMU does not 683d4715481SDaniel P. Berrangé * implement integrated graphics, so uses the PCI ID for the 82P35 684d4715481SDaniel P. Berrangé * chipset. 685d4715481SDaniel P. Berrangé */ 686d4715481SDaniel P. Berrangé k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 687451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 688c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 68908c58f92SMarkus Armbruster /* 69008c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 69108c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 69208c58f92SMarkus Armbruster */ 693e90f2a8cSEduardo Habkost dc->user_creatable = false; 694c0907c9eSPaolo Bonzini } 695c0907c9eSPaolo Bonzini 696c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 697c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 698c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 699c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 700c0907c9eSPaolo Bonzini .class_init = mch_class_init, 701fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 702fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 703fd3b02c8SEduardo Habkost { }, 704fd3b02c8SEduardo Habkost }, 705c0907c9eSPaolo Bonzini }; 706c0907c9eSPaolo Bonzini 707c0907c9eSPaolo Bonzini static void q35_register(void) 708c0907c9eSPaolo Bonzini { 709c0907c9eSPaolo Bonzini type_register_static(&mch_info); 710c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 711c0907c9eSPaolo Bonzini } 712c0907c9eSPaolo Bonzini 713c0907c9eSPaolo Bonzini type_init(q35_register); 714