1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU MCH/ICH9 PCI Bridge Emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5c0907c9eSPaolo Bonzini * Copyright (c) 2009, 2010, 2011 6c0907c9eSPaolo Bonzini * Isaku Yamahata <yamahata at valinux co jp> 7c0907c9eSPaolo Bonzini * VA Linux Systems Japan K.K. 8c0907c9eSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9c0907c9eSPaolo Bonzini * 10ef9f7b58SGonglei * This is based on piix.c, but heavily modified. 11c0907c9eSPaolo Bonzini * 12c0907c9eSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 13c0907c9eSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 14c0907c9eSPaolo Bonzini * in the Software without restriction, including without limitation the rights 15c0907c9eSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16c0907c9eSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 17c0907c9eSPaolo Bonzini * furnished to do so, subject to the following conditions: 18c0907c9eSPaolo Bonzini * 19c0907c9eSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 20c0907c9eSPaolo Bonzini * all copies or substantial portions of the Software. 21c0907c9eSPaolo Bonzini * 22c0907c9eSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23c0907c9eSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24c0907c9eSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25c0907c9eSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26c0907c9eSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27c0907c9eSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28c0907c9eSPaolo Bonzini * THE SOFTWARE. 29c0907c9eSPaolo Bonzini */ 30c0907c9eSPaolo Bonzini #include "hw/hw.h" 31c0907c9eSPaolo Bonzini #include "hw/pci-host/q35.h" 3239848901SIgor Mammedov #include "qapi/visitor.h" 33c0907c9eSPaolo Bonzini 34c0907c9eSPaolo Bonzini /**************************************************************************** 35c0907c9eSPaolo Bonzini * Q35 host 36c0907c9eSPaolo Bonzini */ 37c0907c9eSPaolo Bonzini 3862d92e43SHu Tao static void q35_host_realize(DeviceState *dev, Error **errp) 39c0907c9eSPaolo Bonzini { 40ce88812fSHu Tao PCIHostState *pci = PCI_HOST_BRIDGE(dev); 41ce88812fSHu Tao Q35PCIHost *s = Q35_HOST_DEVICE(dev); 4262d92e43SHu Tao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 43c0907c9eSPaolo Bonzini 4462d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 4562d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46c0907c9eSPaolo Bonzini 4762d92e43SHu Tao sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 4862d92e43SHu Tao sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 49c0907c9eSPaolo Bonzini 50ce88812fSHu Tao pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 51c0907c9eSPaolo Bonzini s->mch.pci_address_space, s->mch.address_space_io, 52c0907c9eSPaolo Bonzini 0, TYPE_PCIE_BUS); 53ce88812fSHu Tao qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 54c0907c9eSPaolo Bonzini qdev_init_nofail(DEVICE(&s->mch)); 55c0907c9eSPaolo Bonzini } 56c0907c9eSPaolo Bonzini 57568f0690SDavid Gibson static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 58568f0690SDavid Gibson PCIBus *rootbus) 59568f0690SDavid Gibson { 6004c7d8b8SCole Robinson Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 6104c7d8b8SCole Robinson 62568f0690SDavid Gibson /* For backwards compat with old device paths */ 6304c7d8b8SCole Robinson if (s->mch.short_root_bus) { 64568f0690SDavid Gibson return "0000"; 65568f0690SDavid Gibson } 6604c7d8b8SCole Robinson return "0000:00"; 6704c7d8b8SCole Robinson } 68568f0690SDavid Gibson 6939848901SIgor Mammedov static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 7039848901SIgor Mammedov void *opaque, const char *name, 7139848901SIgor Mammedov Error **errp) 7239848901SIgor Mammedov { 7339848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 7439848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.begin; 7539848901SIgor Mammedov 7639848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 7739848901SIgor Mammedov } 7839848901SIgor Mammedov 7939848901SIgor Mammedov static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 8039848901SIgor Mammedov void *opaque, const char *name, 8139848901SIgor Mammedov Error **errp) 8239848901SIgor Mammedov { 8339848901SIgor Mammedov Q35PCIHost *s = Q35_HOST_DEVICE(obj); 8439848901SIgor Mammedov uint32_t value = s->mch.pci_info.w32.end; 8539848901SIgor Mammedov 8639848901SIgor Mammedov visit_type_uint32(v, &value, name, errp); 8739848901SIgor Mammedov } 8839848901SIgor Mammedov 8939848901SIgor Mammedov static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 9039848901SIgor Mammedov void *opaque, const char *name, 9139848901SIgor Mammedov Error **errp) 9239848901SIgor Mammedov { 938b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 948b42d730SMichael S. Tsirkin Range w64; 9539848901SIgor Mammedov 968b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 978b42d730SMichael S. Tsirkin 988b42d730SMichael S. Tsirkin visit_type_uint64(v, &w64.begin, name, errp); 9939848901SIgor Mammedov } 10039848901SIgor Mammedov 10139848901SIgor Mammedov static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 10239848901SIgor Mammedov void *opaque, const char *name, 10339848901SIgor Mammedov Error **errp) 10439848901SIgor Mammedov { 1058b42d730SMichael S. Tsirkin PCIHostState *h = PCI_HOST_BRIDGE(obj); 1068b42d730SMichael S. Tsirkin Range w64; 10739848901SIgor Mammedov 1088b42d730SMichael S. Tsirkin pci_bus_get_w64_range(h->bus, &w64); 1098b42d730SMichael S. Tsirkin 1108b42d730SMichael S. Tsirkin visit_type_uint64(v, &w64.end, name, errp); 11139848901SIgor Mammedov } 11239848901SIgor Mammedov 113cbcaf79eSMichael S. Tsirkin static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, 114cbcaf79eSMichael S. Tsirkin void *opaque, const char *name, 115cbcaf79eSMichael S. Tsirkin Error **errp) 116cbcaf79eSMichael S. Tsirkin { 117cbcaf79eSMichael S. Tsirkin PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 118cbcaf79eSMichael S. Tsirkin uint32_t value = e->size; 119cbcaf79eSMichael S. Tsirkin 120cbcaf79eSMichael S. Tsirkin visit_type_uint32(v, &value, name, errp); 121cbcaf79eSMichael S. Tsirkin } 122cbcaf79eSMichael S. Tsirkin 123c0907c9eSPaolo Bonzini static Property mch_props[] = { 12487f65245SMichael S. Tsirkin DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 125c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 12639848901SIgor Mammedov DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 12739848901SIgor Mammedov mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 12804c7d8b8SCole Robinson DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 129c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 130c0907c9eSPaolo Bonzini }; 131c0907c9eSPaolo Bonzini 132c0907c9eSPaolo Bonzini static void q35_host_class_init(ObjectClass *klass, void *data) 133c0907c9eSPaolo Bonzini { 134c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 135568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 136c0907c9eSPaolo Bonzini 137568f0690SDavid Gibson hc->root_bus_path = q35_host_root_bus_path; 13862d92e43SHu Tao dc->realize = q35_host_realize; 139c0907c9eSPaolo Bonzini dc->props = mch_props; 140125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 14168c0e134SMichael S. Tsirkin dc->fw_name = "pci"; 142c0907c9eSPaolo Bonzini } 143c0907c9eSPaolo Bonzini 144c0907c9eSPaolo Bonzini static void q35_host_initfn(Object *obj) 145c0907c9eSPaolo Bonzini { 146c0907c9eSPaolo Bonzini Q35PCIHost *s = Q35_HOST_DEVICE(obj); 14762d92e43SHu Tao PCIHostState *phb = PCI_HOST_BRIDGE(obj); 14862d92e43SHu Tao 14962d92e43SHu Tao memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 15062d92e43SHu Tao "pci-conf-idx", 4); 15162d92e43SHu Tao memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 15262d92e43SHu Tao "pci-conf-data", 4); 153c0907c9eSPaolo Bonzini 154213f0c4fSAndreas Färber object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 155c0907c9eSPaolo Bonzini object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 156c0907c9eSPaolo Bonzini qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 157c0907c9eSPaolo Bonzini qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 15839848901SIgor Mammedov 15939848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 16039848901SIgor Mammedov q35_host_get_pci_hole_start, 16139848901SIgor Mammedov NULL, NULL, NULL, NULL); 16239848901SIgor Mammedov 16339848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 16439848901SIgor Mammedov q35_host_get_pci_hole_end, 16539848901SIgor Mammedov NULL, NULL, NULL, NULL); 16639848901SIgor Mammedov 16739848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 16839848901SIgor Mammedov q35_host_get_pci_hole64_start, 16939848901SIgor Mammedov NULL, NULL, NULL, NULL); 17039848901SIgor Mammedov 17139848901SIgor Mammedov object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 17239848901SIgor Mammedov q35_host_get_pci_hole64_end, 17339848901SIgor Mammedov NULL, NULL, NULL, NULL); 17439848901SIgor Mammedov 175cbcaf79eSMichael S. Tsirkin object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 176cbcaf79eSMichael S. Tsirkin q35_host_get_mmcfg_size, 177cbcaf79eSMichael S. Tsirkin NULL, NULL, NULL, NULL); 178cbcaf79eSMichael S. Tsirkin 17939848901SIgor Mammedov /* Leave enough space for the biggest MCFG BAR */ 18039848901SIgor Mammedov /* TODO: this matches current bios behaviour, but 18139848901SIgor Mammedov * it's not a power of two, which means an MTRR 18239848901SIgor Mammedov * can't cover it exactly. 18339848901SIgor Mammedov */ 18439848901SIgor Mammedov s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 18539848901SIgor Mammedov MCH_HOST_BRIDGE_PCIEXBAR_MAX; 18639848901SIgor Mammedov s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 187c0907c9eSPaolo Bonzini } 188c0907c9eSPaolo Bonzini 189c0907c9eSPaolo Bonzini static const TypeInfo q35_host_info = { 190c0907c9eSPaolo Bonzini .name = TYPE_Q35_HOST_DEVICE, 191c0907c9eSPaolo Bonzini .parent = TYPE_PCIE_HOST_BRIDGE, 192c0907c9eSPaolo Bonzini .instance_size = sizeof(Q35PCIHost), 193c0907c9eSPaolo Bonzini .instance_init = q35_host_initfn, 194c0907c9eSPaolo Bonzini .class_init = q35_host_class_init, 195c0907c9eSPaolo Bonzini }; 196c0907c9eSPaolo Bonzini 197c0907c9eSPaolo Bonzini /**************************************************************************** 198c0907c9eSPaolo Bonzini * MCH D0:F0 199c0907c9eSPaolo Bonzini */ 200c0907c9eSPaolo Bonzini 201c0907c9eSPaolo Bonzini /* PCIe MMCFG */ 202c0907c9eSPaolo Bonzini static void mch_update_pciexbar(MCHPCIState *mch) 203c0907c9eSPaolo Bonzini { 204ce88812fSHu Tao PCIDevice *pci_dev = PCI_DEVICE(mch); 205ce88812fSHu Tao BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 206ce88812fSHu Tao PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 207c0907c9eSPaolo Bonzini 208c0907c9eSPaolo Bonzini uint64_t pciexbar; 209c0907c9eSPaolo Bonzini int enable; 210c0907c9eSPaolo Bonzini uint64_t addr; 211c0907c9eSPaolo Bonzini uint64_t addr_mask; 212c0907c9eSPaolo Bonzini uint32_t length; 213c0907c9eSPaolo Bonzini 214c0907c9eSPaolo Bonzini pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 215c0907c9eSPaolo Bonzini enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 216c0907c9eSPaolo Bonzini addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 217c0907c9eSPaolo Bonzini switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 218c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 219c0907c9eSPaolo Bonzini length = 256 * 1024 * 1024; 220c0907c9eSPaolo Bonzini break; 221c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 222c0907c9eSPaolo Bonzini length = 128 * 1024 * 1024; 223c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 224c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 225c0907c9eSPaolo Bonzini break; 226c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 227c0907c9eSPaolo Bonzini length = 64 * 1024 * 1024; 228c0907c9eSPaolo Bonzini addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 229c0907c9eSPaolo Bonzini break; 230c0907c9eSPaolo Bonzini case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 231c0907c9eSPaolo Bonzini default: 232c0907c9eSPaolo Bonzini enable = 0; 233c0907c9eSPaolo Bonzini length = 0; 234c0907c9eSPaolo Bonzini abort(); 235c0907c9eSPaolo Bonzini break; 236c0907c9eSPaolo Bonzini } 237c0907c9eSPaolo Bonzini addr = pciexbar & addr_mask; 238ce88812fSHu Tao pcie_host_mmcfg_update(pehb, enable, addr, length); 239636228a8SMichael S. Tsirkin /* Leave enough space for the MCFG BAR */ 240636228a8SMichael S. Tsirkin /* 241636228a8SMichael S. Tsirkin * TODO: this matches current bios behaviour, but it's not a power of two, 242636228a8SMichael S. Tsirkin * which means an MTRR can't cover it exactly. 243636228a8SMichael S. Tsirkin */ 244636228a8SMichael S. Tsirkin if (enable) { 245636228a8SMichael S. Tsirkin mch->pci_info.w32.begin = addr + length; 246636228a8SMichael S. Tsirkin } else { 247636228a8SMichael S. Tsirkin mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 248636228a8SMichael S. Tsirkin } 249c0907c9eSPaolo Bonzini } 250c0907c9eSPaolo Bonzini 251c0907c9eSPaolo Bonzini /* PAM */ 252c0907c9eSPaolo Bonzini static void mch_update_pam(MCHPCIState *mch) 253c0907c9eSPaolo Bonzini { 254ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 255c0907c9eSPaolo Bonzini int i; 256c0907c9eSPaolo Bonzini 257c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 258c0907c9eSPaolo Bonzini for (i = 0; i < 13; i++) { 259c0907c9eSPaolo Bonzini pam_update(&mch->pam_regions[i], i, 260ce88812fSHu Tao pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 261c0907c9eSPaolo Bonzini } 262c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 263c0907c9eSPaolo Bonzini } 264c0907c9eSPaolo Bonzini 265c0907c9eSPaolo Bonzini /* SMRAM */ 266c0907c9eSPaolo Bonzini static void mch_update_smram(MCHPCIState *mch) 267c0907c9eSPaolo Bonzini { 268ce88812fSHu Tao PCIDevice *pd = PCI_DEVICE(mch); 269ce88812fSHu Tao 270c0907c9eSPaolo Bonzini memory_region_transaction_begin(); 271*f809c605SPaolo Bonzini smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM]); 272fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, 273fe6567d5SPaolo Bonzini pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME); 274c0907c9eSPaolo Bonzini memory_region_transaction_commit(); 275c0907c9eSPaolo Bonzini } 276c0907c9eSPaolo Bonzini 277c0907c9eSPaolo Bonzini static void mch_write_config(PCIDevice *d, 278c0907c9eSPaolo Bonzini uint32_t address, uint32_t val, int len) 279c0907c9eSPaolo Bonzini { 280c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 281c0907c9eSPaolo Bonzini 282c0907c9eSPaolo Bonzini /* XXX: implement SMRAM.D_LOCK */ 283c0907c9eSPaolo Bonzini pci_default_write_config(d, address, val, len); 284c0907c9eSPaolo Bonzini 285c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 286c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PAM_SIZE)) { 287c0907c9eSPaolo Bonzini mch_update_pam(mch); 288c0907c9eSPaolo Bonzini } 289c0907c9eSPaolo Bonzini 290c0907c9eSPaolo Bonzini if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 291c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 292c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 293c0907c9eSPaolo Bonzini } 294c0907c9eSPaolo Bonzini 295263cf436SBALATON Zoltan if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 296263cf436SBALATON Zoltan MCH_HOST_BRIDGE_SMRAM_SIZE)) { 297c0907c9eSPaolo Bonzini mch_update_smram(mch); 298c0907c9eSPaolo Bonzini } 299c0907c9eSPaolo Bonzini } 300c0907c9eSPaolo Bonzini 301c0907c9eSPaolo Bonzini static void mch_update(MCHPCIState *mch) 302c0907c9eSPaolo Bonzini { 303c0907c9eSPaolo Bonzini mch_update_pciexbar(mch); 304c0907c9eSPaolo Bonzini mch_update_pam(mch); 305c0907c9eSPaolo Bonzini mch_update_smram(mch); 306c0907c9eSPaolo Bonzini } 307c0907c9eSPaolo Bonzini 308c0907c9eSPaolo Bonzini static int mch_post_load(void *opaque, int version_id) 309c0907c9eSPaolo Bonzini { 310c0907c9eSPaolo Bonzini MCHPCIState *mch = opaque; 311c0907c9eSPaolo Bonzini mch_update(mch); 312c0907c9eSPaolo Bonzini return 0; 313c0907c9eSPaolo Bonzini } 314c0907c9eSPaolo Bonzini 315c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_mch = { 316c0907c9eSPaolo Bonzini .name = "mch", 317c0907c9eSPaolo Bonzini .version_id = 1, 318c0907c9eSPaolo Bonzini .minimum_version_id = 1, 319c0907c9eSPaolo Bonzini .post_load = mch_post_load, 320c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 321ce88812fSHu Tao VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 322*f809c605SPaolo Bonzini /* Used to be smm_enabled, which was basically always zero because 323*f809c605SPaolo Bonzini * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 324*f809c605SPaolo Bonzini */ 325*f809c605SPaolo Bonzini VMSTATE_UNUSED(1), 326c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 327c0907c9eSPaolo Bonzini } 328c0907c9eSPaolo Bonzini }; 329c0907c9eSPaolo Bonzini 330c0907c9eSPaolo Bonzini static void mch_reset(DeviceState *qdev) 331c0907c9eSPaolo Bonzini { 332c0907c9eSPaolo Bonzini PCIDevice *d = PCI_DEVICE(qdev); 333c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 334c0907c9eSPaolo Bonzini 335c0907c9eSPaolo Bonzini pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 336c0907c9eSPaolo Bonzini MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 337c0907c9eSPaolo Bonzini 338263cf436SBALATON Zoltan d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 339c0907c9eSPaolo Bonzini 340c0907c9eSPaolo Bonzini mch_update(mch); 341c0907c9eSPaolo Bonzini } 342c0907c9eSPaolo Bonzini 343a52a7fdfSLe Tan static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 344a52a7fdfSLe Tan { 345a52a7fdfSLe Tan IntelIOMMUState *s = opaque; 346a52a7fdfSLe Tan VTDAddressSpace **pvtd_as; 347a52a7fdfSLe Tan int bus_num = pci_bus_num(bus); 348a52a7fdfSLe Tan 349a52a7fdfSLe Tan assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX); 350a52a7fdfSLe Tan assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX); 351a52a7fdfSLe Tan 352a52a7fdfSLe Tan pvtd_as = s->address_spaces[bus_num]; 353a52a7fdfSLe Tan if (!pvtd_as) { 354a52a7fdfSLe Tan /* No corresponding free() */ 355a52a7fdfSLe Tan pvtd_as = g_malloc0(sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX); 356a52a7fdfSLe Tan s->address_spaces[bus_num] = pvtd_as; 357a52a7fdfSLe Tan } 358a52a7fdfSLe Tan if (!pvtd_as[devfn]) { 359a52a7fdfSLe Tan pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace)); 360a52a7fdfSLe Tan 361a52a7fdfSLe Tan pvtd_as[devfn]->bus_num = (uint8_t)bus_num; 362a52a7fdfSLe Tan pvtd_as[devfn]->devfn = (uint8_t)devfn; 363a52a7fdfSLe Tan pvtd_as[devfn]->iommu_state = s; 364d92fa2dcSLe Tan pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0; 365a52a7fdfSLe Tan memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s), 366a52a7fdfSLe Tan &s->iommu_ops, "intel_iommu", UINT64_MAX); 367a52a7fdfSLe Tan address_space_init(&pvtd_as[devfn]->as, 368a52a7fdfSLe Tan &pvtd_as[devfn]->iommu, "intel_iommu"); 369a52a7fdfSLe Tan } 370a52a7fdfSLe Tan return &pvtd_as[devfn]->as; 371a52a7fdfSLe Tan } 372a52a7fdfSLe Tan 373a52a7fdfSLe Tan static void mch_init_dmar(MCHPCIState *mch) 374a52a7fdfSLe Tan { 375a52a7fdfSLe Tan PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); 376a52a7fdfSLe Tan 377a52a7fdfSLe Tan mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE)); 378a52a7fdfSLe Tan object_property_add_child(OBJECT(mch), "intel-iommu", 379a52a7fdfSLe Tan OBJECT(mch->iommu), NULL); 380a52a7fdfSLe Tan qdev_init_nofail(DEVICE(mch->iommu)); 381a52a7fdfSLe Tan sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 382a52a7fdfSLe Tan 383a52a7fdfSLe Tan pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); 384a52a7fdfSLe Tan } 385a52a7fdfSLe Tan 3869af21dbeSMarkus Armbruster static void mch_realize(PCIDevice *d, Error **errp) 387c0907c9eSPaolo Bonzini { 388c0907c9eSPaolo Bonzini int i; 389c0907c9eSPaolo Bonzini MCHPCIState *mch = MCH_PCI_DEVICE(d); 390c0907c9eSPaolo Bonzini 39183d08f26SMichael S. Tsirkin /* setup pci memory mapping */ 39283d08f26SMichael S. Tsirkin pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 39383d08f26SMichael S. Tsirkin mch->pci_address_space); 39439848901SIgor Mammedov 395fe6567d5SPaolo Bonzini /* if *disabled* show SMRAM to all CPUs */ 39640c5dce9SPaolo Bonzini memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 397c0907c9eSPaolo Bonzini mch->pci_address_space, 0xa0000, 0x20000); 398c0907c9eSPaolo Bonzini memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 399c0907c9eSPaolo Bonzini &mch->smram_region, 1); 400fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram_region, true); 401fe6567d5SPaolo Bonzini 402fe6567d5SPaolo Bonzini /* smram, as seen by SMM CPUs */ 403fe6567d5SPaolo Bonzini memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 404fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->smram, true); 405fe6567d5SPaolo Bonzini memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 406*f809c605SPaolo Bonzini mch->ram_memory, 0xa0000, 0x20000); 407fe6567d5SPaolo Bonzini memory_region_set_enabled(&mch->low_smram, true); 408fe6567d5SPaolo Bonzini memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 409fe6567d5SPaolo Bonzini object_property_add_const_link(qdev_get_machine(), "smram", 410fe6567d5SPaolo Bonzini OBJECT(&mch->smram), &error_abort); 411fe6567d5SPaolo Bonzini 412ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 413ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[0], 414ac40aa15SLe Tan PAM_BIOS_BASE, PAM_BIOS_SIZE); 415c0907c9eSPaolo Bonzini for (i = 0; i < 12; ++i) { 416ac40aa15SLe Tan init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 417ac40aa15SLe Tan mch->pci_address_space, &mch->pam_regions[i+1], 418ac40aa15SLe Tan PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 419c0907c9eSPaolo Bonzini } 420a52a7fdfSLe Tan /* Intel IOMMU (VT-d) */ 4218caff636SMarcel Apfelbaum if (machine_iommu(current_machine)) { 422a52a7fdfSLe Tan mch_init_dmar(mch); 423a52a7fdfSLe Tan } 424c0907c9eSPaolo Bonzini } 425c0907c9eSPaolo Bonzini 4266f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void) 4276f1426abSMichael S. Tsirkin { 4286f1426abSMichael S. Tsirkin bool ambiguous; 4296f1426abSMichael S. Tsirkin Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 4306f1426abSMichael S. Tsirkin if (!o) { 4316f1426abSMichael S. Tsirkin return 0; 4326f1426abSMichael S. Tsirkin } 4336f1426abSMichael S. Tsirkin return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 4346f1426abSMichael S. Tsirkin } 4356f1426abSMichael S. Tsirkin 436c0907c9eSPaolo Bonzini static void mch_class_init(ObjectClass *klass, void *data) 437c0907c9eSPaolo Bonzini { 438c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 439c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 440c0907c9eSPaolo Bonzini 4419af21dbeSMarkus Armbruster k->realize = mch_realize; 442c0907c9eSPaolo Bonzini k->config_write = mch_write_config; 443c0907c9eSPaolo Bonzini dc->reset = mch_reset; 444125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 445c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 446c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_mch; 447c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_INTEL; 448c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 449451f7846SRichard W.M. Jones k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 450c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_HOST; 45108c58f92SMarkus Armbruster /* 45208c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 45308c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 45408c58f92SMarkus Armbruster */ 45508c58f92SMarkus Armbruster dc->cannot_instantiate_with_device_add_yet = true; 456c0907c9eSPaolo Bonzini } 457c0907c9eSPaolo Bonzini 458c0907c9eSPaolo Bonzini static const TypeInfo mch_info = { 459c0907c9eSPaolo Bonzini .name = TYPE_MCH_PCI_DEVICE, 460c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 461c0907c9eSPaolo Bonzini .instance_size = sizeof(MCHPCIState), 462c0907c9eSPaolo Bonzini .class_init = mch_class_init, 463c0907c9eSPaolo Bonzini }; 464c0907c9eSPaolo Bonzini 465c0907c9eSPaolo Bonzini static void q35_register(void) 466c0907c9eSPaolo Bonzini { 467c0907c9eSPaolo Bonzini type_register_static(&mch_info); 468c0907c9eSPaolo Bonzini type_register_static(&q35_host_info); 469c0907c9eSPaolo Bonzini } 470c0907c9eSPaolo Bonzini 471c0907c9eSPaolo Bonzini type_init(q35_register); 472