1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/visitor.h" 34 35 /**************************************************************************** 36 * Q35 host 37 */ 38 39 static void q35_host_realize(DeviceState *dev, Error **errp) 40 { 41 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 42 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 43 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 44 45 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 46 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 47 48 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 49 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 50 51 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 52 s->mch.pci_address_space, s->mch.address_space_io, 53 0, TYPE_PCIE_BUS); 54 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 55 qdev_init_nofail(DEVICE(&s->mch)); 56 } 57 58 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 59 PCIBus *rootbus) 60 { 61 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 62 63 /* For backwards compat with old device paths */ 64 if (s->mch.short_root_bus) { 65 return "0000"; 66 } 67 return "0000:00"; 68 } 69 70 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 71 const char *name, void *opaque, 72 Error **errp) 73 { 74 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 75 uint32_t value = s->mch.pci_info.w32.begin; 76 77 visit_type_uint32(v, name, &value, errp); 78 } 79 80 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 81 const char *name, void *opaque, 82 Error **errp) 83 { 84 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 85 uint32_t value = s->mch.pci_info.w32.end; 86 87 visit_type_uint32(v, name, &value, errp); 88 } 89 90 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 91 const char *name, void *opaque, 92 Error **errp) 93 { 94 PCIHostState *h = PCI_HOST_BRIDGE(obj); 95 Range w64; 96 97 pci_bus_get_w64_range(h->bus, &w64); 98 99 visit_type_uint64(v, name, &w64.begin, errp); 100 } 101 102 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 103 const char *name, void *opaque, 104 Error **errp) 105 { 106 PCIHostState *h = PCI_HOST_BRIDGE(obj); 107 Range w64; 108 109 pci_bus_get_w64_range(h->bus, &w64); 110 111 visit_type_uint64(v, name, &w64.end, errp); 112 } 113 114 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 115 void *opaque, Error **errp) 116 { 117 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 118 uint32_t value = e->size; 119 120 visit_type_uint32(v, name, &value, errp); 121 } 122 123 static Property mch_props[] = { 124 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 125 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 126 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 127 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 128 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 129 DEFINE_PROP_END_OF_LIST(), 130 }; 131 132 static void q35_host_class_init(ObjectClass *klass, void *data) 133 { 134 DeviceClass *dc = DEVICE_CLASS(klass); 135 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 136 137 hc->root_bus_path = q35_host_root_bus_path; 138 dc->realize = q35_host_realize; 139 dc->props = mch_props; 140 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 141 dc->fw_name = "pci"; 142 } 143 144 static void q35_host_initfn(Object *obj) 145 { 146 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 147 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 148 149 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 150 "pci-conf-idx", 4); 151 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 152 "pci-conf-data", 4); 153 154 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 155 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 156 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 157 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 158 159 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 160 q35_host_get_pci_hole_start, 161 NULL, NULL, NULL, NULL); 162 163 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 164 q35_host_get_pci_hole_end, 165 NULL, NULL, NULL, NULL); 166 167 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 168 q35_host_get_pci_hole64_start, 169 NULL, NULL, NULL, NULL); 170 171 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 172 q35_host_get_pci_hole64_end, 173 NULL, NULL, NULL, NULL); 174 175 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 176 q35_host_get_mmcfg_size, 177 NULL, NULL, NULL, NULL); 178 179 /* Leave enough space for the biggest MCFG BAR */ 180 /* TODO: this matches current bios behaviour, but 181 * it's not a power of two, which means an MTRR 182 * can't cover it exactly. 183 */ 184 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 185 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 186 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 187 } 188 189 static const TypeInfo q35_host_info = { 190 .name = TYPE_Q35_HOST_DEVICE, 191 .parent = TYPE_PCIE_HOST_BRIDGE, 192 .instance_size = sizeof(Q35PCIHost), 193 .instance_init = q35_host_initfn, 194 .class_init = q35_host_class_init, 195 }; 196 197 /**************************************************************************** 198 * MCH D0:F0 199 */ 200 201 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 202 { 203 return 0xffffffff; 204 } 205 206 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 207 unsigned width) 208 { 209 /* nothing */ 210 } 211 212 static const MemoryRegionOps tseg_blackhole_ops = { 213 .read = tseg_blackhole_read, 214 .write = tseg_blackhole_write, 215 .endianness = DEVICE_NATIVE_ENDIAN, 216 .valid.min_access_size = 1, 217 .valid.max_access_size = 4, 218 .impl.min_access_size = 4, 219 .impl.max_access_size = 4, 220 .endianness = DEVICE_LITTLE_ENDIAN, 221 }; 222 223 /* PCIe MMCFG */ 224 static void mch_update_pciexbar(MCHPCIState *mch) 225 { 226 PCIDevice *pci_dev = PCI_DEVICE(mch); 227 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 228 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 229 230 uint64_t pciexbar; 231 int enable; 232 uint64_t addr; 233 uint64_t addr_mask; 234 uint32_t length; 235 236 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 237 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 238 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 239 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 240 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 241 length = 256 * 1024 * 1024; 242 break; 243 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 244 length = 128 * 1024 * 1024; 245 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 246 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 247 break; 248 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 249 length = 64 * 1024 * 1024; 250 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 251 break; 252 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 253 default: 254 enable = 0; 255 length = 0; 256 abort(); 257 break; 258 } 259 addr = pciexbar & addr_mask; 260 pcie_host_mmcfg_update(pehb, enable, addr, length); 261 /* Leave enough space for the MCFG BAR */ 262 /* 263 * TODO: this matches current bios behaviour, but it's not a power of two, 264 * which means an MTRR can't cover it exactly. 265 */ 266 if (enable) { 267 mch->pci_info.w32.begin = addr + length; 268 } else { 269 mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 270 } 271 } 272 273 /* PAM */ 274 static void mch_update_pam(MCHPCIState *mch) 275 { 276 PCIDevice *pd = PCI_DEVICE(mch); 277 int i; 278 279 memory_region_transaction_begin(); 280 for (i = 0; i < 13; i++) { 281 pam_update(&mch->pam_regions[i], i, 282 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 283 } 284 memory_region_transaction_commit(); 285 } 286 287 /* SMRAM */ 288 static void mch_update_smram(MCHPCIState *mch) 289 { 290 PCIDevice *pd = PCI_DEVICE(mch); 291 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 292 uint32_t tseg_size; 293 294 /* implement SMRAM.D_LCK */ 295 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 296 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 297 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 298 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 299 } 300 301 memory_region_transaction_begin(); 302 303 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 304 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 305 memory_region_set_enabled(&mch->smram_region, h_smrame); 306 /* Show high SMRAM if H_SMRAME = 1 */ 307 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 308 } else { 309 /* Hide high SMRAM and low SMRAM */ 310 memory_region_set_enabled(&mch->smram_region, true); 311 memory_region_set_enabled(&mch->open_high_smram, false); 312 } 313 314 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 315 memory_region_set_enabled(&mch->low_smram, !h_smrame); 316 memory_region_set_enabled(&mch->high_smram, h_smrame); 317 } else { 318 memory_region_set_enabled(&mch->low_smram, false); 319 memory_region_set_enabled(&mch->high_smram, false); 320 } 321 322 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 323 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 324 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 325 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 326 tseg_size = 1024 * 1024; 327 break; 328 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 329 tseg_size = 1024 * 1024 * 2; 330 break; 331 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 332 tseg_size = 1024 * 1024 * 8; 333 break; 334 default: 335 tseg_size = 0; 336 break; 337 } 338 } else { 339 tseg_size = 0; 340 } 341 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 342 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 343 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 344 memory_region_add_subregion_overlap(mch->system_memory, 345 mch->below_4g_mem_size - tseg_size, 346 &mch->tseg_blackhole, 1); 347 348 memory_region_set_enabled(&mch->tseg_window, tseg_size); 349 memory_region_set_size(&mch->tseg_window, tseg_size); 350 memory_region_set_address(&mch->tseg_window, 351 mch->below_4g_mem_size - tseg_size); 352 memory_region_set_alias_offset(&mch->tseg_window, 353 mch->below_4g_mem_size - tseg_size); 354 355 memory_region_transaction_commit(); 356 } 357 358 static void mch_write_config(PCIDevice *d, 359 uint32_t address, uint32_t val, int len) 360 { 361 MCHPCIState *mch = MCH_PCI_DEVICE(d); 362 363 pci_default_write_config(d, address, val, len); 364 365 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 366 MCH_HOST_BRIDGE_PAM_SIZE)) { 367 mch_update_pam(mch); 368 } 369 370 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 371 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 372 mch_update_pciexbar(mch); 373 } 374 375 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 376 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 377 mch_update_smram(mch); 378 } 379 } 380 381 static void mch_update(MCHPCIState *mch) 382 { 383 mch_update_pciexbar(mch); 384 mch_update_pam(mch); 385 mch_update_smram(mch); 386 } 387 388 static int mch_post_load(void *opaque, int version_id) 389 { 390 MCHPCIState *mch = opaque; 391 mch_update(mch); 392 return 0; 393 } 394 395 static const VMStateDescription vmstate_mch = { 396 .name = "mch", 397 .version_id = 1, 398 .minimum_version_id = 1, 399 .post_load = mch_post_load, 400 .fields = (VMStateField[]) { 401 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 402 /* Used to be smm_enabled, which was basically always zero because 403 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 404 */ 405 VMSTATE_UNUSED(1), 406 VMSTATE_END_OF_LIST() 407 } 408 }; 409 410 static void mch_reset(DeviceState *qdev) 411 { 412 PCIDevice *d = PCI_DEVICE(qdev); 413 MCHPCIState *mch = MCH_PCI_DEVICE(d); 414 415 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 416 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 417 418 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 419 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 420 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 421 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 422 423 mch_update(mch); 424 } 425 426 static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 427 { 428 IntelIOMMUState *s = opaque; 429 VTDAddressSpace *vtd_as; 430 431 assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX); 432 433 vtd_as = vtd_find_add_as(s, bus, devfn); 434 return &vtd_as->as; 435 } 436 437 static void mch_init_dmar(MCHPCIState *mch) 438 { 439 PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); 440 441 mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE)); 442 object_property_add_child(OBJECT(mch), "intel-iommu", 443 OBJECT(mch->iommu), NULL); 444 qdev_init_nofail(DEVICE(mch->iommu)); 445 sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 446 447 pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); 448 } 449 450 static void mch_realize(PCIDevice *d, Error **errp) 451 { 452 int i; 453 MCHPCIState *mch = MCH_PCI_DEVICE(d); 454 455 /* setup pci memory mapping */ 456 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 457 mch->pci_address_space); 458 459 /* if *disabled* show SMRAM to all CPUs */ 460 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 461 mch->pci_address_space, 0xa0000, 0x20000); 462 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 463 &mch->smram_region, 1); 464 memory_region_set_enabled(&mch->smram_region, true); 465 466 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 467 mch->ram_memory, 0xa0000, 0x20000); 468 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 469 &mch->open_high_smram, 1); 470 memory_region_set_enabled(&mch->open_high_smram, false); 471 472 /* smram, as seen by SMM CPUs */ 473 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 474 memory_region_set_enabled(&mch->smram, true); 475 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 476 mch->ram_memory, 0xa0000, 0x20000); 477 memory_region_set_enabled(&mch->low_smram, true); 478 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 479 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 480 mch->ram_memory, 0xa0000, 0x20000); 481 memory_region_set_enabled(&mch->high_smram, true); 482 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 483 484 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 485 &tseg_blackhole_ops, NULL, 486 "tseg-blackhole", 0); 487 memory_region_set_enabled(&mch->tseg_blackhole, false); 488 memory_region_add_subregion_overlap(mch->system_memory, 489 mch->below_4g_mem_size, 490 &mch->tseg_blackhole, 1); 491 492 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 493 mch->ram_memory, mch->below_4g_mem_size, 0); 494 memory_region_set_enabled(&mch->tseg_window, false); 495 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 496 &mch->tseg_window); 497 object_property_add_const_link(qdev_get_machine(), "smram", 498 OBJECT(&mch->smram), &error_abort); 499 500 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 501 mch->pci_address_space, &mch->pam_regions[0], 502 PAM_BIOS_BASE, PAM_BIOS_SIZE); 503 for (i = 0; i < 12; ++i) { 504 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 505 mch->pci_address_space, &mch->pam_regions[i+1], 506 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 507 } 508 /* Intel IOMMU (VT-d) */ 509 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { 510 mch_init_dmar(mch); 511 } 512 } 513 514 uint64_t mch_mcfg_base(void) 515 { 516 bool ambiguous; 517 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 518 if (!o) { 519 return 0; 520 } 521 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 522 } 523 524 static void mch_class_init(ObjectClass *klass, void *data) 525 { 526 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 527 DeviceClass *dc = DEVICE_CLASS(klass); 528 529 k->realize = mch_realize; 530 k->config_write = mch_write_config; 531 dc->reset = mch_reset; 532 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 533 dc->desc = "Host bridge"; 534 dc->vmsd = &vmstate_mch; 535 k->vendor_id = PCI_VENDOR_ID_INTEL; 536 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 537 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 538 k->class_id = PCI_CLASS_BRIDGE_HOST; 539 /* 540 * PCI-facing part of the host bridge, not usable without the 541 * host-facing part, which can't be device_add'ed, yet. 542 */ 543 dc->cannot_instantiate_with_device_add_yet = true; 544 } 545 546 static const TypeInfo mch_info = { 547 .name = TYPE_MCH_PCI_DEVICE, 548 .parent = TYPE_PCI_DEVICE, 549 .instance_size = sizeof(MCHPCIState), 550 .class_init = mch_class_init, 551 }; 552 553 static void q35_register(void) 554 { 555 type_register_static(&mch_info); 556 type_register_static(&q35_host_info); 557 } 558 559 type_init(q35_register); 560