1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 41 42 static void q35_host_realize(DeviceState *dev, Error **errp) 43 { 44 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 45 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 46 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 47 48 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 49 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 50 51 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 52 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 53 54 /* register q35 0xcf8 port as coalesced pio */ 55 memory_region_set_flush_coalesced(&pci->data_mem); 56 memory_region_add_coalescing(&pci->conf_mem, 0, 4); 57 58 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 59 s->mch.pci_address_space, 60 s->mch.address_space_io, 61 0, TYPE_PCIE_BUS); 62 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 63 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 64 qdev_init_nofail(DEVICE(&s->mch)); 65 } 66 67 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 68 PCIBus *rootbus) 69 { 70 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 71 72 /* For backwards compat with old device paths */ 73 if (s->mch.short_root_bus) { 74 return "0000"; 75 } 76 return "0000:00"; 77 } 78 79 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 80 const char *name, void *opaque, 81 Error **errp) 82 { 83 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 84 uint64_t val64; 85 uint32_t value; 86 87 val64 = range_is_empty(&s->mch.pci_hole) 88 ? 0 : range_lob(&s->mch.pci_hole); 89 value = val64; 90 assert(value == val64); 91 visit_type_uint32(v, name, &value, errp); 92 } 93 94 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 95 const char *name, void *opaque, 96 Error **errp) 97 { 98 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 99 uint64_t val64; 100 uint32_t value; 101 102 val64 = range_is_empty(&s->mch.pci_hole) 103 ? 0 : range_upb(&s->mch.pci_hole) + 1; 104 value = val64; 105 assert(value == val64); 106 visit_type_uint32(v, name, &value, errp); 107 } 108 109 /* 110 * The 64bit PCI hole start is set by the Guest firmware 111 * as the address of the first 64bit PCI MEM resource. 112 * If no PCI device has resources on the 64bit area, 113 * the 64bit PCI hole will start after "over 4G RAM" and the 114 * reserved space for memory hotplug if any. 115 */ 116 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 117 const char *name, void *opaque, 118 Error **errp) 119 { 120 PCIHostState *h = PCI_HOST_BRIDGE(obj); 121 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 122 Range w64; 123 uint64_t value; 124 125 pci_bus_get_w64_range(h->bus, &w64); 126 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 127 if (!value && s->pci_hole64_fix) { 128 value = pc_pci_hole64_start(); 129 } 130 visit_type_uint64(v, name, &value, errp); 131 } 132 133 /* 134 * The 64bit PCI hole end is set by the Guest firmware 135 * as the address of the last 64bit PCI MEM resource. 136 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 137 * that can be configured by the user. 138 */ 139 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 140 const char *name, void *opaque, 141 Error **errp) 142 { 143 PCIHostState *h = PCI_HOST_BRIDGE(obj); 144 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 145 uint64_t hole64_start = pc_pci_hole64_start(); 146 Range w64; 147 uint64_t value, hole64_end; 148 149 pci_bus_get_w64_range(h->bus, &w64); 150 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 151 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 152 if (s->pci_hole64_fix && value < hole64_end) { 153 value = hole64_end; 154 } 155 visit_type_uint64(v, name, &value, errp); 156 } 157 158 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 159 void *opaque, Error **errp) 160 { 161 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 162 163 visit_type_uint64(v, name, &e->size, errp); 164 } 165 166 /* 167 * NOTE: setting defaults for the mch.* fields in this table 168 * doesn't work, because mch is a separate QOM object that is 169 * zeroed by the object_initialize(&s->mch, ...) call inside 170 * q35_host_initfn(). The default values for those 171 * properties need to be initialized manually by 172 * q35_host_initfn() after the object_initialize() call. 173 */ 174 static Property q35_host_props[] = { 175 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 176 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 177 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 178 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 179 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 180 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 181 mch.below_4g_mem_size, 0), 182 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 183 mch.above_4g_mem_size, 0), 184 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 185 DEFINE_PROP_END_OF_LIST(), 186 }; 187 188 static void q35_host_class_init(ObjectClass *klass, void *data) 189 { 190 DeviceClass *dc = DEVICE_CLASS(klass); 191 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 192 193 hc->root_bus_path = q35_host_root_bus_path; 194 dc->realize = q35_host_realize; 195 dc->props = q35_host_props; 196 /* Reason: needs to be wired up by pc_q35_init */ 197 dc->user_creatable = false; 198 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 199 dc->fw_name = "pci"; 200 } 201 202 static void q35_host_initfn(Object *obj) 203 { 204 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 205 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 206 207 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 208 "pci-conf-idx", 4); 209 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 210 "pci-conf-data", 4); 211 212 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 213 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 214 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 215 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 216 /* mch's object_initialize resets the default value, set it again */ 217 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 218 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 219 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 220 q35_host_get_pci_hole_start, 221 NULL, NULL, NULL, NULL); 222 223 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 224 q35_host_get_pci_hole_end, 225 NULL, NULL, NULL, NULL); 226 227 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 228 q35_host_get_pci_hole64_start, 229 NULL, NULL, NULL, NULL); 230 231 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 232 q35_host_get_pci_hole64_end, 233 NULL, NULL, NULL, NULL); 234 235 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 236 q35_host_get_mmcfg_size, 237 NULL, NULL, NULL, NULL); 238 239 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 240 (Object **) &s->mch.ram_memory, 241 qdev_prop_allow_set_link_before_realize, 0, NULL); 242 243 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 244 (Object **) &s->mch.pci_address_space, 245 qdev_prop_allow_set_link_before_realize, 0, NULL); 246 247 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 248 (Object **) &s->mch.system_memory, 249 qdev_prop_allow_set_link_before_realize, 0, NULL); 250 251 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 252 (Object **) &s->mch.address_space_io, 253 qdev_prop_allow_set_link_before_realize, 0, NULL); 254 255 /* Leave enough space for the biggest MCFG BAR */ 256 /* TODO: this matches current bios behaviour, but 257 * it's not a power of two, which means an MTRR 258 * can't cover it exactly. 259 */ 260 range_set_bounds(&s->mch.pci_hole, 261 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 262 IO_APIC_DEFAULT_ADDRESS - 1); 263 } 264 265 static const TypeInfo q35_host_info = { 266 .name = TYPE_Q35_HOST_DEVICE, 267 .parent = TYPE_PCIE_HOST_BRIDGE, 268 .instance_size = sizeof(Q35PCIHost), 269 .instance_init = q35_host_initfn, 270 .class_init = q35_host_class_init, 271 }; 272 273 /**************************************************************************** 274 * MCH D0:F0 275 */ 276 277 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 278 { 279 return 0xffffffff; 280 } 281 282 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 283 unsigned width) 284 { 285 /* nothing */ 286 } 287 288 static const MemoryRegionOps tseg_blackhole_ops = { 289 .read = tseg_blackhole_read, 290 .write = tseg_blackhole_write, 291 .endianness = DEVICE_NATIVE_ENDIAN, 292 .valid.min_access_size = 1, 293 .valid.max_access_size = 4, 294 .impl.min_access_size = 4, 295 .impl.max_access_size = 4, 296 .endianness = DEVICE_LITTLE_ENDIAN, 297 }; 298 299 /* PCIe MMCFG */ 300 static void mch_update_pciexbar(MCHPCIState *mch) 301 { 302 PCIDevice *pci_dev = PCI_DEVICE(mch); 303 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 304 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 305 306 uint64_t pciexbar; 307 int enable; 308 uint64_t addr; 309 uint64_t addr_mask; 310 uint32_t length; 311 312 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 313 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 314 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 315 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 316 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 317 length = 256 * 1024 * 1024; 318 break; 319 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 320 length = 128 * 1024 * 1024; 321 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 322 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 323 break; 324 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 325 length = 64 * 1024 * 1024; 326 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 327 break; 328 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 329 default: 330 abort(); 331 } 332 addr = pciexbar & addr_mask; 333 pcie_host_mmcfg_update(pehb, enable, addr, length); 334 /* Leave enough space for the MCFG BAR */ 335 /* 336 * TODO: this matches current bios behaviour, but it's not a power of two, 337 * which means an MTRR can't cover it exactly. 338 */ 339 if (enable) { 340 range_set_bounds(&mch->pci_hole, 341 addr + length, 342 IO_APIC_DEFAULT_ADDRESS - 1); 343 } else { 344 range_set_bounds(&mch->pci_hole, 345 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 346 IO_APIC_DEFAULT_ADDRESS - 1); 347 } 348 } 349 350 /* PAM */ 351 static void mch_update_pam(MCHPCIState *mch) 352 { 353 PCIDevice *pd = PCI_DEVICE(mch); 354 int i; 355 356 memory_region_transaction_begin(); 357 for (i = 0; i < 13; i++) { 358 pam_update(&mch->pam_regions[i], i, 359 pd->config[MCH_HOST_BRIDGE_PAM0 + (DIV_ROUND_UP(i, 2))]); 360 } 361 memory_region_transaction_commit(); 362 } 363 364 /* SMRAM */ 365 static void mch_update_smram(MCHPCIState *mch) 366 { 367 PCIDevice *pd = PCI_DEVICE(mch); 368 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 369 uint32_t tseg_size; 370 371 /* implement SMRAM.D_LCK */ 372 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 373 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 374 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 375 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 376 } 377 378 memory_region_transaction_begin(); 379 380 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 381 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 382 memory_region_set_enabled(&mch->smram_region, h_smrame); 383 /* Show high SMRAM if H_SMRAME = 1 */ 384 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 385 } else { 386 /* Hide high SMRAM and low SMRAM */ 387 memory_region_set_enabled(&mch->smram_region, true); 388 memory_region_set_enabled(&mch->open_high_smram, false); 389 } 390 391 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 392 memory_region_set_enabled(&mch->low_smram, !h_smrame); 393 memory_region_set_enabled(&mch->high_smram, h_smrame); 394 } else { 395 memory_region_set_enabled(&mch->low_smram, false); 396 memory_region_set_enabled(&mch->high_smram, false); 397 } 398 399 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 400 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 401 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 402 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 403 tseg_size = 1024 * 1024; 404 break; 405 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 406 tseg_size = 1024 * 1024 * 2; 407 break; 408 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 409 tseg_size = 1024 * 1024 * 8; 410 break; 411 default: 412 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 413 break; 414 } 415 } else { 416 tseg_size = 0; 417 } 418 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 419 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 420 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 421 memory_region_add_subregion_overlap(mch->system_memory, 422 mch->below_4g_mem_size - tseg_size, 423 &mch->tseg_blackhole, 1); 424 425 memory_region_set_enabled(&mch->tseg_window, tseg_size); 426 memory_region_set_size(&mch->tseg_window, tseg_size); 427 memory_region_set_address(&mch->tseg_window, 428 mch->below_4g_mem_size - tseg_size); 429 memory_region_set_alias_offset(&mch->tseg_window, 430 mch->below_4g_mem_size - tseg_size); 431 432 memory_region_transaction_commit(); 433 } 434 435 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 436 { 437 PCIDevice *pd = PCI_DEVICE(mch); 438 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 439 440 if (mch->ext_tseg_mbytes > 0 && 441 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 442 pci_set_word(reg, mch->ext_tseg_mbytes); 443 } 444 } 445 446 static void mch_write_config(PCIDevice *d, 447 uint32_t address, uint32_t val, int len) 448 { 449 MCHPCIState *mch = MCH_PCI_DEVICE(d); 450 451 pci_default_write_config(d, address, val, len); 452 453 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 454 MCH_HOST_BRIDGE_PAM_SIZE)) { 455 mch_update_pam(mch); 456 } 457 458 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 459 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 460 mch_update_pciexbar(mch); 461 } 462 463 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 464 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 465 mch_update_smram(mch); 466 } 467 468 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 469 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 470 mch_update_ext_tseg_mbytes(mch); 471 } 472 } 473 474 static void mch_update(MCHPCIState *mch) 475 { 476 mch_update_pciexbar(mch); 477 mch_update_pam(mch); 478 mch_update_smram(mch); 479 mch_update_ext_tseg_mbytes(mch); 480 } 481 482 static int mch_post_load(void *opaque, int version_id) 483 { 484 MCHPCIState *mch = opaque; 485 mch_update(mch); 486 return 0; 487 } 488 489 static const VMStateDescription vmstate_mch = { 490 .name = "mch", 491 .version_id = 1, 492 .minimum_version_id = 1, 493 .post_load = mch_post_load, 494 .fields = (VMStateField[]) { 495 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 496 /* Used to be smm_enabled, which was basically always zero because 497 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 498 */ 499 VMSTATE_UNUSED(1), 500 VMSTATE_END_OF_LIST() 501 } 502 }; 503 504 static void mch_reset(DeviceState *qdev) 505 { 506 PCIDevice *d = PCI_DEVICE(qdev); 507 MCHPCIState *mch = MCH_PCI_DEVICE(d); 508 509 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 510 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 511 512 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 513 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 514 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 515 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 516 517 if (mch->ext_tseg_mbytes > 0) { 518 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 519 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 520 } 521 522 mch_update(mch); 523 } 524 525 static void mch_realize(PCIDevice *d, Error **errp) 526 { 527 int i; 528 MCHPCIState *mch = MCH_PCI_DEVICE(d); 529 530 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 531 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 532 mch->ext_tseg_mbytes); 533 return; 534 } 535 536 /* setup pci memory mapping */ 537 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 538 mch->pci_address_space); 539 540 /* if *disabled* show SMRAM to all CPUs */ 541 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 542 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 543 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 544 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 545 &mch->smram_region, 1); 546 memory_region_set_enabled(&mch->smram_region, true); 547 548 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 549 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 550 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 551 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 552 &mch->open_high_smram, 1); 553 memory_region_set_enabled(&mch->open_high_smram, false); 554 555 /* smram, as seen by SMM CPUs */ 556 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 557 memory_region_set_enabled(&mch->smram, true); 558 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 559 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 560 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 561 memory_region_set_enabled(&mch->low_smram, true); 562 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 563 &mch->low_smram); 564 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 565 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 566 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 567 memory_region_set_enabled(&mch->high_smram, true); 568 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 569 570 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 571 &tseg_blackhole_ops, NULL, 572 "tseg-blackhole", 0); 573 memory_region_set_enabled(&mch->tseg_blackhole, false); 574 memory_region_add_subregion_overlap(mch->system_memory, 575 mch->below_4g_mem_size, 576 &mch->tseg_blackhole, 1); 577 578 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 579 mch->ram_memory, mch->below_4g_mem_size, 0); 580 memory_region_set_enabled(&mch->tseg_window, false); 581 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 582 &mch->tseg_window); 583 object_property_add_const_link(qdev_get_machine(), "smram", 584 OBJECT(&mch->smram), &error_abort); 585 586 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 587 mch->pci_address_space, &mch->pam_regions[0], 588 PAM_BIOS_BASE, PAM_BIOS_SIZE); 589 for (i = 0; i < 12; ++i) { 590 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 591 mch->pci_address_space, &mch->pam_regions[i+1], 592 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 593 } 594 } 595 596 uint64_t mch_mcfg_base(void) 597 { 598 bool ambiguous; 599 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 600 if (!o) { 601 return 0; 602 } 603 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 604 } 605 606 static Property mch_props[] = { 607 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 608 16), 609 DEFINE_PROP_END_OF_LIST(), 610 }; 611 612 static void mch_class_init(ObjectClass *klass, void *data) 613 { 614 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 615 DeviceClass *dc = DEVICE_CLASS(klass); 616 617 k->realize = mch_realize; 618 k->config_write = mch_write_config; 619 dc->reset = mch_reset; 620 dc->props = mch_props; 621 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 622 dc->desc = "Host bridge"; 623 dc->vmsd = &vmstate_mch; 624 k->vendor_id = PCI_VENDOR_ID_INTEL; 625 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 626 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 627 k->class_id = PCI_CLASS_BRIDGE_HOST; 628 /* 629 * PCI-facing part of the host bridge, not usable without the 630 * host-facing part, which can't be device_add'ed, yet. 631 */ 632 dc->user_creatable = false; 633 } 634 635 static const TypeInfo mch_info = { 636 .name = TYPE_MCH_PCI_DEVICE, 637 .parent = TYPE_PCI_DEVICE, 638 .instance_size = sizeof(MCHPCIState), 639 .class_init = mch_class_init, 640 .interfaces = (InterfaceInfo[]) { 641 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 642 { }, 643 }, 644 }; 645 646 static void q35_register(void) 647 { 648 type_register_static(&mch_info); 649 type_register_static(&q35_host_info); 650 } 651 652 type_init(q35_register); 653