1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 static void q35_host_realize(DeviceState *dev, Error **errp) 41 { 42 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 43 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 44 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 45 46 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 47 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 48 49 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51 52 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 53 s->mch.pci_address_space, s->mch.address_space_io, 54 0, TYPE_PCIE_BUS); 55 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 56 qdev_init_nofail(DEVICE(&s->mch)); 57 } 58 59 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 60 PCIBus *rootbus) 61 { 62 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 63 64 /* For backwards compat with old device paths */ 65 if (s->mch.short_root_bus) { 66 return "0000"; 67 } 68 return "0000:00"; 69 } 70 71 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 72 const char *name, void *opaque, 73 Error **errp) 74 { 75 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 76 uint32_t value = s->mch.pci_info.w32.begin; 77 78 visit_type_uint32(v, name, &value, errp); 79 } 80 81 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 82 const char *name, void *opaque, 83 Error **errp) 84 { 85 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 86 uint32_t value = s->mch.pci_info.w32.end; 87 88 visit_type_uint32(v, name, &value, errp); 89 } 90 91 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 92 const char *name, void *opaque, 93 Error **errp) 94 { 95 PCIHostState *h = PCI_HOST_BRIDGE(obj); 96 Range w64; 97 98 pci_bus_get_w64_range(h->bus, &w64); 99 100 visit_type_uint64(v, name, &w64.begin, errp); 101 } 102 103 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 104 const char *name, void *opaque, 105 Error **errp) 106 { 107 PCIHostState *h = PCI_HOST_BRIDGE(obj); 108 Range w64; 109 110 pci_bus_get_w64_range(h->bus, &w64); 111 112 visit_type_uint64(v, name, &w64.end, errp); 113 } 114 115 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 116 void *opaque, Error **errp) 117 { 118 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 119 uint32_t value = e->size; 120 121 visit_type_uint32(v, name, &value, errp); 122 } 123 124 static Property mch_props[] = { 125 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 126 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 127 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 128 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 129 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 130 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 131 mch.below_4g_mem_size, 0), 132 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 133 mch.above_4g_mem_size, 0), 134 DEFINE_PROP_END_OF_LIST(), 135 }; 136 137 static void q35_host_class_init(ObjectClass *klass, void *data) 138 { 139 DeviceClass *dc = DEVICE_CLASS(klass); 140 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 141 142 hc->root_bus_path = q35_host_root_bus_path; 143 dc->realize = q35_host_realize; 144 dc->props = mch_props; 145 /* Reason: needs to be wired up by pc_q35_init */ 146 dc->cannot_instantiate_with_device_add_yet = true; 147 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 148 dc->fw_name = "pci"; 149 } 150 151 static void q35_host_initfn(Object *obj) 152 { 153 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 154 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 155 156 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 157 "pci-conf-idx", 4); 158 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 159 "pci-conf-data", 4); 160 161 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 162 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 163 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 164 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 165 166 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 167 q35_host_get_pci_hole_start, 168 NULL, NULL, NULL, NULL); 169 170 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 171 q35_host_get_pci_hole_end, 172 NULL, NULL, NULL, NULL); 173 174 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 175 q35_host_get_pci_hole64_start, 176 NULL, NULL, NULL, NULL); 177 178 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 179 q35_host_get_pci_hole64_end, 180 NULL, NULL, NULL, NULL); 181 182 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 183 q35_host_get_mmcfg_size, 184 NULL, NULL, NULL, NULL); 185 186 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 187 (Object **) &s->mch.ram_memory, 188 qdev_prop_allow_set_link_before_realize, 0, NULL); 189 190 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 191 (Object **) &s->mch.pci_address_space, 192 qdev_prop_allow_set_link_before_realize, 0, NULL); 193 194 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 195 (Object **) &s->mch.system_memory, 196 qdev_prop_allow_set_link_before_realize, 0, NULL); 197 198 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 199 (Object **) &s->mch.address_space_io, 200 qdev_prop_allow_set_link_before_realize, 0, NULL); 201 202 /* Leave enough space for the biggest MCFG BAR */ 203 /* TODO: this matches current bios behaviour, but 204 * it's not a power of two, which means an MTRR 205 * can't cover it exactly. 206 */ 207 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 208 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 209 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 210 } 211 212 static const TypeInfo q35_host_info = { 213 .name = TYPE_Q35_HOST_DEVICE, 214 .parent = TYPE_PCIE_HOST_BRIDGE, 215 .instance_size = sizeof(Q35PCIHost), 216 .instance_init = q35_host_initfn, 217 .class_init = q35_host_class_init, 218 }; 219 220 /**************************************************************************** 221 * MCH D0:F0 222 */ 223 224 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 225 { 226 return 0xffffffff; 227 } 228 229 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 230 unsigned width) 231 { 232 /* nothing */ 233 } 234 235 static const MemoryRegionOps tseg_blackhole_ops = { 236 .read = tseg_blackhole_read, 237 .write = tseg_blackhole_write, 238 .endianness = DEVICE_NATIVE_ENDIAN, 239 .valid.min_access_size = 1, 240 .valid.max_access_size = 4, 241 .impl.min_access_size = 4, 242 .impl.max_access_size = 4, 243 .endianness = DEVICE_LITTLE_ENDIAN, 244 }; 245 246 /* PCIe MMCFG */ 247 static void mch_update_pciexbar(MCHPCIState *mch) 248 { 249 PCIDevice *pci_dev = PCI_DEVICE(mch); 250 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 251 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 252 253 uint64_t pciexbar; 254 int enable; 255 uint64_t addr; 256 uint64_t addr_mask; 257 uint32_t length; 258 259 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 260 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 261 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 262 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 263 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 264 length = 256 * 1024 * 1024; 265 break; 266 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 267 length = 128 * 1024 * 1024; 268 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 269 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 270 break; 271 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 272 length = 64 * 1024 * 1024; 273 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 274 break; 275 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 276 default: 277 enable = 0; 278 length = 0; 279 abort(); 280 break; 281 } 282 addr = pciexbar & addr_mask; 283 pcie_host_mmcfg_update(pehb, enable, addr, length); 284 /* Leave enough space for the MCFG BAR */ 285 /* 286 * TODO: this matches current bios behaviour, but it's not a power of two, 287 * which means an MTRR can't cover it exactly. 288 */ 289 if (enable) { 290 mch->pci_info.w32.begin = addr + length; 291 } else { 292 mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 293 } 294 } 295 296 /* PAM */ 297 static void mch_update_pam(MCHPCIState *mch) 298 { 299 PCIDevice *pd = PCI_DEVICE(mch); 300 int i; 301 302 memory_region_transaction_begin(); 303 for (i = 0; i < 13; i++) { 304 pam_update(&mch->pam_regions[i], i, 305 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 306 } 307 memory_region_transaction_commit(); 308 } 309 310 /* SMRAM */ 311 static void mch_update_smram(MCHPCIState *mch) 312 { 313 PCIDevice *pd = PCI_DEVICE(mch); 314 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 315 uint32_t tseg_size; 316 317 /* implement SMRAM.D_LCK */ 318 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 319 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 320 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 321 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 322 } 323 324 memory_region_transaction_begin(); 325 326 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 327 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 328 memory_region_set_enabled(&mch->smram_region, h_smrame); 329 /* Show high SMRAM if H_SMRAME = 1 */ 330 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 331 } else { 332 /* Hide high SMRAM and low SMRAM */ 333 memory_region_set_enabled(&mch->smram_region, true); 334 memory_region_set_enabled(&mch->open_high_smram, false); 335 } 336 337 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 338 memory_region_set_enabled(&mch->low_smram, !h_smrame); 339 memory_region_set_enabled(&mch->high_smram, h_smrame); 340 } else { 341 memory_region_set_enabled(&mch->low_smram, false); 342 memory_region_set_enabled(&mch->high_smram, false); 343 } 344 345 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 346 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 347 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 348 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 349 tseg_size = 1024 * 1024; 350 break; 351 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 352 tseg_size = 1024 * 1024 * 2; 353 break; 354 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 355 tseg_size = 1024 * 1024 * 8; 356 break; 357 default: 358 tseg_size = 0; 359 break; 360 } 361 } else { 362 tseg_size = 0; 363 } 364 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 365 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 366 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 367 memory_region_add_subregion_overlap(mch->system_memory, 368 mch->below_4g_mem_size - tseg_size, 369 &mch->tseg_blackhole, 1); 370 371 memory_region_set_enabled(&mch->tseg_window, tseg_size); 372 memory_region_set_size(&mch->tseg_window, tseg_size); 373 memory_region_set_address(&mch->tseg_window, 374 mch->below_4g_mem_size - tseg_size); 375 memory_region_set_alias_offset(&mch->tseg_window, 376 mch->below_4g_mem_size - tseg_size); 377 378 memory_region_transaction_commit(); 379 } 380 381 static void mch_write_config(PCIDevice *d, 382 uint32_t address, uint32_t val, int len) 383 { 384 MCHPCIState *mch = MCH_PCI_DEVICE(d); 385 386 pci_default_write_config(d, address, val, len); 387 388 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 389 MCH_HOST_BRIDGE_PAM_SIZE)) { 390 mch_update_pam(mch); 391 } 392 393 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 394 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 395 mch_update_pciexbar(mch); 396 } 397 398 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 399 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 400 mch_update_smram(mch); 401 } 402 } 403 404 static void mch_update(MCHPCIState *mch) 405 { 406 mch_update_pciexbar(mch); 407 mch_update_pam(mch); 408 mch_update_smram(mch); 409 } 410 411 static int mch_post_load(void *opaque, int version_id) 412 { 413 MCHPCIState *mch = opaque; 414 mch_update(mch); 415 return 0; 416 } 417 418 static const VMStateDescription vmstate_mch = { 419 .name = "mch", 420 .version_id = 1, 421 .minimum_version_id = 1, 422 .post_load = mch_post_load, 423 .fields = (VMStateField[]) { 424 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 425 /* Used to be smm_enabled, which was basically always zero because 426 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 427 */ 428 VMSTATE_UNUSED(1), 429 VMSTATE_END_OF_LIST() 430 } 431 }; 432 433 static void mch_reset(DeviceState *qdev) 434 { 435 PCIDevice *d = PCI_DEVICE(qdev); 436 MCHPCIState *mch = MCH_PCI_DEVICE(d); 437 438 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 439 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 440 441 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 442 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 443 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 444 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 445 446 mch_update(mch); 447 } 448 449 static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 450 { 451 IntelIOMMUState *s = opaque; 452 VTDAddressSpace *vtd_as; 453 454 assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX); 455 456 vtd_as = vtd_find_add_as(s, bus, devfn); 457 return &vtd_as->as; 458 } 459 460 static void mch_init_dmar(MCHPCIState *mch) 461 { 462 PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); 463 464 mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE)); 465 object_property_add_child(OBJECT(mch), "intel-iommu", 466 OBJECT(mch->iommu), NULL); 467 qdev_init_nofail(DEVICE(mch->iommu)); 468 sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 469 470 pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); 471 } 472 473 static void mch_realize(PCIDevice *d, Error **errp) 474 { 475 int i; 476 MCHPCIState *mch = MCH_PCI_DEVICE(d); 477 478 /* setup pci memory mapping */ 479 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 480 mch->pci_address_space); 481 482 /* if *disabled* show SMRAM to all CPUs */ 483 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 484 mch->pci_address_space, 0xa0000, 0x20000); 485 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 486 &mch->smram_region, 1); 487 memory_region_set_enabled(&mch->smram_region, true); 488 489 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 490 mch->ram_memory, 0xa0000, 0x20000); 491 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 492 &mch->open_high_smram, 1); 493 memory_region_set_enabled(&mch->open_high_smram, false); 494 495 /* smram, as seen by SMM CPUs */ 496 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 497 memory_region_set_enabled(&mch->smram, true); 498 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 499 mch->ram_memory, 0xa0000, 0x20000); 500 memory_region_set_enabled(&mch->low_smram, true); 501 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 502 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 503 mch->ram_memory, 0xa0000, 0x20000); 504 memory_region_set_enabled(&mch->high_smram, true); 505 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 506 507 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 508 &tseg_blackhole_ops, NULL, 509 "tseg-blackhole", 0); 510 memory_region_set_enabled(&mch->tseg_blackhole, false); 511 memory_region_add_subregion_overlap(mch->system_memory, 512 mch->below_4g_mem_size, 513 &mch->tseg_blackhole, 1); 514 515 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 516 mch->ram_memory, mch->below_4g_mem_size, 0); 517 memory_region_set_enabled(&mch->tseg_window, false); 518 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 519 &mch->tseg_window); 520 object_property_add_const_link(qdev_get_machine(), "smram", 521 OBJECT(&mch->smram), &error_abort); 522 523 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 524 mch->pci_address_space, &mch->pam_regions[0], 525 PAM_BIOS_BASE, PAM_BIOS_SIZE); 526 for (i = 0; i < 12; ++i) { 527 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 528 mch->pci_address_space, &mch->pam_regions[i+1], 529 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 530 } 531 /* Intel IOMMU (VT-d) */ 532 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { 533 mch_init_dmar(mch); 534 } 535 } 536 537 uint64_t mch_mcfg_base(void) 538 { 539 bool ambiguous; 540 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 541 if (!o) { 542 return 0; 543 } 544 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 545 } 546 547 static void mch_class_init(ObjectClass *klass, void *data) 548 { 549 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 550 DeviceClass *dc = DEVICE_CLASS(klass); 551 552 k->realize = mch_realize; 553 k->config_write = mch_write_config; 554 dc->reset = mch_reset; 555 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 556 dc->desc = "Host bridge"; 557 dc->vmsd = &vmstate_mch; 558 k->vendor_id = PCI_VENDOR_ID_INTEL; 559 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 560 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 561 k->class_id = PCI_CLASS_BRIDGE_HOST; 562 /* 563 * PCI-facing part of the host bridge, not usable without the 564 * host-facing part, which can't be device_add'ed, yet. 565 */ 566 dc->cannot_instantiate_with_device_add_yet = true; 567 } 568 569 static const TypeInfo mch_info = { 570 .name = TYPE_MCH_PCI_DEVICE, 571 .parent = TYPE_PCI_DEVICE, 572 .instance_size = sizeof(MCHPCIState), 573 .class_init = mch_class_init, 574 }; 575 576 static void q35_register(void) 577 { 578 type_register_static(&mch_info); 579 type_register_static(&q35_host_info); 580 } 581 582 type_init(q35_register); 583