1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "monitor/monitor.h" 38 #include "net/net.h" 39 #include "sysemu/numa.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "qapi/error.h" 50 #include "qapi/qapi-commands-pci.h" 51 #include "qemu/cutils.h" 52 53 //#define DEBUG_PCI 54 #ifdef DEBUG_PCI 55 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 56 #else 57 # define PCI_DPRINTF(format, ...) do { } while (0) 58 #endif 59 60 bool pci_available = true; 61 62 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 63 static char *pcibus_get_dev_path(DeviceState *dev); 64 static char *pcibus_get_fw_dev_path(DeviceState *dev); 65 static void pcibus_reset(BusState *qbus); 66 67 static Property pci_props[] = { 68 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 69 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 70 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), 71 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 72 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 75 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 77 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 79 failover_pair_id), 80 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 81 DEFINE_PROP_END_OF_LIST() 82 }; 83 84 static const VMStateDescription vmstate_pcibus = { 85 .name = "PCIBUS", 86 .version_id = 1, 87 .minimum_version_id = 1, 88 .fields = (VMStateField[]) { 89 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 90 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 91 nirq, 0, vmstate_info_int32, 92 int32_t), 93 VMSTATE_END_OF_LIST() 94 } 95 }; 96 97 static void pci_init_bus_master(PCIDevice *pci_dev) 98 { 99 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 100 101 memory_region_init_alias(&pci_dev->bus_master_enable_region, 102 OBJECT(pci_dev), "bus master", 103 dma_as->root, 0, memory_region_size(dma_as->root)); 104 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 105 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 106 &pci_dev->bus_master_enable_region); 107 } 108 109 static void pcibus_machine_done(Notifier *notifier, void *data) 110 { 111 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 115 if (bus->devices[i]) { 116 pci_init_bus_master(bus->devices[i]); 117 } 118 } 119 } 120 121 static void pci_bus_realize(BusState *qbus, Error **errp) 122 { 123 PCIBus *bus = PCI_BUS(qbus); 124 125 bus->machine_done.notify = pcibus_machine_done; 126 qemu_add_machine_init_done_notifier(&bus->machine_done); 127 128 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 129 } 130 131 static void pcie_bus_realize(BusState *qbus, Error **errp) 132 { 133 PCIBus *bus = PCI_BUS(qbus); 134 Error *local_err = NULL; 135 136 pci_bus_realize(qbus, &local_err); 137 if (local_err) { 138 error_propagate(errp, local_err); 139 return; 140 } 141 142 /* 143 * A PCI-E bus can support extended config space if it's the root 144 * bus, or if the bus/bridge above it does as well 145 */ 146 if (pci_bus_is_root(bus)) { 147 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 148 } else { 149 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 150 151 if (pci_bus_allows_extended_config_space(parent_bus)) { 152 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 153 } 154 } 155 } 156 157 static void pci_bus_unrealize(BusState *qbus) 158 { 159 PCIBus *bus = PCI_BUS(qbus); 160 161 qemu_remove_machine_init_done_notifier(&bus->machine_done); 162 163 vmstate_unregister(NULL, &vmstate_pcibus, bus); 164 } 165 166 static int pcibus_num(PCIBus *bus) 167 { 168 if (pci_bus_is_root(bus)) { 169 return 0; /* pci host bridge */ 170 } 171 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 172 } 173 174 static uint16_t pcibus_numa_node(PCIBus *bus) 175 { 176 return NUMA_NODE_UNASSIGNED; 177 } 178 179 static void pci_bus_class_init(ObjectClass *klass, void *data) 180 { 181 BusClass *k = BUS_CLASS(klass); 182 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 183 184 k->print_dev = pcibus_dev_print; 185 k->get_dev_path = pcibus_get_dev_path; 186 k->get_fw_dev_path = pcibus_get_fw_dev_path; 187 k->realize = pci_bus_realize; 188 k->unrealize = pci_bus_unrealize; 189 k->reset = pcibus_reset; 190 191 pbc->bus_num = pcibus_num; 192 pbc->numa_node = pcibus_numa_node; 193 } 194 195 static const TypeInfo pci_bus_info = { 196 .name = TYPE_PCI_BUS, 197 .parent = TYPE_BUS, 198 .instance_size = sizeof(PCIBus), 199 .class_size = sizeof(PCIBusClass), 200 .class_init = pci_bus_class_init, 201 }; 202 203 static const TypeInfo cxl_interface_info = { 204 .name = INTERFACE_CXL_DEVICE, 205 .parent = TYPE_INTERFACE, 206 }; 207 208 static const TypeInfo pcie_interface_info = { 209 .name = INTERFACE_PCIE_DEVICE, 210 .parent = TYPE_INTERFACE, 211 }; 212 213 static const TypeInfo conventional_pci_interface_info = { 214 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 215 .parent = TYPE_INTERFACE, 216 }; 217 218 static void pcie_bus_class_init(ObjectClass *klass, void *data) 219 { 220 BusClass *k = BUS_CLASS(klass); 221 222 k->realize = pcie_bus_realize; 223 } 224 225 static const TypeInfo pcie_bus_info = { 226 .name = TYPE_PCIE_BUS, 227 .parent = TYPE_PCI_BUS, 228 .class_init = pcie_bus_class_init, 229 }; 230 231 static const TypeInfo cxl_bus_info = { 232 .name = TYPE_CXL_BUS, 233 .parent = TYPE_PCIE_BUS, 234 .class_init = pcie_bus_class_init, 235 }; 236 237 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 238 static void pci_update_mappings(PCIDevice *d); 239 static void pci_irq_handler(void *opaque, int irq_num, int level); 240 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 241 static void pci_del_option_rom(PCIDevice *pdev); 242 243 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 244 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 245 246 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 247 248 int pci_bar(PCIDevice *d, int reg) 249 { 250 uint8_t type; 251 252 /* PCIe virtual functions do not have their own BARs */ 253 assert(!pci_is_vf(d)); 254 255 if (reg != PCI_ROM_SLOT) 256 return PCI_BASE_ADDRESS_0 + reg * 4; 257 258 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 259 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 260 } 261 262 static inline int pci_irq_state(PCIDevice *d, int irq_num) 263 { 264 return (d->irq_state >> irq_num) & 0x1; 265 } 266 267 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 268 { 269 d->irq_state &= ~(0x1 << irq_num); 270 d->irq_state |= level << irq_num; 271 } 272 273 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 274 { 275 assert(irq_num >= 0); 276 assert(irq_num < bus->nirq); 277 bus->irq_count[irq_num] += change; 278 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 279 } 280 281 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 282 { 283 PCIBus *bus; 284 for (;;) { 285 bus = pci_get_bus(pci_dev); 286 irq_num = bus->map_irq(pci_dev, irq_num); 287 if (bus->set_irq) 288 break; 289 pci_dev = bus->parent_dev; 290 } 291 pci_bus_change_irq_level(bus, irq_num, change); 292 } 293 294 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 295 { 296 assert(irq_num >= 0); 297 assert(irq_num < bus->nirq); 298 return !!bus->irq_count[irq_num]; 299 } 300 301 /* Update interrupt status bit in config space on interrupt 302 * state change. */ 303 static void pci_update_irq_status(PCIDevice *dev) 304 { 305 if (dev->irq_state) { 306 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 307 } else { 308 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 309 } 310 } 311 312 void pci_device_deassert_intx(PCIDevice *dev) 313 { 314 int i; 315 for (i = 0; i < PCI_NUM_PINS; ++i) { 316 pci_irq_handler(dev, i, 0); 317 } 318 } 319 320 static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) 321 { 322 MemTxAttrs attrs = {}; 323 324 attrs.requester_id = pci_requester_id(dev); 325 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, 326 attrs, NULL); 327 } 328 329 static void pci_reset_regions(PCIDevice *dev) 330 { 331 int r; 332 if (pci_is_vf(dev)) { 333 return; 334 } 335 336 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 337 PCIIORegion *region = &dev->io_regions[r]; 338 if (!region->size) { 339 continue; 340 } 341 342 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 343 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 344 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 345 } else { 346 pci_set_long(dev->config + pci_bar(dev, r), region->type); 347 } 348 } 349 } 350 351 static void pci_do_device_reset(PCIDevice *dev) 352 { 353 pci_device_deassert_intx(dev); 354 assert(dev->irq_state == 0); 355 356 /* Clear all writable bits */ 357 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 358 pci_get_word(dev->wmask + PCI_COMMAND) | 359 pci_get_word(dev->w1cmask + PCI_COMMAND)); 360 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 361 pci_get_word(dev->wmask + PCI_STATUS) | 362 pci_get_word(dev->w1cmask + PCI_STATUS)); 363 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 364 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 365 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 366 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 367 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 368 pci_reset_regions(dev); 369 pci_update_mappings(dev); 370 371 msi_reset(dev); 372 msix_reset(dev); 373 } 374 375 /* 376 * This function is called on #RST and FLR. 377 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 378 */ 379 void pci_device_reset(PCIDevice *dev) 380 { 381 device_cold_reset(&dev->qdev); 382 pci_do_device_reset(dev); 383 } 384 385 /* 386 * Trigger pci bus reset under a given bus. 387 * Called via bus_cold_reset on RST# assert, after the devices 388 * have been reset device_cold_reset-ed already. 389 */ 390 static void pcibus_reset(BusState *qbus) 391 { 392 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 393 int i; 394 395 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 396 if (bus->devices[i]) { 397 pci_do_device_reset(bus->devices[i]); 398 } 399 } 400 401 for (i = 0; i < bus->nirq; i++) { 402 assert(bus->irq_count[i] == 0); 403 } 404 } 405 406 static void pci_host_bus_register(DeviceState *host) 407 { 408 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 409 410 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 411 } 412 413 static void pci_host_bus_unregister(DeviceState *host) 414 { 415 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 416 417 QLIST_REMOVE(host_bridge, next); 418 } 419 420 PCIBus *pci_device_root_bus(const PCIDevice *d) 421 { 422 PCIBus *bus = pci_get_bus(d); 423 424 while (!pci_bus_is_root(bus)) { 425 d = bus->parent_dev; 426 assert(d != NULL); 427 428 bus = pci_get_bus(d); 429 } 430 431 return bus; 432 } 433 434 const char *pci_root_bus_path(PCIDevice *dev) 435 { 436 PCIBus *rootbus = pci_device_root_bus(dev); 437 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 438 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 439 440 assert(host_bridge->bus == rootbus); 441 442 if (hc->root_bus_path) { 443 return (*hc->root_bus_path)(host_bridge, rootbus); 444 } 445 446 return rootbus->qbus.name; 447 } 448 449 bool pci_bus_bypass_iommu(PCIBus *bus) 450 { 451 PCIBus *rootbus = bus; 452 PCIHostState *host_bridge; 453 454 if (!pci_bus_is_root(bus)) { 455 rootbus = pci_device_root_bus(bus->parent_dev); 456 } 457 458 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 459 460 assert(host_bridge->bus == rootbus); 461 462 return host_bridge->bypass_iommu; 463 } 464 465 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, 466 MemoryRegion *address_space_mem, 467 MemoryRegion *address_space_io, 468 uint8_t devfn_min) 469 { 470 assert(PCI_FUNC(devfn_min) == 0); 471 bus->devfn_min = devfn_min; 472 bus->slot_reserved_mask = 0x0; 473 bus->address_space_mem = address_space_mem; 474 bus->address_space_io = address_space_io; 475 bus->flags |= PCI_BUS_IS_ROOT; 476 477 /* host bridge */ 478 QLIST_INIT(&bus->child); 479 480 pci_host_bus_register(parent); 481 } 482 483 static void pci_bus_uninit(PCIBus *bus) 484 { 485 pci_host_bus_unregister(BUS(bus)->parent); 486 } 487 488 bool pci_bus_is_express(PCIBus *bus) 489 { 490 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 491 } 492 493 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 494 const char *name, 495 MemoryRegion *address_space_mem, 496 MemoryRegion *address_space_io, 497 uint8_t devfn_min, const char *typename) 498 { 499 qbus_init(bus, bus_size, typename, parent, name); 500 pci_root_bus_internal_init(bus, parent, address_space_mem, 501 address_space_io, devfn_min); 502 } 503 504 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 505 MemoryRegion *address_space_mem, 506 MemoryRegion *address_space_io, 507 uint8_t devfn_min, const char *typename) 508 { 509 PCIBus *bus; 510 511 bus = PCI_BUS(qbus_new(typename, parent, name)); 512 pci_root_bus_internal_init(bus, parent, address_space_mem, 513 address_space_io, devfn_min); 514 return bus; 515 } 516 517 void pci_root_bus_cleanup(PCIBus *bus) 518 { 519 pci_bus_uninit(bus); 520 /* the caller of the unplug hotplug handler will delete this device */ 521 qbus_unrealize(BUS(bus)); 522 } 523 524 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 525 void *irq_opaque, int nirq) 526 { 527 bus->set_irq = set_irq; 528 bus->map_irq = map_irq; 529 bus->irq_opaque = irq_opaque; 530 bus->nirq = nirq; 531 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 532 } 533 534 void pci_bus_irqs_cleanup(PCIBus *bus) 535 { 536 bus->set_irq = NULL; 537 bus->map_irq = NULL; 538 bus->irq_opaque = NULL; 539 bus->nirq = 0; 540 g_free(bus->irq_count); 541 } 542 543 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 544 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 545 void *irq_opaque, 546 MemoryRegion *address_space_mem, 547 MemoryRegion *address_space_io, 548 uint8_t devfn_min, int nirq, 549 const char *typename) 550 { 551 PCIBus *bus; 552 553 bus = pci_root_bus_new(parent, name, address_space_mem, 554 address_space_io, devfn_min, typename); 555 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 556 return bus; 557 } 558 559 void pci_unregister_root_bus(PCIBus *bus) 560 { 561 pci_bus_irqs_cleanup(bus); 562 pci_root_bus_cleanup(bus); 563 } 564 565 int pci_bus_num(PCIBus *s) 566 { 567 return PCI_BUS_GET_CLASS(s)->bus_num(s); 568 } 569 570 /* Returns the min and max bus numbers of a PCI bus hierarchy */ 571 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) 572 { 573 int i; 574 *min_bus = *max_bus = pci_bus_num(bus); 575 576 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 577 PCIDevice *dev = bus->devices[i]; 578 579 if (dev && IS_PCI_BRIDGE(dev)) { 580 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); 581 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); 582 } 583 } 584 } 585 586 int pci_bus_numa_node(PCIBus *bus) 587 { 588 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 589 } 590 591 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 592 const VMStateField *field) 593 { 594 PCIDevice *s = container_of(pv, PCIDevice, config); 595 uint8_t *config; 596 int i; 597 598 assert(size == pci_config_size(s)); 599 config = g_malloc(size); 600 601 qemu_get_buffer(f, config, size); 602 for (i = 0; i < size; ++i) { 603 if ((config[i] ^ s->config[i]) & 604 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 605 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 606 "cmask: %x wmask: %x w1cmask:%x", __func__, 607 i, config[i], s->config[i], 608 s->cmask[i], s->wmask[i], s->w1cmask[i]); 609 g_free(config); 610 return -EINVAL; 611 } 612 } 613 memcpy(s->config, config, size); 614 615 pci_update_mappings(s); 616 if (IS_PCI_BRIDGE(s)) { 617 pci_bridge_update_mappings(PCI_BRIDGE(s)); 618 } 619 620 memory_region_set_enabled(&s->bus_master_enable_region, 621 pci_get_word(s->config + PCI_COMMAND) 622 & PCI_COMMAND_MASTER); 623 624 g_free(config); 625 return 0; 626 } 627 628 /* just put buffer */ 629 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 630 const VMStateField *field, JSONWriter *vmdesc) 631 { 632 const uint8_t **v = pv; 633 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 634 qemu_put_buffer(f, *v, size); 635 636 return 0; 637 } 638 639 static VMStateInfo vmstate_info_pci_config = { 640 .name = "pci config", 641 .get = get_pci_config_device, 642 .put = put_pci_config_device, 643 }; 644 645 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 646 const VMStateField *field) 647 { 648 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 649 uint32_t irq_state[PCI_NUM_PINS]; 650 int i; 651 for (i = 0; i < PCI_NUM_PINS; ++i) { 652 irq_state[i] = qemu_get_be32(f); 653 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 654 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 655 irq_state[i]); 656 return -EINVAL; 657 } 658 } 659 660 for (i = 0; i < PCI_NUM_PINS; ++i) { 661 pci_set_irq_state(s, i, irq_state[i]); 662 } 663 664 return 0; 665 } 666 667 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 668 const VMStateField *field, JSONWriter *vmdesc) 669 { 670 int i; 671 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 672 673 for (i = 0; i < PCI_NUM_PINS; ++i) { 674 qemu_put_be32(f, pci_irq_state(s, i)); 675 } 676 677 return 0; 678 } 679 680 static VMStateInfo vmstate_info_pci_irq_state = { 681 .name = "pci irq state", 682 .get = get_pci_irq_state, 683 .put = put_pci_irq_state, 684 }; 685 686 static bool migrate_is_pcie(void *opaque, int version_id) 687 { 688 return pci_is_express((PCIDevice *)opaque); 689 } 690 691 static bool migrate_is_not_pcie(void *opaque, int version_id) 692 { 693 return !pci_is_express((PCIDevice *)opaque); 694 } 695 696 const VMStateDescription vmstate_pci_device = { 697 .name = "PCIDevice", 698 .version_id = 2, 699 .minimum_version_id = 1, 700 .fields = (VMStateField[]) { 701 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 702 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 703 migrate_is_not_pcie, 704 0, vmstate_info_pci_config, 705 PCI_CONFIG_SPACE_SIZE), 706 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 707 migrate_is_pcie, 708 0, vmstate_info_pci_config, 709 PCIE_CONFIG_SPACE_SIZE), 710 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 711 vmstate_info_pci_irq_state, 712 PCI_NUM_PINS * sizeof(int32_t)), 713 VMSTATE_END_OF_LIST() 714 } 715 }; 716 717 718 void pci_device_save(PCIDevice *s, QEMUFile *f) 719 { 720 /* Clear interrupt status bit: it is implicit 721 * in irq_state which we are saving. 722 * This makes us compatible with old devices 723 * which never set or clear this bit. */ 724 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 725 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 726 /* Restore the interrupt status bit. */ 727 pci_update_irq_status(s); 728 } 729 730 int pci_device_load(PCIDevice *s, QEMUFile *f) 731 { 732 int ret; 733 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 734 /* Restore the interrupt status bit. */ 735 pci_update_irq_status(s); 736 return ret; 737 } 738 739 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 740 { 741 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 742 pci_default_sub_vendor_id); 743 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 744 pci_default_sub_device_id); 745 } 746 747 /* 748 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 749 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 750 */ 751 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 752 unsigned int *slotp, unsigned int *funcp) 753 { 754 const char *p; 755 char *e; 756 unsigned long val; 757 unsigned long dom = 0, bus = 0; 758 unsigned int slot = 0; 759 unsigned int func = 0; 760 761 p = addr; 762 val = strtoul(p, &e, 16); 763 if (e == p) 764 return -1; 765 if (*e == ':') { 766 bus = val; 767 p = e + 1; 768 val = strtoul(p, &e, 16); 769 if (e == p) 770 return -1; 771 if (*e == ':') { 772 dom = bus; 773 bus = val; 774 p = e + 1; 775 val = strtoul(p, &e, 16); 776 if (e == p) 777 return -1; 778 } 779 } 780 781 slot = val; 782 783 if (funcp != NULL) { 784 if (*e != '.') 785 return -1; 786 787 p = e + 1; 788 val = strtoul(p, &e, 16); 789 if (e == p) 790 return -1; 791 792 func = val; 793 } 794 795 /* if funcp == NULL func is 0 */ 796 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 797 return -1; 798 799 if (*e) 800 return -1; 801 802 *domp = dom; 803 *busp = bus; 804 *slotp = slot; 805 if (funcp != NULL) 806 *funcp = func; 807 return 0; 808 } 809 810 static void pci_init_cmask(PCIDevice *dev) 811 { 812 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 813 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 814 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 815 dev->cmask[PCI_REVISION_ID] = 0xff; 816 dev->cmask[PCI_CLASS_PROG] = 0xff; 817 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 818 dev->cmask[PCI_HEADER_TYPE] = 0xff; 819 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 820 } 821 822 static void pci_init_wmask(PCIDevice *dev) 823 { 824 int config_size = pci_config_size(dev); 825 826 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 827 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 828 pci_set_word(dev->wmask + PCI_COMMAND, 829 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 830 PCI_COMMAND_INTX_DISABLE); 831 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 832 833 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 834 config_size - PCI_CONFIG_HEADER_SIZE); 835 } 836 837 static void pci_init_w1cmask(PCIDevice *dev) 838 { 839 /* 840 * Note: It's okay to set w1cmask even for readonly bits as 841 * long as their value is hardwired to 0. 842 */ 843 pci_set_word(dev->w1cmask + PCI_STATUS, 844 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 845 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 846 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 847 } 848 849 static void pci_init_mask_bridge(PCIDevice *d) 850 { 851 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 852 PCI_SEC_LETENCY_TIMER */ 853 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 854 855 /* base and limit */ 856 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 857 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 858 pci_set_word(d->wmask + PCI_MEMORY_BASE, 859 PCI_MEMORY_RANGE_MASK & 0xffff); 860 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 861 PCI_MEMORY_RANGE_MASK & 0xffff); 862 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 863 PCI_PREF_RANGE_MASK & 0xffff); 864 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 865 PCI_PREF_RANGE_MASK & 0xffff); 866 867 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 868 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 869 870 /* Supported memory and i/o types */ 871 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 872 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 873 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 874 PCI_PREF_RANGE_TYPE_64); 875 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 876 PCI_PREF_RANGE_TYPE_64); 877 878 /* 879 * TODO: Bridges default to 10-bit VGA decoding but we currently only 880 * implement 16-bit decoding (no alias support). 881 */ 882 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 883 PCI_BRIDGE_CTL_PARITY | 884 PCI_BRIDGE_CTL_SERR | 885 PCI_BRIDGE_CTL_ISA | 886 PCI_BRIDGE_CTL_VGA | 887 PCI_BRIDGE_CTL_VGA_16BIT | 888 PCI_BRIDGE_CTL_MASTER_ABORT | 889 PCI_BRIDGE_CTL_BUS_RESET | 890 PCI_BRIDGE_CTL_FAST_BACK | 891 PCI_BRIDGE_CTL_DISCARD | 892 PCI_BRIDGE_CTL_SEC_DISCARD | 893 PCI_BRIDGE_CTL_DISCARD_SERR); 894 /* Below does not do anything as we never set this bit, put here for 895 * completeness. */ 896 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 897 PCI_BRIDGE_CTL_DISCARD_STATUS); 898 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 899 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 900 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 901 PCI_PREF_RANGE_TYPE_MASK); 902 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 903 PCI_PREF_RANGE_TYPE_MASK); 904 } 905 906 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 907 { 908 uint8_t slot = PCI_SLOT(dev->devfn); 909 uint8_t func; 910 911 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 912 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 913 } 914 915 /* 916 * With SR/IOV and ARI, a device at function 0 need not be a multifunction 917 * device, as it may just be a VF that ended up with function 0 in 918 * the legacy PCI interpretation. Avoid failing in such cases: 919 */ 920 if (pci_is_vf(dev) && 921 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 922 return; 923 } 924 925 /* 926 * multifunction bit is interpreted in two ways as follows. 927 * - all functions must set the bit to 1. 928 * Example: Intel X53 929 * - function 0 must set the bit, but the rest function (> 0) 930 * is allowed to leave the bit to 0. 931 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 932 * 933 * So OS (at least Linux) checks the bit of only function 0, 934 * and doesn't see the bit of function > 0. 935 * 936 * The below check allows both interpretation. 937 */ 938 if (PCI_FUNC(dev->devfn)) { 939 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 940 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 941 /* function 0 should set multifunction bit */ 942 error_setg(errp, "PCI: single function device can't be populated " 943 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 944 return; 945 } 946 return; 947 } 948 949 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 950 return; 951 } 952 /* function 0 indicates single function, so function > 0 must be NULL */ 953 for (func = 1; func < PCI_FUNC_MAX; ++func) { 954 if (bus->devices[PCI_DEVFN(slot, func)]) { 955 error_setg(errp, "PCI: %x.0 indicates single function, " 956 "but %x.%x is already populated.", 957 slot, slot, func); 958 return; 959 } 960 } 961 } 962 963 static void pci_config_alloc(PCIDevice *pci_dev) 964 { 965 int config_size = pci_config_size(pci_dev); 966 967 pci_dev->config = g_malloc0(config_size); 968 pci_dev->cmask = g_malloc0(config_size); 969 pci_dev->wmask = g_malloc0(config_size); 970 pci_dev->w1cmask = g_malloc0(config_size); 971 pci_dev->used = g_malloc0(config_size); 972 } 973 974 static void pci_config_free(PCIDevice *pci_dev) 975 { 976 g_free(pci_dev->config); 977 g_free(pci_dev->cmask); 978 g_free(pci_dev->wmask); 979 g_free(pci_dev->w1cmask); 980 g_free(pci_dev->used); 981 } 982 983 static void do_pci_unregister_device(PCIDevice *pci_dev) 984 { 985 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 986 pci_config_free(pci_dev); 987 988 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 989 memory_region_del_subregion(&pci_dev->bus_master_container_region, 990 &pci_dev->bus_master_enable_region); 991 } 992 address_space_destroy(&pci_dev->bus_master_as); 993 } 994 995 /* Extract PCIReqIDCache into BDF format */ 996 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 997 { 998 uint8_t bus_n; 999 uint16_t result; 1000 1001 switch (cache->type) { 1002 case PCI_REQ_ID_BDF: 1003 result = pci_get_bdf(cache->dev); 1004 break; 1005 case PCI_REQ_ID_SECONDARY_BUS: 1006 bus_n = pci_dev_bus_num(cache->dev); 1007 result = PCI_BUILD_BDF(bus_n, 0); 1008 break; 1009 default: 1010 error_report("Invalid PCI requester ID cache type: %d", 1011 cache->type); 1012 exit(1); 1013 break; 1014 } 1015 1016 return result; 1017 } 1018 1019 /* Parse bridges up to the root complex and return requester ID 1020 * cache for specific device. For full PCIe topology, the cache 1021 * result would be exactly the same as getting BDF of the device. 1022 * However, several tricks are required when system mixed up with 1023 * legacy PCI devices and PCIe-to-PCI bridges. 1024 * 1025 * Here we cache the proxy device (and type) not requester ID since 1026 * bus number might change from time to time. 1027 */ 1028 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 1029 { 1030 PCIDevice *parent; 1031 PCIReqIDCache cache = { 1032 .dev = dev, 1033 .type = PCI_REQ_ID_BDF, 1034 }; 1035 1036 while (!pci_bus_is_root(pci_get_bus(dev))) { 1037 /* We are under PCI/PCIe bridges */ 1038 parent = pci_get_bus(dev)->parent_dev; 1039 if (pci_is_express(parent)) { 1040 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 1041 /* When we pass through PCIe-to-PCI/PCIX bridges, we 1042 * override the requester ID using secondary bus 1043 * number of parent bridge with zeroed devfn 1044 * (pcie-to-pci bridge spec chap 2.3). */ 1045 cache.type = PCI_REQ_ID_SECONDARY_BUS; 1046 cache.dev = dev; 1047 } 1048 } else { 1049 /* Legacy PCI, override requester ID with the bridge's 1050 * BDF upstream. When the root complex connects to 1051 * legacy PCI devices (including buses), it can only 1052 * obtain requester ID info from directly attached 1053 * devices. If devices are attached under bridges, only 1054 * the requester ID of the bridge that is directly 1055 * attached to the root complex can be recognized. */ 1056 cache.type = PCI_REQ_ID_BDF; 1057 cache.dev = parent; 1058 } 1059 dev = parent; 1060 } 1061 1062 return cache; 1063 } 1064 1065 uint16_t pci_requester_id(PCIDevice *dev) 1066 { 1067 return pci_req_id_cache_extract(&dev->requester_id_cache); 1068 } 1069 1070 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1071 { 1072 return !(bus->devices[devfn]); 1073 } 1074 1075 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1076 { 1077 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1078 } 1079 1080 /* -1 for devfn means auto assign */ 1081 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1082 const char *name, int devfn, 1083 Error **errp) 1084 { 1085 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1086 PCIConfigReadFunc *config_read = pc->config_read; 1087 PCIConfigWriteFunc *config_write = pc->config_write; 1088 Error *local_err = NULL; 1089 DeviceState *dev = DEVICE(pci_dev); 1090 PCIBus *bus = pci_get_bus(pci_dev); 1091 bool is_bridge = IS_PCI_BRIDGE(pci_dev); 1092 1093 /* Only pci bridges can be attached to extra PCI root buses */ 1094 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { 1095 error_setg(errp, 1096 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1097 bus->parent_dev->name); 1098 return NULL; 1099 } 1100 1101 if (devfn < 0) { 1102 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1103 devfn += PCI_FUNC_MAX) { 1104 if (pci_bus_devfn_available(bus, devfn) && 1105 !pci_bus_devfn_reserved(bus, devfn)) { 1106 goto found; 1107 } 1108 } 1109 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1110 "or reserved", name); 1111 return NULL; 1112 found: ; 1113 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1114 error_setg(errp, "PCI: slot %d function %d not available for %s," 1115 " reserved", 1116 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1117 return NULL; 1118 } else if (!pci_bus_devfn_available(bus, devfn)) { 1119 error_setg(errp, "PCI: slot %d function %d not available for %s," 1120 " in use by %s,id=%s", 1121 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1122 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); 1123 return NULL; 1124 } else if (dev->hotplugged && 1125 !pci_is_vf(pci_dev) && 1126 pci_get_function_0(pci_dev)) { 1127 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1128 " new func %s cannot be exposed to guest.", 1129 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1130 pci_get_function_0(pci_dev)->name, 1131 name); 1132 1133 return NULL; 1134 } 1135 1136 pci_dev->devfn = devfn; 1137 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1138 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1139 1140 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1141 "bus master container", UINT64_MAX); 1142 address_space_init(&pci_dev->bus_master_as, 1143 &pci_dev->bus_master_container_region, pci_dev->name); 1144 1145 if (phase_check(PHASE_MACHINE_READY)) { 1146 pci_init_bus_master(pci_dev); 1147 } 1148 pci_dev->irq_state = 0; 1149 pci_config_alloc(pci_dev); 1150 1151 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1152 pci_config_set_device_id(pci_dev->config, pc->device_id); 1153 pci_config_set_revision(pci_dev->config, pc->revision); 1154 pci_config_set_class(pci_dev->config, pc->class_id); 1155 1156 if (!is_bridge) { 1157 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1158 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1159 pc->subsystem_vendor_id); 1160 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1161 pc->subsystem_id); 1162 } else { 1163 pci_set_default_subsystem_id(pci_dev); 1164 } 1165 } else { 1166 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1167 assert(!pc->subsystem_vendor_id); 1168 assert(!pc->subsystem_id); 1169 } 1170 pci_init_cmask(pci_dev); 1171 pci_init_wmask(pci_dev); 1172 pci_init_w1cmask(pci_dev); 1173 if (is_bridge) { 1174 pci_init_mask_bridge(pci_dev); 1175 } 1176 pci_init_multifunction(bus, pci_dev, &local_err); 1177 if (local_err) { 1178 error_propagate(errp, local_err); 1179 do_pci_unregister_device(pci_dev); 1180 return NULL; 1181 } 1182 1183 if (!config_read) 1184 config_read = pci_default_read_config; 1185 if (!config_write) 1186 config_write = pci_default_write_config; 1187 pci_dev->config_read = config_read; 1188 pci_dev->config_write = config_write; 1189 bus->devices[devfn] = pci_dev; 1190 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1191 return pci_dev; 1192 } 1193 1194 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1195 { 1196 PCIIORegion *r; 1197 int i; 1198 1199 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1200 r = &pci_dev->io_regions[i]; 1201 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1202 continue; 1203 memory_region_del_subregion(r->address_space, r->memory); 1204 } 1205 1206 pci_unregister_vga(pci_dev); 1207 } 1208 1209 static void pci_qdev_unrealize(DeviceState *dev) 1210 { 1211 PCIDevice *pci_dev = PCI_DEVICE(dev); 1212 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1213 1214 pci_unregister_io_regions(pci_dev); 1215 pci_del_option_rom(pci_dev); 1216 1217 if (pc->exit) { 1218 pc->exit(pci_dev); 1219 } 1220 1221 pci_device_deassert_intx(pci_dev); 1222 do_pci_unregister_device(pci_dev); 1223 1224 pci_dev->msi_trigger = NULL; 1225 } 1226 1227 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1228 uint8_t type, MemoryRegion *memory) 1229 { 1230 PCIIORegion *r; 1231 uint32_t addr; /* offset in pci config space */ 1232 uint64_t wmask; 1233 pcibus_t size = memory_region_size(memory); 1234 uint8_t hdr_type; 1235 1236 assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ 1237 assert(region_num >= 0); 1238 assert(region_num < PCI_NUM_REGIONS); 1239 assert(is_power_of_2(size)); 1240 1241 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1242 hdr_type = 1243 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1244 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1245 1246 r = &pci_dev->io_regions[region_num]; 1247 r->addr = PCI_BAR_UNMAPPED; 1248 r->size = size; 1249 r->type = type; 1250 r->memory = memory; 1251 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1252 ? pci_get_bus(pci_dev)->address_space_io 1253 : pci_get_bus(pci_dev)->address_space_mem; 1254 1255 wmask = ~(size - 1); 1256 if (region_num == PCI_ROM_SLOT) { 1257 /* ROM enable bit is writable */ 1258 wmask |= PCI_ROM_ADDRESS_ENABLE; 1259 } 1260 1261 addr = pci_bar(pci_dev, region_num); 1262 pci_set_long(pci_dev->config + addr, type); 1263 1264 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1265 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1266 pci_set_quad(pci_dev->wmask + addr, wmask); 1267 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1268 } else { 1269 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1270 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1271 } 1272 } 1273 1274 static void pci_update_vga(PCIDevice *pci_dev) 1275 { 1276 uint16_t cmd; 1277 1278 if (!pci_dev->has_vga) { 1279 return; 1280 } 1281 1282 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1283 1284 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1285 cmd & PCI_COMMAND_MEMORY); 1286 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1287 cmd & PCI_COMMAND_IO); 1288 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1289 cmd & PCI_COMMAND_IO); 1290 } 1291 1292 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1293 MemoryRegion *io_lo, MemoryRegion *io_hi) 1294 { 1295 PCIBus *bus = pci_get_bus(pci_dev); 1296 1297 assert(!pci_dev->has_vga); 1298 1299 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1300 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1301 memory_region_add_subregion_overlap(bus->address_space_mem, 1302 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1303 1304 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1305 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1306 memory_region_add_subregion_overlap(bus->address_space_io, 1307 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1308 1309 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1310 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1311 memory_region_add_subregion_overlap(bus->address_space_io, 1312 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1313 pci_dev->has_vga = true; 1314 1315 pci_update_vga(pci_dev); 1316 } 1317 1318 void pci_unregister_vga(PCIDevice *pci_dev) 1319 { 1320 PCIBus *bus = pci_get_bus(pci_dev); 1321 1322 if (!pci_dev->has_vga) { 1323 return; 1324 } 1325 1326 memory_region_del_subregion(bus->address_space_mem, 1327 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1328 memory_region_del_subregion(bus->address_space_io, 1329 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1330 memory_region_del_subregion(bus->address_space_io, 1331 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1332 pci_dev->has_vga = false; 1333 } 1334 1335 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1336 { 1337 return pci_dev->io_regions[region_num].addr; 1338 } 1339 1340 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, 1341 uint8_t type, pcibus_t size) 1342 { 1343 pcibus_t new_addr; 1344 if (!pci_is_vf(d)) { 1345 int bar = pci_bar(d, reg); 1346 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1347 new_addr = pci_get_quad(d->config + bar); 1348 } else { 1349 new_addr = pci_get_long(d->config + bar); 1350 } 1351 } else { 1352 PCIDevice *pf = d->exp.sriov_vf.pf; 1353 uint16_t sriov_cap = pf->exp.sriov_cap; 1354 int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; 1355 uint16_t vf_offset = 1356 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); 1357 uint16_t vf_stride = 1358 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); 1359 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; 1360 1361 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1362 new_addr = pci_get_quad(pf->config + bar); 1363 } else { 1364 new_addr = pci_get_long(pf->config + bar); 1365 } 1366 new_addr += vf_num * size; 1367 } 1368 /* The ROM slot has a specific enable bit, keep it intact */ 1369 if (reg != PCI_ROM_SLOT) { 1370 new_addr &= ~(size - 1); 1371 } 1372 return new_addr; 1373 } 1374 1375 pcibus_t pci_bar_address(PCIDevice *d, 1376 int reg, uint8_t type, pcibus_t size) 1377 { 1378 pcibus_t new_addr, last_addr; 1379 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1380 Object *machine = qdev_get_machine(); 1381 ObjectClass *oc = object_get_class(machine); 1382 MachineClass *mc = MACHINE_CLASS(oc); 1383 bool allow_0_address = mc->pci_allow_0_address; 1384 1385 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1386 if (!(cmd & PCI_COMMAND_IO)) { 1387 return PCI_BAR_UNMAPPED; 1388 } 1389 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1390 last_addr = new_addr + size - 1; 1391 /* Check if 32 bit BAR wraps around explicitly. 1392 * TODO: make priorities correct and remove this work around. 1393 */ 1394 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1395 (!allow_0_address && new_addr == 0)) { 1396 return PCI_BAR_UNMAPPED; 1397 } 1398 return new_addr; 1399 } 1400 1401 if (!(cmd & PCI_COMMAND_MEMORY)) { 1402 return PCI_BAR_UNMAPPED; 1403 } 1404 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1405 /* the ROM slot has a specific enable bit */ 1406 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1407 return PCI_BAR_UNMAPPED; 1408 } 1409 new_addr &= ~(size - 1); 1410 last_addr = new_addr + size - 1; 1411 /* NOTE: we do not support wrapping */ 1412 /* XXX: as we cannot support really dynamic 1413 mappings, we handle specific values as invalid 1414 mappings. */ 1415 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1416 (!allow_0_address && new_addr == 0)) { 1417 return PCI_BAR_UNMAPPED; 1418 } 1419 1420 /* Now pcibus_t is 64bit. 1421 * Check if 32 bit BAR wraps around explicitly. 1422 * Without this, PC ide doesn't work well. 1423 * TODO: remove this work around. 1424 */ 1425 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1426 return PCI_BAR_UNMAPPED; 1427 } 1428 1429 /* 1430 * OS is allowed to set BAR beyond its addressable 1431 * bits. For example, 32 bit OS can set 64bit bar 1432 * to >4G. Check it. TODO: we might need to support 1433 * it in the future for e.g. PAE. 1434 */ 1435 if (last_addr >= HWADDR_MAX) { 1436 return PCI_BAR_UNMAPPED; 1437 } 1438 1439 return new_addr; 1440 } 1441 1442 static void pci_update_mappings(PCIDevice *d) 1443 { 1444 PCIIORegion *r; 1445 int i; 1446 pcibus_t new_addr; 1447 1448 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1449 r = &d->io_regions[i]; 1450 1451 /* this region isn't registered */ 1452 if (!r->size) 1453 continue; 1454 1455 new_addr = pci_bar_address(d, i, r->type, r->size); 1456 if (!d->has_power) { 1457 new_addr = PCI_BAR_UNMAPPED; 1458 } 1459 1460 /* This bar isn't changed */ 1461 if (new_addr == r->addr) 1462 continue; 1463 1464 /* now do the real mapping */ 1465 if (r->addr != PCI_BAR_UNMAPPED) { 1466 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), 1467 PCI_SLOT(d->devfn), 1468 PCI_FUNC(d->devfn), 1469 i, r->addr, r->size); 1470 memory_region_del_subregion(r->address_space, r->memory); 1471 } 1472 r->addr = new_addr; 1473 if (r->addr != PCI_BAR_UNMAPPED) { 1474 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), 1475 PCI_SLOT(d->devfn), 1476 PCI_FUNC(d->devfn), 1477 i, r->addr, r->size); 1478 memory_region_add_subregion_overlap(r->address_space, 1479 r->addr, r->memory, 1); 1480 } 1481 } 1482 1483 pci_update_vga(d); 1484 } 1485 1486 static inline int pci_irq_disabled(PCIDevice *d) 1487 { 1488 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1489 } 1490 1491 /* Called after interrupt disabled field update in config space, 1492 * assert/deassert interrupts if necessary. 1493 * Gets original interrupt disable bit value (before update). */ 1494 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1495 { 1496 int i, disabled = pci_irq_disabled(d); 1497 if (disabled == was_irq_disabled) 1498 return; 1499 for (i = 0; i < PCI_NUM_PINS; ++i) { 1500 int state = pci_irq_state(d, i); 1501 pci_change_irq_level(d, i, disabled ? -state : state); 1502 } 1503 } 1504 1505 uint32_t pci_default_read_config(PCIDevice *d, 1506 uint32_t address, int len) 1507 { 1508 uint32_t val = 0; 1509 1510 assert(address + len <= pci_config_size(d)); 1511 1512 if (pci_is_express_downstream_port(d) && 1513 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1514 pcie_sync_bridge_lnk(d); 1515 } 1516 memcpy(&val, d->config + address, len); 1517 return le32_to_cpu(val); 1518 } 1519 1520 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1521 { 1522 int i, was_irq_disabled = pci_irq_disabled(d); 1523 uint32_t val = val_in; 1524 1525 assert(addr + l <= pci_config_size(d)); 1526 1527 for (i = 0; i < l; val >>= 8, ++i) { 1528 uint8_t wmask = d->wmask[addr + i]; 1529 uint8_t w1cmask = d->w1cmask[addr + i]; 1530 assert(!(wmask & w1cmask)); 1531 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1532 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1533 } 1534 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1535 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1536 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1537 range_covers_byte(addr, l, PCI_COMMAND)) 1538 pci_update_mappings(d); 1539 1540 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1541 pci_update_irq_disabled(d, was_irq_disabled); 1542 memory_region_set_enabled(&d->bus_master_enable_region, 1543 (pci_get_word(d->config + PCI_COMMAND) 1544 & PCI_COMMAND_MASTER) && d->has_power); 1545 } 1546 1547 msi_write_config(d, addr, val_in, l); 1548 msix_write_config(d, addr, val_in, l); 1549 pcie_sriov_config_write(d, addr, val_in, l); 1550 } 1551 1552 /***********************************************************/ 1553 /* generic PCI irq support */ 1554 1555 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1556 static void pci_irq_handler(void *opaque, int irq_num, int level) 1557 { 1558 PCIDevice *pci_dev = opaque; 1559 int change; 1560 1561 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1562 assert(level == 0 || level == 1); 1563 change = level - pci_irq_state(pci_dev, irq_num); 1564 if (!change) 1565 return; 1566 1567 pci_set_irq_state(pci_dev, irq_num, level); 1568 pci_update_irq_status(pci_dev); 1569 if (pci_irq_disabled(pci_dev)) 1570 return; 1571 pci_change_irq_level(pci_dev, irq_num, change); 1572 } 1573 1574 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1575 { 1576 int intx = pci_intx(pci_dev); 1577 assert(0 <= intx && intx < PCI_NUM_PINS); 1578 1579 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1580 } 1581 1582 void pci_set_irq(PCIDevice *pci_dev, int level) 1583 { 1584 int intx = pci_intx(pci_dev); 1585 pci_irq_handler(pci_dev, intx, level); 1586 } 1587 1588 /* Special hooks used by device assignment */ 1589 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1590 { 1591 assert(pci_bus_is_root(bus)); 1592 bus->route_intx_to_irq = route_intx_to_irq; 1593 } 1594 1595 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1596 { 1597 PCIBus *bus; 1598 1599 do { 1600 bus = pci_get_bus(dev); 1601 pin = bus->map_irq(dev, pin); 1602 dev = bus->parent_dev; 1603 } while (dev); 1604 1605 if (!bus->route_intx_to_irq) { 1606 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1607 object_get_typename(OBJECT(bus->qbus.parent))); 1608 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1609 } 1610 1611 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1612 } 1613 1614 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1615 { 1616 return old->mode != new->mode || old->irq != new->irq; 1617 } 1618 1619 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1620 { 1621 PCIDevice *dev; 1622 PCIBus *sec; 1623 int i; 1624 1625 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1626 dev = bus->devices[i]; 1627 if (dev && dev->intx_routing_notifier) { 1628 dev->intx_routing_notifier(dev); 1629 } 1630 } 1631 1632 QLIST_FOREACH(sec, &bus->child, sibling) { 1633 pci_bus_fire_intx_routing_notifier(sec); 1634 } 1635 } 1636 1637 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1638 PCIINTxRoutingNotifier notifier) 1639 { 1640 dev->intx_routing_notifier = notifier; 1641 } 1642 1643 /* 1644 * PCI-to-PCI bridge specification 1645 * 9.1: Interrupt routing. Table 9-1 1646 * 1647 * the PCI Express Base Specification, Revision 2.1 1648 * 2.2.8.1: INTx interrutp signaling - Rules 1649 * the Implementation Note 1650 * Table 2-20 1651 */ 1652 /* 1653 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1654 * 0-origin unlike PCI interrupt pin register. 1655 */ 1656 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1657 { 1658 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1659 } 1660 1661 /***********************************************************/ 1662 /* monitor info on PCI */ 1663 1664 typedef struct { 1665 uint16_t class; 1666 const char *desc; 1667 const char *fw_name; 1668 uint16_t fw_ign_bits; 1669 } pci_class_desc; 1670 1671 static const pci_class_desc pci_class_descriptions[] = 1672 { 1673 { 0x0001, "VGA controller", "display"}, 1674 { 0x0100, "SCSI controller", "scsi"}, 1675 { 0x0101, "IDE controller", "ide"}, 1676 { 0x0102, "Floppy controller", "fdc"}, 1677 { 0x0103, "IPI controller", "ipi"}, 1678 { 0x0104, "RAID controller", "raid"}, 1679 { 0x0106, "SATA controller"}, 1680 { 0x0107, "SAS controller"}, 1681 { 0x0180, "Storage controller"}, 1682 { 0x0200, "Ethernet controller", "ethernet"}, 1683 { 0x0201, "Token Ring controller", "token-ring"}, 1684 { 0x0202, "FDDI controller", "fddi"}, 1685 { 0x0203, "ATM controller", "atm"}, 1686 { 0x0280, "Network controller"}, 1687 { 0x0300, "VGA controller", "display", 0x00ff}, 1688 { 0x0301, "XGA controller"}, 1689 { 0x0302, "3D controller"}, 1690 { 0x0380, "Display controller"}, 1691 { 0x0400, "Video controller", "video"}, 1692 { 0x0401, "Audio controller", "sound"}, 1693 { 0x0402, "Phone"}, 1694 { 0x0403, "Audio controller", "sound"}, 1695 { 0x0480, "Multimedia controller"}, 1696 { 0x0500, "RAM controller", "memory"}, 1697 { 0x0501, "Flash controller", "flash"}, 1698 { 0x0580, "Memory controller"}, 1699 { 0x0600, "Host bridge", "host"}, 1700 { 0x0601, "ISA bridge", "isa"}, 1701 { 0x0602, "EISA bridge", "eisa"}, 1702 { 0x0603, "MC bridge", "mca"}, 1703 { 0x0604, "PCI bridge", "pci-bridge"}, 1704 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1705 { 0x0606, "NUBUS bridge", "nubus"}, 1706 { 0x0607, "CARDBUS bridge", "cardbus"}, 1707 { 0x0608, "RACEWAY bridge"}, 1708 { 0x0680, "Bridge"}, 1709 { 0x0700, "Serial port", "serial"}, 1710 { 0x0701, "Parallel port", "parallel"}, 1711 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1712 { 0x0801, "DMA controller", "dma-controller"}, 1713 { 0x0802, "Timer", "timer"}, 1714 { 0x0803, "RTC", "rtc"}, 1715 { 0x0900, "Keyboard", "keyboard"}, 1716 { 0x0901, "Pen", "pen"}, 1717 { 0x0902, "Mouse", "mouse"}, 1718 { 0x0A00, "Dock station", "dock", 0x00ff}, 1719 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1720 { 0x0c00, "Firewire controller", "firewire"}, 1721 { 0x0c01, "Access bus controller", "access-bus"}, 1722 { 0x0c02, "SSA controller", "ssa"}, 1723 { 0x0c03, "USB controller", "usb"}, 1724 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1725 { 0x0c05, "SMBus"}, 1726 { 0, NULL} 1727 }; 1728 1729 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1730 pci_bus_dev_fn fn, 1731 void *opaque) 1732 { 1733 PCIDevice *d; 1734 int devfn; 1735 1736 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1737 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1738 if (d) { 1739 fn(bus, d, opaque); 1740 } 1741 } 1742 } 1743 1744 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1745 pci_bus_dev_fn fn, void *opaque) 1746 { 1747 bus = pci_find_bus_nr(bus, bus_num); 1748 1749 if (bus) { 1750 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1751 } 1752 } 1753 1754 void pci_for_each_device_under_bus(PCIBus *bus, 1755 pci_bus_dev_fn fn, void *opaque) 1756 { 1757 PCIDevice *d; 1758 int devfn; 1759 1760 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1761 d = bus->devices[devfn]; 1762 if (d) { 1763 fn(bus, d, opaque); 1764 } 1765 } 1766 } 1767 1768 void pci_for_each_device(PCIBus *bus, int bus_num, 1769 pci_bus_dev_fn fn, void *opaque) 1770 { 1771 bus = pci_find_bus_nr(bus, bus_num); 1772 1773 if (bus) { 1774 pci_for_each_device_under_bus(bus, fn, opaque); 1775 } 1776 } 1777 1778 static const pci_class_desc *get_class_desc(int class) 1779 { 1780 const pci_class_desc *desc; 1781 1782 desc = pci_class_descriptions; 1783 while (desc->desc && class != desc->class) { 1784 desc++; 1785 } 1786 1787 return desc; 1788 } 1789 1790 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1791 1792 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1793 { 1794 PciMemoryRegionList *head = NULL, **tail = &head; 1795 int i; 1796 1797 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1798 const PCIIORegion *r = &dev->io_regions[i]; 1799 PciMemoryRegion *region; 1800 1801 if (!r->size) { 1802 continue; 1803 } 1804 1805 region = g_malloc0(sizeof(*region)); 1806 1807 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1808 region->type = g_strdup("io"); 1809 } else { 1810 region->type = g_strdup("memory"); 1811 region->has_prefetch = true; 1812 region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1813 region->has_mem_type_64 = true; 1814 region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1815 } 1816 1817 region->bar = i; 1818 region->address = r->addr; 1819 region->size = r->size; 1820 1821 QAPI_LIST_APPEND(tail, region); 1822 } 1823 1824 return head; 1825 } 1826 1827 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1828 int bus_num) 1829 { 1830 PciBridgeInfo *info; 1831 PciMemoryRange *range; 1832 1833 info = g_new0(PciBridgeInfo, 1); 1834 1835 info->bus = g_new0(PciBusInfo, 1); 1836 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1837 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1838 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1839 1840 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1841 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1842 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1843 1844 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1845 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1846 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1847 1848 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1849 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1850 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1851 1852 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1853 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1854 if (child_bus) { 1855 info->has_devices = true; 1856 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1857 } 1858 } 1859 1860 return info; 1861 } 1862 1863 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1864 int bus_num) 1865 { 1866 const pci_class_desc *desc; 1867 PciDeviceInfo *info; 1868 uint8_t type; 1869 int class; 1870 1871 info = g_new0(PciDeviceInfo, 1); 1872 info->bus = bus_num; 1873 info->slot = PCI_SLOT(dev->devfn); 1874 info->function = PCI_FUNC(dev->devfn); 1875 1876 info->class_info = g_new0(PciDeviceClass, 1); 1877 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1878 info->class_info->q_class = class; 1879 desc = get_class_desc(class); 1880 if (desc->desc) { 1881 info->class_info->desc = g_strdup(desc->desc); 1882 } 1883 1884 info->id = g_new0(PciDeviceId, 1); 1885 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1886 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1887 info->regions = qmp_query_pci_regions(dev); 1888 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1889 1890 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1891 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1892 info->has_irq = true; 1893 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1894 } 1895 1896 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1897 if (type == PCI_HEADER_TYPE_BRIDGE) { 1898 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1899 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1900 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1901 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1902 info->id->subsystem_vendor = 1903 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1904 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1905 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1906 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1907 info->id->subsystem_vendor = 1908 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1909 } 1910 1911 return info; 1912 } 1913 1914 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1915 { 1916 PciDeviceInfoList *head = NULL, **tail = &head; 1917 PCIDevice *dev; 1918 int devfn; 1919 1920 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1921 dev = bus->devices[devfn]; 1922 if (dev) { 1923 QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num)); 1924 } 1925 } 1926 1927 return head; 1928 } 1929 1930 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1931 { 1932 PciInfo *info = NULL; 1933 1934 bus = pci_find_bus_nr(bus, bus_num); 1935 if (bus) { 1936 info = g_malloc0(sizeof(*info)); 1937 info->bus = bus_num; 1938 info->devices = qmp_query_pci_devices(bus, bus_num); 1939 } 1940 1941 return info; 1942 } 1943 1944 PciInfoList *qmp_query_pci(Error **errp) 1945 { 1946 PciInfoList *head = NULL, **tail = &head; 1947 PCIHostState *host_bridge; 1948 1949 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1950 QAPI_LIST_APPEND(tail, 1951 qmp_query_pci_bus(host_bridge->bus, 1952 pci_bus_num(host_bridge->bus))); 1953 } 1954 1955 return head; 1956 } 1957 1958 /* Initialize a PCI NIC. */ 1959 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1960 const char *default_model, 1961 const char *default_devaddr) 1962 { 1963 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1964 GSList *list; 1965 GPtrArray *pci_nic_models; 1966 PCIBus *bus; 1967 PCIDevice *pci_dev; 1968 DeviceState *dev; 1969 int devfn; 1970 int i; 1971 int dom, busnr; 1972 unsigned slot; 1973 1974 if (nd->model && !strcmp(nd->model, "virtio")) { 1975 g_free(nd->model); 1976 nd->model = g_strdup("virtio-net-pci"); 1977 } 1978 1979 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1980 pci_nic_models = g_ptr_array_new(); 1981 while (list) { 1982 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1983 TYPE_DEVICE); 1984 GSList *next; 1985 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1986 dc->user_creatable) { 1987 const char *name = object_class_get_name(list->data); 1988 /* 1989 * A network device might also be something else than a NIC, see 1990 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1991 * property, too. Unfortunately, some devices like virtio-net only 1992 * create this property during instance_init, so we have to create 1993 * a temporary instance here to be able to check it. 1994 */ 1995 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1996 if (object_property_find(obj, "netdev")) { 1997 g_ptr_array_add(pci_nic_models, (gpointer)name); 1998 } 1999 object_unref(obj); 2000 } 2001 next = list->next; 2002 g_slist_free_1(list); 2003 list = next; 2004 } 2005 g_ptr_array_add(pci_nic_models, NULL); 2006 2007 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 2008 exit(0); 2009 } 2010 2011 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 2012 default_model); 2013 if (i < 0) { 2014 exit(1); 2015 } 2016 2017 if (!rootbus) { 2018 error_report("No primary PCI bus"); 2019 exit(1); 2020 } 2021 2022 assert(!rootbus->parent_dev); 2023 2024 if (!devaddr) { 2025 devfn = -1; 2026 busnr = 0; 2027 } else { 2028 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 2029 error_report("Invalid PCI device address %s for device %s", 2030 devaddr, nd->model); 2031 exit(1); 2032 } 2033 2034 if (dom != 0) { 2035 error_report("No support for non-zero PCI domains"); 2036 exit(1); 2037 } 2038 2039 devfn = PCI_DEVFN(slot, 0); 2040 } 2041 2042 bus = pci_find_bus_nr(rootbus, busnr); 2043 if (!bus) { 2044 error_report("Invalid PCI device address %s for device %s", 2045 devaddr, nd->model); 2046 exit(1); 2047 } 2048 2049 pci_dev = pci_new(devfn, nd->model); 2050 dev = &pci_dev->qdev; 2051 qdev_set_nic_properties(dev, nd); 2052 pci_realize_and_unref(pci_dev, bus, &error_fatal); 2053 g_ptr_array_free(pci_nic_models, true); 2054 return pci_dev; 2055 } 2056 2057 PCIDevice *pci_vga_init(PCIBus *bus) 2058 { 2059 vga_interface_created = true; 2060 switch (vga_interface_type) { 2061 case VGA_CIRRUS: 2062 return pci_create_simple(bus, -1, "cirrus-vga"); 2063 case VGA_QXL: 2064 return pci_create_simple(bus, -1, "qxl-vga"); 2065 case VGA_STD: 2066 return pci_create_simple(bus, -1, "VGA"); 2067 case VGA_VMWARE: 2068 return pci_create_simple(bus, -1, "vmware-svga"); 2069 case VGA_VIRTIO: 2070 return pci_create_simple(bus, -1, "virtio-vga"); 2071 case VGA_NONE: 2072 default: /* Other non-PCI types. Checking for unsupported types is already 2073 done in vl.c. */ 2074 return NULL; 2075 } 2076 } 2077 2078 /* Whether a given bus number is in range of the secondary 2079 * bus of the given bridge device. */ 2080 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 2081 { 2082 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 2083 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 2084 dev->config[PCI_SECONDARY_BUS] <= bus_num && 2085 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 2086 } 2087 2088 /* Whether a given bus number is in a range of a root bus */ 2089 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 2090 { 2091 int i; 2092 2093 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 2094 PCIDevice *dev = bus->devices[i]; 2095 2096 if (dev && IS_PCI_BRIDGE(dev)) { 2097 if (pci_secondary_bus_in_range(dev, bus_num)) { 2098 return true; 2099 } 2100 } 2101 } 2102 2103 return false; 2104 } 2105 2106 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2107 { 2108 PCIBus *sec; 2109 2110 if (!bus) { 2111 return NULL; 2112 } 2113 2114 if (pci_bus_num(bus) == bus_num) { 2115 return bus; 2116 } 2117 2118 /* Consider all bus numbers in range for the host pci bridge. */ 2119 if (!pci_bus_is_root(bus) && 2120 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2121 return NULL; 2122 } 2123 2124 /* try child bus */ 2125 for (; bus; bus = sec) { 2126 QLIST_FOREACH(sec, &bus->child, sibling) { 2127 if (pci_bus_num(sec) == bus_num) { 2128 return sec; 2129 } 2130 /* PXB buses assumed to be children of bus 0 */ 2131 if (pci_bus_is_root(sec)) { 2132 if (pci_root_bus_in_range(sec, bus_num)) { 2133 break; 2134 } 2135 } else { 2136 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2137 break; 2138 } 2139 } 2140 } 2141 } 2142 2143 return NULL; 2144 } 2145 2146 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 2147 pci_bus_fn end, void *parent_state) 2148 { 2149 PCIBus *sec; 2150 void *state; 2151 2152 if (!bus) { 2153 return; 2154 } 2155 2156 if (begin) { 2157 state = begin(bus, parent_state); 2158 } else { 2159 state = parent_state; 2160 } 2161 2162 QLIST_FOREACH(sec, &bus->child, sibling) { 2163 pci_for_each_bus_depth_first(sec, begin, end, state); 2164 } 2165 2166 if (end) { 2167 end(bus, state); 2168 } 2169 } 2170 2171 2172 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2173 { 2174 bus = pci_find_bus_nr(bus, bus_num); 2175 2176 if (!bus) 2177 return NULL; 2178 2179 return bus->devices[devfn]; 2180 } 2181 2182 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2183 { 2184 PCIDevice *pci_dev = (PCIDevice *)qdev; 2185 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2186 ObjectClass *klass = OBJECT_CLASS(pc); 2187 Error *local_err = NULL; 2188 bool is_default_rom; 2189 uint16_t class_id; 2190 2191 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { 2192 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2193 return; 2194 } 2195 2196 /* initialize cap_present for pci_is_express() and pci_config_size(), 2197 * Note that hybrid PCIs are not set automatically and need to manage 2198 * QEMU_PCI_CAP_EXPRESS manually */ 2199 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2200 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2201 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2202 } 2203 2204 if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { 2205 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; 2206 } 2207 2208 pci_dev = do_pci_register_device(pci_dev, 2209 object_get_typename(OBJECT(qdev)), 2210 pci_dev->devfn, errp); 2211 if (pci_dev == NULL) 2212 return; 2213 2214 if (pc->realize) { 2215 pc->realize(pci_dev, &local_err); 2216 if (local_err) { 2217 error_propagate(errp, local_err); 2218 do_pci_unregister_device(pci_dev); 2219 return; 2220 } 2221 } 2222 2223 if (pci_dev->failover_pair_id) { 2224 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2225 error_setg(errp, "failover primary device must be on " 2226 "PCIExpress bus"); 2227 pci_qdev_unrealize(DEVICE(pci_dev)); 2228 return; 2229 } 2230 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2231 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2232 error_setg(errp, "failover primary device is not an " 2233 "Ethernet device"); 2234 pci_qdev_unrealize(DEVICE(pci_dev)); 2235 return; 2236 } 2237 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2238 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2239 error_setg(errp, "failover: primary device must be in its own " 2240 "PCI slot"); 2241 pci_qdev_unrealize(DEVICE(pci_dev)); 2242 return; 2243 } 2244 qdev->allow_unplug_during_migration = true; 2245 } 2246 2247 /* rom loading */ 2248 is_default_rom = false; 2249 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2250 pci_dev->romfile = g_strdup(pc->romfile); 2251 is_default_rom = true; 2252 } 2253 2254 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2255 if (local_err) { 2256 error_propagate(errp, local_err); 2257 pci_qdev_unrealize(DEVICE(pci_dev)); 2258 return; 2259 } 2260 2261 pci_set_power(pci_dev, true); 2262 2263 pci_dev->msi_trigger = pci_msi_trigger; 2264 } 2265 2266 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2267 const char *name) 2268 { 2269 DeviceState *dev; 2270 2271 dev = qdev_new(name); 2272 qdev_prop_set_int32(dev, "addr", devfn); 2273 qdev_prop_set_bit(dev, "multifunction", multifunction); 2274 return PCI_DEVICE(dev); 2275 } 2276 2277 PCIDevice *pci_new(int devfn, const char *name) 2278 { 2279 return pci_new_multifunction(devfn, false, name); 2280 } 2281 2282 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2283 { 2284 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2285 } 2286 2287 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2288 bool multifunction, 2289 const char *name) 2290 { 2291 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2292 pci_realize_and_unref(dev, bus, &error_fatal); 2293 return dev; 2294 } 2295 2296 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2297 { 2298 return pci_create_simple_multifunction(bus, devfn, false, name); 2299 } 2300 2301 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2302 { 2303 int offset = PCI_CONFIG_HEADER_SIZE; 2304 int i; 2305 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2306 if (pdev->used[i]) 2307 offset = i + 1; 2308 else if (i - offset + 1 == size) 2309 return offset; 2310 } 2311 return 0; 2312 } 2313 2314 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2315 uint8_t *prev_p) 2316 { 2317 uint8_t next, prev; 2318 2319 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2320 return 0; 2321 2322 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2323 prev = next + PCI_CAP_LIST_NEXT) 2324 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2325 break; 2326 2327 if (prev_p) 2328 *prev_p = prev; 2329 return next; 2330 } 2331 2332 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2333 { 2334 uint8_t next, prev, found = 0; 2335 2336 if (!(pdev->used[offset])) { 2337 return 0; 2338 } 2339 2340 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2341 2342 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2343 prev = next + PCI_CAP_LIST_NEXT) { 2344 if (next <= offset && next > found) { 2345 found = next; 2346 } 2347 } 2348 return found; 2349 } 2350 2351 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2352 This is needed for an option rom which is used for more than one device. */ 2353 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2354 { 2355 uint16_t vendor_id; 2356 uint16_t device_id; 2357 uint16_t rom_vendor_id; 2358 uint16_t rom_device_id; 2359 uint16_t rom_magic; 2360 uint16_t pcir_offset; 2361 uint8_t checksum; 2362 2363 /* Words in rom data are little endian (like in PCI configuration), 2364 so they can be read / written with pci_get_word / pci_set_word. */ 2365 2366 /* Only a valid rom will be patched. */ 2367 rom_magic = pci_get_word(ptr); 2368 if (rom_magic != 0xaa55) { 2369 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2370 return; 2371 } 2372 pcir_offset = pci_get_word(ptr + 0x18); 2373 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2374 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2375 return; 2376 } 2377 2378 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2379 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2380 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2381 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2382 2383 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2384 vendor_id, device_id, rom_vendor_id, rom_device_id); 2385 2386 checksum = ptr[6]; 2387 2388 if (vendor_id != rom_vendor_id) { 2389 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2390 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2391 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2392 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2393 ptr[6] = checksum; 2394 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2395 } 2396 2397 if (device_id != rom_device_id) { 2398 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2399 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2400 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2401 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2402 ptr[6] = checksum; 2403 pci_set_word(ptr + pcir_offset + 6, device_id); 2404 } 2405 } 2406 2407 /* Add an option rom for the device */ 2408 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2409 Error **errp) 2410 { 2411 int64_t size; 2412 char *path; 2413 void *ptr; 2414 char name[32]; 2415 const VMStateDescription *vmsd; 2416 2417 if (!pdev->romfile) 2418 return; 2419 if (strlen(pdev->romfile) == 0) 2420 return; 2421 2422 if (!pdev->rom_bar) { 2423 /* 2424 * Load rom via fw_cfg instead of creating a rom bar, 2425 * for 0.11 compatibility. 2426 */ 2427 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2428 2429 /* 2430 * Hot-plugged devices can't use the option ROM 2431 * if the rom bar is disabled. 2432 */ 2433 if (DEVICE(pdev)->hotplugged) { 2434 error_setg(errp, "Hot-plugged device without ROM bar" 2435 " can't have an option ROM"); 2436 return; 2437 } 2438 2439 if (class == 0x0300) { 2440 rom_add_vga(pdev->romfile); 2441 } else { 2442 rom_add_option(pdev->romfile, -1); 2443 } 2444 return; 2445 } 2446 2447 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2448 if (path == NULL) { 2449 path = g_strdup(pdev->romfile); 2450 } 2451 2452 size = get_image_size(path); 2453 if (size < 0) { 2454 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2455 g_free(path); 2456 return; 2457 } else if (size == 0) { 2458 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2459 g_free(path); 2460 return; 2461 } else if (size > 2 * GiB) { 2462 error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2463 pdev->romfile); 2464 g_free(path); 2465 return; 2466 } 2467 if (pdev->romsize != -1) { 2468 if (size > pdev->romsize) { 2469 error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size %u", 2470 pdev->romfile, (uint32_t)size, pdev->romsize); 2471 g_free(path); 2472 return; 2473 } 2474 } else { 2475 pdev->romsize = pow2ceil(size); 2476 } 2477 2478 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2479 2480 if (vmsd) { 2481 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2482 } else { 2483 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2484 } 2485 pdev->has_rom = true; 2486 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, &error_fatal); 2487 ptr = memory_region_get_ram_ptr(&pdev->rom); 2488 if (load_image_size(path, ptr, size) < 0) { 2489 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2490 g_free(path); 2491 return; 2492 } 2493 g_free(path); 2494 2495 if (is_default_rom) { 2496 /* Only the default rom images will be patched (if needed). */ 2497 pci_patch_ids(pdev, ptr, size); 2498 } 2499 2500 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2501 } 2502 2503 static void pci_del_option_rom(PCIDevice *pdev) 2504 { 2505 if (!pdev->has_rom) 2506 return; 2507 2508 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2509 pdev->has_rom = false; 2510 } 2511 2512 /* 2513 * On success, pci_add_capability() returns a positive value 2514 * that the offset of the pci capability. 2515 * On failure, it sets an error and returns a negative error 2516 * code. 2517 */ 2518 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2519 uint8_t offset, uint8_t size, 2520 Error **errp) 2521 { 2522 uint8_t *config; 2523 int i, overlapping_cap; 2524 2525 if (!offset) { 2526 offset = pci_find_space(pdev, size); 2527 /* out of PCI config space is programming error */ 2528 assert(offset); 2529 } else { 2530 /* Verify that capabilities don't overlap. Note: device assignment 2531 * depends on this check to verify that the device is not broken. 2532 * Should never trigger for emulated devices, but it's helpful 2533 * for debugging these. */ 2534 for (i = offset; i < offset + size; i++) { 2535 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2536 if (overlapping_cap) { 2537 error_setg(errp, "%s:%02x:%02x.%x " 2538 "Attempt to add PCI capability %x at offset " 2539 "%x overlaps existing capability %x at offset %x", 2540 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2541 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2542 cap_id, offset, overlapping_cap, i); 2543 return -EINVAL; 2544 } 2545 } 2546 } 2547 2548 config = pdev->config + offset; 2549 config[PCI_CAP_LIST_ID] = cap_id; 2550 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2551 pdev->config[PCI_CAPABILITY_LIST] = offset; 2552 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2553 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2554 /* Make capability read-only by default */ 2555 memset(pdev->wmask + offset, 0, size); 2556 /* Check capability by default */ 2557 memset(pdev->cmask + offset, 0xFF, size); 2558 return offset; 2559 } 2560 2561 /* Unlink capability from the pci config space. */ 2562 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2563 { 2564 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2565 if (!offset) 2566 return; 2567 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2568 /* Make capability writable again */ 2569 memset(pdev->wmask + offset, 0xff, size); 2570 memset(pdev->w1cmask + offset, 0, size); 2571 /* Clear cmask as device-specific registers can't be checked */ 2572 memset(pdev->cmask + offset, 0, size); 2573 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2574 2575 if (!pdev->config[PCI_CAPABILITY_LIST]) 2576 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2577 } 2578 2579 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2580 { 2581 return pci_find_capability_list(pdev, cap_id, NULL); 2582 } 2583 2584 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2585 { 2586 PCIDevice *d = (PCIDevice *)dev; 2587 const pci_class_desc *desc; 2588 char ctxt[64]; 2589 PCIIORegion *r; 2590 int i, class; 2591 2592 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2593 desc = pci_class_descriptions; 2594 while (desc->desc && class != desc->class) 2595 desc++; 2596 if (desc->desc) { 2597 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2598 } else { 2599 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2600 } 2601 2602 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2603 "pci id %04x:%04x (sub %04x:%04x)\n", 2604 indent, "", ctxt, pci_dev_bus_num(d), 2605 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2606 pci_get_word(d->config + PCI_VENDOR_ID), 2607 pci_get_word(d->config + PCI_DEVICE_ID), 2608 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2609 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2610 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2611 r = &d->io_regions[i]; 2612 if (!r->size) 2613 continue; 2614 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2615 " [0x%"FMT_PCIBUS"]\n", 2616 indent, "", 2617 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2618 r->addr, r->addr + r->size - 1); 2619 } 2620 } 2621 2622 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2623 { 2624 PCIDevice *d = (PCIDevice *)dev; 2625 const char *name = NULL; 2626 const pci_class_desc *desc = pci_class_descriptions; 2627 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2628 2629 while (desc->desc && 2630 (class & ~desc->fw_ign_bits) != 2631 (desc->class & ~desc->fw_ign_bits)) { 2632 desc++; 2633 } 2634 2635 if (desc->desc) { 2636 name = desc->fw_name; 2637 } 2638 2639 if (name) { 2640 pstrcpy(buf, len, name); 2641 } else { 2642 snprintf(buf, len, "pci%04x,%04x", 2643 pci_get_word(d->config + PCI_VENDOR_ID), 2644 pci_get_word(d->config + PCI_DEVICE_ID)); 2645 } 2646 2647 return buf; 2648 } 2649 2650 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2651 { 2652 PCIDevice *d = (PCIDevice *)dev; 2653 char name[33]; 2654 int has_func = !!PCI_FUNC(d->devfn); 2655 2656 return g_strdup_printf("%s@%x%s%.*x", 2657 pci_dev_fw_name(dev, name, sizeof(name)), 2658 PCI_SLOT(d->devfn), 2659 has_func ? "," : "", 2660 has_func, 2661 PCI_FUNC(d->devfn)); 2662 } 2663 2664 static char *pcibus_get_dev_path(DeviceState *dev) 2665 { 2666 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2667 PCIDevice *t; 2668 int slot_depth; 2669 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2670 * 00 is added here to make this format compatible with 2671 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2672 * Slot.Function list specifies the slot and function numbers for all 2673 * devices on the path from root to the specific device. */ 2674 const char *root_bus_path; 2675 int root_bus_len; 2676 char slot[] = ":SS.F"; 2677 int slot_len = sizeof slot - 1 /* For '\0' */; 2678 int path_len; 2679 char *path, *p; 2680 int s; 2681 2682 root_bus_path = pci_root_bus_path(d); 2683 root_bus_len = strlen(root_bus_path); 2684 2685 /* Calculate # of slots on path between device and root. */; 2686 slot_depth = 0; 2687 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2688 ++slot_depth; 2689 } 2690 2691 path_len = root_bus_len + slot_len * slot_depth; 2692 2693 /* Allocate memory, fill in the terminating null byte. */ 2694 path = g_malloc(path_len + 1 /* For '\0' */); 2695 path[path_len] = '\0'; 2696 2697 memcpy(path, root_bus_path, root_bus_len); 2698 2699 /* Fill in slot numbers. We walk up from device to root, so need to print 2700 * them in the reverse order, last to first. */ 2701 p = path + path_len; 2702 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2703 p -= slot_len; 2704 s = snprintf(slot, sizeof slot, ":%02x.%x", 2705 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2706 assert(s == slot_len); 2707 memcpy(p, slot, slot_len); 2708 } 2709 2710 return path; 2711 } 2712 2713 static int pci_qdev_find_recursive(PCIBus *bus, 2714 const char *id, PCIDevice **pdev) 2715 { 2716 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2717 if (!qdev) { 2718 return -ENODEV; 2719 } 2720 2721 /* roughly check if given qdev is pci device */ 2722 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2723 *pdev = PCI_DEVICE(qdev); 2724 return 0; 2725 } 2726 return -EINVAL; 2727 } 2728 2729 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2730 { 2731 PCIHostState *host_bridge; 2732 int rc = -ENODEV; 2733 2734 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2735 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2736 if (!tmp) { 2737 rc = 0; 2738 break; 2739 } 2740 if (tmp != -ENODEV) { 2741 rc = tmp; 2742 } 2743 } 2744 2745 return rc; 2746 } 2747 2748 MemoryRegion *pci_address_space(PCIDevice *dev) 2749 { 2750 return pci_get_bus(dev)->address_space_mem; 2751 } 2752 2753 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2754 { 2755 return pci_get_bus(dev)->address_space_io; 2756 } 2757 2758 static void pci_device_class_init(ObjectClass *klass, void *data) 2759 { 2760 DeviceClass *k = DEVICE_CLASS(klass); 2761 2762 k->realize = pci_qdev_realize; 2763 k->unrealize = pci_qdev_unrealize; 2764 k->bus_type = TYPE_PCI_BUS; 2765 device_class_set_props(k, pci_props); 2766 } 2767 2768 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2769 { 2770 if (!object_class_is_abstract(klass)) { 2771 ObjectClass *conventional = 2772 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2773 ObjectClass *pcie = 2774 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2775 ObjectClass *cxl = 2776 object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); 2777 assert(conventional || pcie || cxl); 2778 } 2779 } 2780 2781 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2782 { 2783 PCIBus *bus = pci_get_bus(dev); 2784 PCIBus *iommu_bus = bus; 2785 uint8_t devfn = dev->devfn; 2786 2787 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2788 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2789 2790 /* 2791 * The requester ID of the provided device may be aliased, as seen from 2792 * the IOMMU, due to topology limitations. The IOMMU relies on a 2793 * requester ID to provide a unique AddressSpace for devices, but 2794 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2795 * to-PCI bridge creates and accepts transactions on behalf of down- 2796 * stream devices. When doing so, all downstream devices are masked 2797 * (aliased) behind a single requester ID. The requester ID used 2798 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2799 * bridges, with a PCIe capability indicating such, follow the 2800 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2801 * where the bridge uses the seconary bus as the bridge portion of the 2802 * requester ID and devfn of 00.0. For other bridges, typically those 2803 * found on the root complex such as the dmi-to-pci-bridge, we follow 2804 * the convention of typical bare-metal hardware, which uses the 2805 * requester ID of the bridge itself. There are device specific 2806 * exceptions to these rules, but these are the defaults that the 2807 * Linux kernel uses when determining DMA aliases itself and believed 2808 * to be true for the bare metal equivalents of the devices emulated 2809 * in QEMU. 2810 */ 2811 if (!pci_bus_is_express(iommu_bus)) { 2812 PCIDevice *parent = iommu_bus->parent_dev; 2813 2814 if (pci_is_express(parent) && 2815 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2816 devfn = PCI_DEVFN(0, 0); 2817 bus = iommu_bus; 2818 } else { 2819 devfn = parent->devfn; 2820 bus = parent_bus; 2821 } 2822 } 2823 2824 iommu_bus = parent_bus; 2825 } 2826 if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { 2827 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2828 } 2829 return &address_space_memory; 2830 } 2831 2832 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2833 { 2834 bus->iommu_fn = fn; 2835 bus->iommu_opaque = opaque; 2836 } 2837 2838 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2839 { 2840 Range *range = opaque; 2841 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2842 int i; 2843 2844 if (!(cmd & PCI_COMMAND_MEMORY)) { 2845 return; 2846 } 2847 2848 if (IS_PCI_BRIDGE(dev)) { 2849 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2850 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2851 2852 base = MAX(base, 0x1ULL << 32); 2853 2854 if (limit >= base) { 2855 Range pref_range; 2856 range_set_bounds(&pref_range, base, limit); 2857 range_extend(range, &pref_range); 2858 } 2859 } 2860 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2861 PCIIORegion *r = &dev->io_regions[i]; 2862 pcibus_t lob, upb; 2863 Range region_range; 2864 2865 if (!r->size || 2866 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2867 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2868 continue; 2869 } 2870 2871 lob = pci_bar_address(dev, i, r->type, r->size); 2872 upb = lob + r->size - 1; 2873 if (lob == PCI_BAR_UNMAPPED) { 2874 continue; 2875 } 2876 2877 lob = MAX(lob, 0x1ULL << 32); 2878 2879 if (upb >= lob) { 2880 range_set_bounds(®ion_range, lob, upb); 2881 range_extend(range, ®ion_range); 2882 } 2883 } 2884 } 2885 2886 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2887 { 2888 range_make_empty(range); 2889 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2890 } 2891 2892 static bool pcie_has_upstream_port(PCIDevice *dev) 2893 { 2894 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2895 2896 /* Device associated with an upstream port. 2897 * As there are several types of these, it's easier to check the 2898 * parent device: upstream ports are always connected to 2899 * root or downstream ports. 2900 */ 2901 return parent_dev && 2902 pci_is_express(parent_dev) && 2903 parent_dev->exp.exp_cap && 2904 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2905 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2906 } 2907 2908 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2909 { 2910 PCIBus *bus = pci_get_bus(pci_dev); 2911 2912 if(pcie_has_upstream_port(pci_dev)) { 2913 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2914 return bus->devices[0]; 2915 } else { 2916 /* Other bus types might support multiple devices at slots 0-31 */ 2917 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2918 } 2919 } 2920 2921 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2922 { 2923 MSIMessage msg; 2924 if (msix_enabled(dev)) { 2925 msg = msix_get_message(dev, vector); 2926 } else if (msi_enabled(dev)) { 2927 msg = msi_get_message(dev, vector); 2928 } else { 2929 /* Should never happen */ 2930 error_report("%s: unknown interrupt type", __func__); 2931 abort(); 2932 } 2933 return msg; 2934 } 2935 2936 void pci_set_power(PCIDevice *d, bool state) 2937 { 2938 if (d->has_power == state) { 2939 return; 2940 } 2941 2942 d->has_power = state; 2943 pci_update_mappings(d); 2944 memory_region_set_enabled(&d->bus_master_enable_region, 2945 (pci_get_word(d->config + PCI_COMMAND) 2946 & PCI_COMMAND_MASTER) && d->has_power); 2947 if (!d->has_power) { 2948 pci_device_reset(d); 2949 } 2950 } 2951 2952 static const TypeInfo pci_device_type_info = { 2953 .name = TYPE_PCI_DEVICE, 2954 .parent = TYPE_DEVICE, 2955 .instance_size = sizeof(PCIDevice), 2956 .abstract = true, 2957 .class_size = sizeof(PCIDeviceClass), 2958 .class_init = pci_device_class_init, 2959 .class_base_init = pci_device_class_base_init, 2960 }; 2961 2962 static void pci_register_types(void) 2963 { 2964 type_register_static(&pci_bus_info); 2965 type_register_static(&pcie_bus_info); 2966 type_register_static(&cxl_bus_info); 2967 type_register_static(&conventional_pci_interface_info); 2968 type_register_static(&cxl_interface_info); 2969 type_register_static(&pcie_interface_info); 2970 type_register_static(&pci_device_type_info); 2971 } 2972 2973 type_init(pci_register_types) 2974