1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pci_host.h" 29 #include "monitor/monitor.h" 30 #include "net/net.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/loader.h" 33 #include "qemu/error-report.h" 34 #include "qemu/range.h" 35 #include "qmp-commands.h" 36 #include "trace.h" 37 #include "hw/pci/msi.h" 38 #include "hw/pci/msix.h" 39 #include "exec/address-spaces.h" 40 #include "hw/hotplug.h" 41 #include "hw/boards.h" 42 43 //#define DEBUG_PCI 44 #ifdef DEBUG_PCI 45 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 46 #else 47 # define PCI_DPRINTF(format, ...) do { } while (0) 48 #endif 49 50 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 51 static char *pcibus_get_dev_path(DeviceState *dev); 52 static char *pcibus_get_fw_dev_path(DeviceState *dev); 53 static void pcibus_reset(BusState *qbus); 54 55 static Property pci_props[] = { 56 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 57 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 58 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 59 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 60 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 61 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 62 QEMU_PCI_CAP_SERR_BITNR, true), 63 DEFINE_PROP_END_OF_LIST() 64 }; 65 66 static const VMStateDescription vmstate_pcibus = { 67 .name = "PCIBUS", 68 .version_id = 1, 69 .minimum_version_id = 1, 70 .fields = (VMStateField[]) { 71 VMSTATE_INT32_EQUAL(nirq, PCIBus), 72 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 73 nirq, 0, vmstate_info_int32, 74 int32_t), 75 VMSTATE_END_OF_LIST() 76 } 77 }; 78 79 static void pci_bus_realize(BusState *qbus, Error **errp) 80 { 81 PCIBus *bus = PCI_BUS(qbus); 82 83 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 84 } 85 86 static void pci_bus_unrealize(BusState *qbus, Error **errp) 87 { 88 PCIBus *bus = PCI_BUS(qbus); 89 90 vmstate_unregister(NULL, &vmstate_pcibus, bus); 91 } 92 93 static bool pcibus_is_root(PCIBus *bus) 94 { 95 return !bus->parent_dev; 96 } 97 98 static int pcibus_num(PCIBus *bus) 99 { 100 if (pcibus_is_root(bus)) { 101 return 0; /* pci host bridge */ 102 } 103 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 104 } 105 106 static uint16_t pcibus_numa_node(PCIBus *bus) 107 { 108 return NUMA_NODE_UNASSIGNED; 109 } 110 111 static void pci_bus_class_init(ObjectClass *klass, void *data) 112 { 113 BusClass *k = BUS_CLASS(klass); 114 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 115 116 k->print_dev = pcibus_dev_print; 117 k->get_dev_path = pcibus_get_dev_path; 118 k->get_fw_dev_path = pcibus_get_fw_dev_path; 119 k->realize = pci_bus_realize; 120 k->unrealize = pci_bus_unrealize; 121 k->reset = pcibus_reset; 122 123 pbc->is_root = pcibus_is_root; 124 pbc->bus_num = pcibus_num; 125 pbc->numa_node = pcibus_numa_node; 126 } 127 128 static const TypeInfo pci_bus_info = { 129 .name = TYPE_PCI_BUS, 130 .parent = TYPE_BUS, 131 .instance_size = sizeof(PCIBus), 132 .class_size = sizeof(PCIBusClass), 133 .class_init = pci_bus_class_init, 134 }; 135 136 static const TypeInfo pcie_bus_info = { 137 .name = TYPE_PCIE_BUS, 138 .parent = TYPE_PCI_BUS, 139 }; 140 141 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 142 static void pci_update_mappings(PCIDevice *d); 143 static void pci_irq_handler(void *opaque, int irq_num, int level); 144 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 145 static void pci_del_option_rom(PCIDevice *pdev); 146 147 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 148 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 149 150 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 151 152 int pci_bar(PCIDevice *d, int reg) 153 { 154 uint8_t type; 155 156 if (reg != PCI_ROM_SLOT) 157 return PCI_BASE_ADDRESS_0 + reg * 4; 158 159 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 160 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 161 } 162 163 static inline int pci_irq_state(PCIDevice *d, int irq_num) 164 { 165 return (d->irq_state >> irq_num) & 0x1; 166 } 167 168 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 169 { 170 d->irq_state &= ~(0x1 << irq_num); 171 d->irq_state |= level << irq_num; 172 } 173 174 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 175 { 176 PCIBus *bus; 177 for (;;) { 178 bus = pci_dev->bus; 179 irq_num = bus->map_irq(pci_dev, irq_num); 180 if (bus->set_irq) 181 break; 182 pci_dev = bus->parent_dev; 183 } 184 bus->irq_count[irq_num] += change; 185 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 186 } 187 188 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 189 { 190 assert(irq_num >= 0); 191 assert(irq_num < bus->nirq); 192 return !!bus->irq_count[irq_num]; 193 } 194 195 /* Update interrupt status bit in config space on interrupt 196 * state change. */ 197 static void pci_update_irq_status(PCIDevice *dev) 198 { 199 if (dev->irq_state) { 200 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 201 } else { 202 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 203 } 204 } 205 206 void pci_device_deassert_intx(PCIDevice *dev) 207 { 208 int i; 209 for (i = 0; i < PCI_NUM_PINS; ++i) { 210 pci_irq_handler(dev, i, 0); 211 } 212 } 213 214 static void pci_do_device_reset(PCIDevice *dev) 215 { 216 int r; 217 218 pci_device_deassert_intx(dev); 219 assert(dev->irq_state == 0); 220 221 /* Clear all writable bits */ 222 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 223 pci_get_word(dev->wmask + PCI_COMMAND) | 224 pci_get_word(dev->w1cmask + PCI_COMMAND)); 225 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 226 pci_get_word(dev->wmask + PCI_STATUS) | 227 pci_get_word(dev->w1cmask + PCI_STATUS)); 228 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 229 dev->config[PCI_INTERRUPT_LINE] = 0x0; 230 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 231 PCIIORegion *region = &dev->io_regions[r]; 232 if (!region->size) { 233 continue; 234 } 235 236 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 237 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 238 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 239 } else { 240 pci_set_long(dev->config + pci_bar(dev, r), region->type); 241 } 242 } 243 pci_update_mappings(dev); 244 245 msi_reset(dev); 246 msix_reset(dev); 247 } 248 249 /* 250 * This function is called on #RST and FLR. 251 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 252 */ 253 void pci_device_reset(PCIDevice *dev) 254 { 255 qdev_reset_all(&dev->qdev); 256 pci_do_device_reset(dev); 257 } 258 259 /* 260 * Trigger pci bus reset under a given bus. 261 * Called via qbus_reset_all on RST# assert, after the devices 262 * have been reset qdev_reset_all-ed already. 263 */ 264 static void pcibus_reset(BusState *qbus) 265 { 266 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 270 if (bus->devices[i]) { 271 pci_do_device_reset(bus->devices[i]); 272 } 273 } 274 275 for (i = 0; i < bus->nirq; i++) { 276 assert(bus->irq_count[i] == 0); 277 } 278 } 279 280 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) 281 { 282 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); 283 284 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 285 } 286 287 PCIBus *pci_find_primary_bus(void) 288 { 289 PCIBus *primary_bus = NULL; 290 PCIHostState *host; 291 292 QLIST_FOREACH(host, &pci_host_bridges, next) { 293 if (primary_bus) { 294 /* We have multiple root buses, refuse to select a primary */ 295 return NULL; 296 } 297 primary_bus = host->bus; 298 } 299 300 return primary_bus; 301 } 302 303 PCIBus *pci_device_root_bus(const PCIDevice *d) 304 { 305 PCIBus *bus = d->bus; 306 307 while (!pci_bus_is_root(bus)) { 308 d = bus->parent_dev; 309 assert(d != NULL); 310 311 bus = d->bus; 312 } 313 314 return bus; 315 } 316 317 const char *pci_root_bus_path(PCIDevice *dev) 318 { 319 PCIBus *rootbus = pci_device_root_bus(dev); 320 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 321 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 322 323 assert(host_bridge->bus == rootbus); 324 325 if (hc->root_bus_path) { 326 return (*hc->root_bus_path)(host_bridge, rootbus); 327 } 328 329 return rootbus->qbus.name; 330 } 331 332 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 333 const char *name, 334 MemoryRegion *address_space_mem, 335 MemoryRegion *address_space_io, 336 uint8_t devfn_min) 337 { 338 assert(PCI_FUNC(devfn_min) == 0); 339 bus->devfn_min = devfn_min; 340 bus->address_space_mem = address_space_mem; 341 bus->address_space_io = address_space_io; 342 343 /* host bridge */ 344 QLIST_INIT(&bus->child); 345 346 pci_host_bus_register(bus, parent); 347 } 348 349 bool pci_bus_is_express(PCIBus *bus) 350 { 351 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 352 } 353 354 bool pci_bus_is_root(PCIBus *bus) 355 { 356 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 357 } 358 359 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 360 const char *name, 361 MemoryRegion *address_space_mem, 362 MemoryRegion *address_space_io, 363 uint8_t devfn_min, const char *typename) 364 { 365 qbus_create_inplace(bus, bus_size, typename, parent, name); 366 pci_bus_init(bus, parent, name, address_space_mem, 367 address_space_io, devfn_min); 368 } 369 370 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 371 MemoryRegion *address_space_mem, 372 MemoryRegion *address_space_io, 373 uint8_t devfn_min, const char *typename) 374 { 375 PCIBus *bus; 376 377 bus = PCI_BUS(qbus_create(typename, parent, name)); 378 pci_bus_init(bus, parent, name, address_space_mem, 379 address_space_io, devfn_min); 380 return bus; 381 } 382 383 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 384 void *irq_opaque, int nirq) 385 { 386 bus->set_irq = set_irq; 387 bus->map_irq = map_irq; 388 bus->irq_opaque = irq_opaque; 389 bus->nirq = nirq; 390 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 391 } 392 393 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 394 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 395 void *irq_opaque, 396 MemoryRegion *address_space_mem, 397 MemoryRegion *address_space_io, 398 uint8_t devfn_min, int nirq, const char *typename) 399 { 400 PCIBus *bus; 401 402 bus = pci_bus_new(parent, name, address_space_mem, 403 address_space_io, devfn_min, typename); 404 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 405 return bus; 406 } 407 408 int pci_bus_num(PCIBus *s) 409 { 410 return PCI_BUS_GET_CLASS(s)->bus_num(s); 411 } 412 413 int pci_bus_numa_node(PCIBus *bus) 414 { 415 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 416 } 417 418 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 419 { 420 PCIDevice *s = container_of(pv, PCIDevice, config); 421 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 422 uint8_t *config; 423 int i; 424 425 assert(size == pci_config_size(s)); 426 config = g_malloc(size); 427 428 qemu_get_buffer(f, config, size); 429 for (i = 0; i < size; ++i) { 430 if ((config[i] ^ s->config[i]) & 431 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 432 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 433 "cmask: %x wmask: %x w1cmask:%x", __func__, 434 i, config[i], s->config[i], 435 s->cmask[i], s->wmask[i], s->w1cmask[i]); 436 g_free(config); 437 return -EINVAL; 438 } 439 } 440 memcpy(s->config, config, size); 441 442 pci_update_mappings(s); 443 if (pc->is_bridge) { 444 PCIBridge *b = PCI_BRIDGE(s); 445 pci_bridge_update_mappings(b); 446 } 447 448 memory_region_set_enabled(&s->bus_master_enable_region, 449 pci_get_word(s->config + PCI_COMMAND) 450 & PCI_COMMAND_MASTER); 451 452 g_free(config); 453 return 0; 454 } 455 456 /* just put buffer */ 457 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 458 { 459 const uint8_t **v = pv; 460 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 461 qemu_put_buffer(f, *v, size); 462 } 463 464 static VMStateInfo vmstate_info_pci_config = { 465 .name = "pci config", 466 .get = get_pci_config_device, 467 .put = put_pci_config_device, 468 }; 469 470 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 471 { 472 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 473 uint32_t irq_state[PCI_NUM_PINS]; 474 int i; 475 for (i = 0; i < PCI_NUM_PINS; ++i) { 476 irq_state[i] = qemu_get_be32(f); 477 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 478 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 479 irq_state[i]); 480 return -EINVAL; 481 } 482 } 483 484 for (i = 0; i < PCI_NUM_PINS; ++i) { 485 pci_set_irq_state(s, i, irq_state[i]); 486 } 487 488 return 0; 489 } 490 491 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 492 { 493 int i; 494 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 495 496 for (i = 0; i < PCI_NUM_PINS; ++i) { 497 qemu_put_be32(f, pci_irq_state(s, i)); 498 } 499 } 500 501 static VMStateInfo vmstate_info_pci_irq_state = { 502 .name = "pci irq state", 503 .get = get_pci_irq_state, 504 .put = put_pci_irq_state, 505 }; 506 507 const VMStateDescription vmstate_pci_device = { 508 .name = "PCIDevice", 509 .version_id = 2, 510 .minimum_version_id = 1, 511 .fields = (VMStateField[]) { 512 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 513 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 514 vmstate_info_pci_config, 515 PCI_CONFIG_SPACE_SIZE), 516 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 517 vmstate_info_pci_irq_state, 518 PCI_NUM_PINS * sizeof(int32_t)), 519 VMSTATE_END_OF_LIST() 520 } 521 }; 522 523 const VMStateDescription vmstate_pcie_device = { 524 .name = "PCIEDevice", 525 .version_id = 2, 526 .minimum_version_id = 1, 527 .fields = (VMStateField[]) { 528 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 529 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 530 vmstate_info_pci_config, 531 PCIE_CONFIG_SPACE_SIZE), 532 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 533 vmstate_info_pci_irq_state, 534 PCI_NUM_PINS * sizeof(int32_t)), 535 VMSTATE_END_OF_LIST() 536 } 537 }; 538 539 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 540 { 541 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 542 } 543 544 void pci_device_save(PCIDevice *s, QEMUFile *f) 545 { 546 /* Clear interrupt status bit: it is implicit 547 * in irq_state which we are saving. 548 * This makes us compatible with old devices 549 * which never set or clear this bit. */ 550 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 551 vmstate_save_state(f, pci_get_vmstate(s), s, NULL); 552 /* Restore the interrupt status bit. */ 553 pci_update_irq_status(s); 554 } 555 556 int pci_device_load(PCIDevice *s, QEMUFile *f) 557 { 558 int ret; 559 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 560 /* Restore the interrupt status bit. */ 561 pci_update_irq_status(s); 562 return ret; 563 } 564 565 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 566 { 567 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 568 pci_default_sub_vendor_id); 569 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 570 pci_default_sub_device_id); 571 } 572 573 /* 574 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 575 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 576 */ 577 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 578 unsigned int *slotp, unsigned int *funcp) 579 { 580 const char *p; 581 char *e; 582 unsigned long val; 583 unsigned long dom = 0, bus = 0; 584 unsigned int slot = 0; 585 unsigned int func = 0; 586 587 p = addr; 588 val = strtoul(p, &e, 16); 589 if (e == p) 590 return -1; 591 if (*e == ':') { 592 bus = val; 593 p = e + 1; 594 val = strtoul(p, &e, 16); 595 if (e == p) 596 return -1; 597 if (*e == ':') { 598 dom = bus; 599 bus = val; 600 p = e + 1; 601 val = strtoul(p, &e, 16); 602 if (e == p) 603 return -1; 604 } 605 } 606 607 slot = val; 608 609 if (funcp != NULL) { 610 if (*e != '.') 611 return -1; 612 613 p = e + 1; 614 val = strtoul(p, &e, 16); 615 if (e == p) 616 return -1; 617 618 func = val; 619 } 620 621 /* if funcp == NULL func is 0 */ 622 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 623 return -1; 624 625 if (*e) 626 return -1; 627 628 *domp = dom; 629 *busp = bus; 630 *slotp = slot; 631 if (funcp != NULL) 632 *funcp = func; 633 return 0; 634 } 635 636 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 637 const char *devaddr) 638 { 639 int dom, bus; 640 unsigned slot; 641 642 if (!root) { 643 fprintf(stderr, "No primary PCI bus\n"); 644 return NULL; 645 } 646 647 assert(!root->parent_dev); 648 649 if (!devaddr) { 650 *devfnp = -1; 651 return pci_find_bus_nr(root, 0); 652 } 653 654 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 655 return NULL; 656 } 657 658 if (dom != 0) { 659 fprintf(stderr, "No support for non-zero PCI domains\n"); 660 return NULL; 661 } 662 663 *devfnp = PCI_DEVFN(slot, 0); 664 return pci_find_bus_nr(root, bus); 665 } 666 667 static void pci_init_cmask(PCIDevice *dev) 668 { 669 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 670 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 671 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 672 dev->cmask[PCI_REVISION_ID] = 0xff; 673 dev->cmask[PCI_CLASS_PROG] = 0xff; 674 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 675 dev->cmask[PCI_HEADER_TYPE] = 0xff; 676 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 677 } 678 679 static void pci_init_wmask(PCIDevice *dev) 680 { 681 int config_size = pci_config_size(dev); 682 683 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 684 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 685 pci_set_word(dev->wmask + PCI_COMMAND, 686 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 687 PCI_COMMAND_INTX_DISABLE); 688 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 689 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 690 } 691 692 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 693 config_size - PCI_CONFIG_HEADER_SIZE); 694 } 695 696 static void pci_init_w1cmask(PCIDevice *dev) 697 { 698 /* 699 * Note: It's okay to set w1cmask even for readonly bits as 700 * long as their value is hardwired to 0. 701 */ 702 pci_set_word(dev->w1cmask + PCI_STATUS, 703 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 704 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 705 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 706 } 707 708 static void pci_init_mask_bridge(PCIDevice *d) 709 { 710 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 711 PCI_SEC_LETENCY_TIMER */ 712 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 713 714 /* base and limit */ 715 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 716 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 717 pci_set_word(d->wmask + PCI_MEMORY_BASE, 718 PCI_MEMORY_RANGE_MASK & 0xffff); 719 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 720 PCI_MEMORY_RANGE_MASK & 0xffff); 721 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 722 PCI_PREF_RANGE_MASK & 0xffff); 723 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 724 PCI_PREF_RANGE_MASK & 0xffff); 725 726 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 727 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 728 729 /* Supported memory and i/o types */ 730 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 731 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 732 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 733 PCI_PREF_RANGE_TYPE_64); 734 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 735 PCI_PREF_RANGE_TYPE_64); 736 737 /* 738 * TODO: Bridges default to 10-bit VGA decoding but we currently only 739 * implement 16-bit decoding (no alias support). 740 */ 741 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 742 PCI_BRIDGE_CTL_PARITY | 743 PCI_BRIDGE_CTL_SERR | 744 PCI_BRIDGE_CTL_ISA | 745 PCI_BRIDGE_CTL_VGA | 746 PCI_BRIDGE_CTL_VGA_16BIT | 747 PCI_BRIDGE_CTL_MASTER_ABORT | 748 PCI_BRIDGE_CTL_BUS_RESET | 749 PCI_BRIDGE_CTL_FAST_BACK | 750 PCI_BRIDGE_CTL_DISCARD | 751 PCI_BRIDGE_CTL_SEC_DISCARD | 752 PCI_BRIDGE_CTL_DISCARD_SERR); 753 /* Below does not do anything as we never set this bit, put here for 754 * completeness. */ 755 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 756 PCI_BRIDGE_CTL_DISCARD_STATUS); 757 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 758 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 759 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 760 PCI_PREF_RANGE_TYPE_MASK); 761 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 762 PCI_PREF_RANGE_TYPE_MASK); 763 } 764 765 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 766 { 767 uint8_t slot = PCI_SLOT(dev->devfn); 768 uint8_t func; 769 770 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 771 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 772 } 773 774 /* 775 * multifunction bit is interpreted in two ways as follows. 776 * - all functions must set the bit to 1. 777 * Example: Intel X53 778 * - function 0 must set the bit, but the rest function (> 0) 779 * is allowed to leave the bit to 0. 780 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 781 * 782 * So OS (at least Linux) checks the bit of only function 0, 783 * and doesn't see the bit of function > 0. 784 * 785 * The below check allows both interpretation. 786 */ 787 if (PCI_FUNC(dev->devfn)) { 788 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 789 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 790 /* function 0 should set multifunction bit */ 791 error_setg(errp, "PCI: single function device can't be populated " 792 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 793 return; 794 } 795 return; 796 } 797 798 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 799 return; 800 } 801 /* function 0 indicates single function, so function > 0 must be NULL */ 802 for (func = 1; func < PCI_FUNC_MAX; ++func) { 803 if (bus->devices[PCI_DEVFN(slot, func)]) { 804 error_setg(errp, "PCI: %x.0 indicates single function, " 805 "but %x.%x is already populated.", 806 slot, slot, func); 807 return; 808 } 809 } 810 } 811 812 static void pci_config_alloc(PCIDevice *pci_dev) 813 { 814 int config_size = pci_config_size(pci_dev); 815 816 pci_dev->config = g_malloc0(config_size); 817 pci_dev->cmask = g_malloc0(config_size); 818 pci_dev->wmask = g_malloc0(config_size); 819 pci_dev->w1cmask = g_malloc0(config_size); 820 pci_dev->used = g_malloc0(config_size); 821 } 822 823 static void pci_config_free(PCIDevice *pci_dev) 824 { 825 g_free(pci_dev->config); 826 g_free(pci_dev->cmask); 827 g_free(pci_dev->wmask); 828 g_free(pci_dev->w1cmask); 829 g_free(pci_dev->used); 830 } 831 832 static void do_pci_unregister_device(PCIDevice *pci_dev) 833 { 834 pci_dev->bus->devices[pci_dev->devfn] = NULL; 835 pci_config_free(pci_dev); 836 837 address_space_destroy(&pci_dev->bus_master_as); 838 } 839 840 /* -1 for devfn means auto assign */ 841 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 842 const char *name, int devfn, 843 Error **errp) 844 { 845 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 846 PCIConfigReadFunc *config_read = pc->config_read; 847 PCIConfigWriteFunc *config_write = pc->config_write; 848 Error *local_err = NULL; 849 AddressSpace *dma_as; 850 851 if (devfn < 0) { 852 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 853 devfn += PCI_FUNC_MAX) { 854 if (!bus->devices[devfn]) 855 goto found; 856 } 857 error_setg(errp, "PCI: no slot/function available for %s, all in use", 858 name); 859 return NULL; 860 found: ; 861 } else if (bus->devices[devfn]) { 862 error_setg(errp, "PCI: slot %d function %d not available for %s," 863 " in use by %s", 864 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 865 bus->devices[devfn]->name); 866 return NULL; 867 } 868 869 pci_dev->bus = bus; 870 pci_dev->devfn = devfn; 871 dma_as = pci_device_iommu_address_space(pci_dev); 872 873 memory_region_init_alias(&pci_dev->bus_master_enable_region, 874 OBJECT(pci_dev), "bus master", 875 dma_as->root, 0, memory_region_size(dma_as->root)); 876 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 877 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 878 name); 879 880 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 881 pci_dev->irq_state = 0; 882 pci_config_alloc(pci_dev); 883 884 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 885 pci_config_set_device_id(pci_dev->config, pc->device_id); 886 pci_config_set_revision(pci_dev->config, pc->revision); 887 pci_config_set_class(pci_dev->config, pc->class_id); 888 889 if (!pc->is_bridge) { 890 if (pc->subsystem_vendor_id || pc->subsystem_id) { 891 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 892 pc->subsystem_vendor_id); 893 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 894 pc->subsystem_id); 895 } else { 896 pci_set_default_subsystem_id(pci_dev); 897 } 898 } else { 899 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 900 assert(!pc->subsystem_vendor_id); 901 assert(!pc->subsystem_id); 902 } 903 pci_init_cmask(pci_dev); 904 pci_init_wmask(pci_dev); 905 pci_init_w1cmask(pci_dev); 906 if (pc->is_bridge) { 907 pci_init_mask_bridge(pci_dev); 908 } 909 pci_init_multifunction(bus, pci_dev, &local_err); 910 if (local_err) { 911 error_propagate(errp, local_err); 912 do_pci_unregister_device(pci_dev); 913 return NULL; 914 } 915 916 if (!config_read) 917 config_read = pci_default_read_config; 918 if (!config_write) 919 config_write = pci_default_write_config; 920 pci_dev->config_read = config_read; 921 pci_dev->config_write = config_write; 922 bus->devices[devfn] = pci_dev; 923 pci_dev->version_id = 2; /* Current pci device vmstate version */ 924 return pci_dev; 925 } 926 927 static void pci_unregister_io_regions(PCIDevice *pci_dev) 928 { 929 PCIIORegion *r; 930 int i; 931 932 for(i = 0; i < PCI_NUM_REGIONS; i++) { 933 r = &pci_dev->io_regions[i]; 934 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 935 continue; 936 memory_region_del_subregion(r->address_space, r->memory); 937 } 938 939 pci_unregister_vga(pci_dev); 940 } 941 942 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 943 { 944 PCIDevice *pci_dev = PCI_DEVICE(dev); 945 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 946 947 pci_unregister_io_regions(pci_dev); 948 pci_del_option_rom(pci_dev); 949 950 if (pc->exit) { 951 pc->exit(pci_dev); 952 } 953 954 do_pci_unregister_device(pci_dev); 955 } 956 957 void pci_register_bar(PCIDevice *pci_dev, int region_num, 958 uint8_t type, MemoryRegion *memory) 959 { 960 PCIIORegion *r; 961 uint32_t addr; 962 uint64_t wmask; 963 pcibus_t size = memory_region_size(memory); 964 965 assert(region_num >= 0); 966 assert(region_num < PCI_NUM_REGIONS); 967 if (size & (size-1)) { 968 fprintf(stderr, "ERROR: PCI region size must be pow2 " 969 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 970 exit(1); 971 } 972 973 r = &pci_dev->io_regions[region_num]; 974 r->addr = PCI_BAR_UNMAPPED; 975 r->size = size; 976 r->type = type; 977 r->memory = NULL; 978 979 wmask = ~(size - 1); 980 addr = pci_bar(pci_dev, region_num); 981 if (region_num == PCI_ROM_SLOT) { 982 /* ROM enable bit is writable */ 983 wmask |= PCI_ROM_ADDRESS_ENABLE; 984 } 985 pci_set_long(pci_dev->config + addr, type); 986 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 987 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 988 pci_set_quad(pci_dev->wmask + addr, wmask); 989 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 990 } else { 991 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 992 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 993 } 994 pci_dev->io_regions[region_num].memory = memory; 995 pci_dev->io_regions[region_num].address_space 996 = type & PCI_BASE_ADDRESS_SPACE_IO 997 ? pci_dev->bus->address_space_io 998 : pci_dev->bus->address_space_mem; 999 } 1000 1001 static void pci_update_vga(PCIDevice *pci_dev) 1002 { 1003 uint16_t cmd; 1004 1005 if (!pci_dev->has_vga) { 1006 return; 1007 } 1008 1009 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1010 1011 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1012 cmd & PCI_COMMAND_MEMORY); 1013 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1014 cmd & PCI_COMMAND_IO); 1015 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1016 cmd & PCI_COMMAND_IO); 1017 } 1018 1019 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1020 MemoryRegion *io_lo, MemoryRegion *io_hi) 1021 { 1022 assert(!pci_dev->has_vga); 1023 1024 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1025 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1026 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1027 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1028 1029 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1030 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1031 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1032 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1033 1034 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1035 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1036 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1037 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1038 pci_dev->has_vga = true; 1039 1040 pci_update_vga(pci_dev); 1041 } 1042 1043 void pci_unregister_vga(PCIDevice *pci_dev) 1044 { 1045 if (!pci_dev->has_vga) { 1046 return; 1047 } 1048 1049 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1050 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1051 memory_region_del_subregion(pci_dev->bus->address_space_io, 1052 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1053 memory_region_del_subregion(pci_dev->bus->address_space_io, 1054 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1055 pci_dev->has_vga = false; 1056 } 1057 1058 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1059 { 1060 return pci_dev->io_regions[region_num].addr; 1061 } 1062 1063 static pcibus_t pci_bar_address(PCIDevice *d, 1064 int reg, uint8_t type, pcibus_t size) 1065 { 1066 pcibus_t new_addr, last_addr; 1067 int bar = pci_bar(d, reg); 1068 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1069 Object *machine = qdev_get_machine(); 1070 ObjectClass *oc = object_get_class(machine); 1071 MachineClass *mc = MACHINE_CLASS(oc); 1072 bool allow_0_address = mc->pci_allow_0_address; 1073 1074 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1075 if (!(cmd & PCI_COMMAND_IO)) { 1076 return PCI_BAR_UNMAPPED; 1077 } 1078 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1079 last_addr = new_addr + size - 1; 1080 /* Check if 32 bit BAR wraps around explicitly. 1081 * TODO: make priorities correct and remove this work around. 1082 */ 1083 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1084 (!allow_0_address && new_addr == 0)) { 1085 return PCI_BAR_UNMAPPED; 1086 } 1087 return new_addr; 1088 } 1089 1090 if (!(cmd & PCI_COMMAND_MEMORY)) { 1091 return PCI_BAR_UNMAPPED; 1092 } 1093 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1094 new_addr = pci_get_quad(d->config + bar); 1095 } else { 1096 new_addr = pci_get_long(d->config + bar); 1097 } 1098 /* the ROM slot has a specific enable bit */ 1099 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1100 return PCI_BAR_UNMAPPED; 1101 } 1102 new_addr &= ~(size - 1); 1103 last_addr = new_addr + size - 1; 1104 /* NOTE: we do not support wrapping */ 1105 /* XXX: as we cannot support really dynamic 1106 mappings, we handle specific values as invalid 1107 mappings. */ 1108 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1109 (!allow_0_address && new_addr == 0)) { 1110 return PCI_BAR_UNMAPPED; 1111 } 1112 1113 /* Now pcibus_t is 64bit. 1114 * Check if 32 bit BAR wraps around explicitly. 1115 * Without this, PC ide doesn't work well. 1116 * TODO: remove this work around. 1117 */ 1118 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1119 return PCI_BAR_UNMAPPED; 1120 } 1121 1122 /* 1123 * OS is allowed to set BAR beyond its addressable 1124 * bits. For example, 32 bit OS can set 64bit bar 1125 * to >4G. Check it. TODO: we might need to support 1126 * it in the future for e.g. PAE. 1127 */ 1128 if (last_addr >= HWADDR_MAX) { 1129 return PCI_BAR_UNMAPPED; 1130 } 1131 1132 return new_addr; 1133 } 1134 1135 static void pci_update_mappings(PCIDevice *d) 1136 { 1137 PCIIORegion *r; 1138 int i; 1139 pcibus_t new_addr; 1140 1141 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1142 r = &d->io_regions[i]; 1143 1144 /* this region isn't registered */ 1145 if (!r->size) 1146 continue; 1147 1148 new_addr = pci_bar_address(d, i, r->type, r->size); 1149 1150 /* This bar isn't changed */ 1151 if (new_addr == r->addr) 1152 continue; 1153 1154 /* now do the real mapping */ 1155 if (r->addr != PCI_BAR_UNMAPPED) { 1156 trace_pci_update_mappings_del(d, pci_bus_num(d->bus), 1157 PCI_SLOT(d->devfn), 1158 PCI_FUNC(d->devfn), 1159 i, r->addr, r->size); 1160 memory_region_del_subregion(r->address_space, r->memory); 1161 } 1162 r->addr = new_addr; 1163 if (r->addr != PCI_BAR_UNMAPPED) { 1164 trace_pci_update_mappings_add(d, pci_bus_num(d->bus), 1165 PCI_SLOT(d->devfn), 1166 PCI_FUNC(d->devfn), 1167 i, r->addr, r->size); 1168 memory_region_add_subregion_overlap(r->address_space, 1169 r->addr, r->memory, 1); 1170 } 1171 } 1172 1173 pci_update_vga(d); 1174 } 1175 1176 static inline int pci_irq_disabled(PCIDevice *d) 1177 { 1178 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1179 } 1180 1181 /* Called after interrupt disabled field update in config space, 1182 * assert/deassert interrupts if necessary. 1183 * Gets original interrupt disable bit value (before update). */ 1184 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1185 { 1186 int i, disabled = pci_irq_disabled(d); 1187 if (disabled == was_irq_disabled) 1188 return; 1189 for (i = 0; i < PCI_NUM_PINS; ++i) { 1190 int state = pci_irq_state(d, i); 1191 pci_change_irq_level(d, i, disabled ? -state : state); 1192 } 1193 } 1194 1195 uint32_t pci_default_read_config(PCIDevice *d, 1196 uint32_t address, int len) 1197 { 1198 uint32_t val = 0; 1199 1200 memcpy(&val, d->config + address, len); 1201 return le32_to_cpu(val); 1202 } 1203 1204 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1205 { 1206 int i, was_irq_disabled = pci_irq_disabled(d); 1207 uint32_t val = val_in; 1208 1209 for (i = 0; i < l; val >>= 8, ++i) { 1210 uint8_t wmask = d->wmask[addr + i]; 1211 uint8_t w1cmask = d->w1cmask[addr + i]; 1212 assert(!(wmask & w1cmask)); 1213 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1214 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1215 } 1216 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1217 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1218 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1219 range_covers_byte(addr, l, PCI_COMMAND)) 1220 pci_update_mappings(d); 1221 1222 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1223 pci_update_irq_disabled(d, was_irq_disabled); 1224 memory_region_set_enabled(&d->bus_master_enable_region, 1225 pci_get_word(d->config + PCI_COMMAND) 1226 & PCI_COMMAND_MASTER); 1227 } 1228 1229 msi_write_config(d, addr, val_in, l); 1230 msix_write_config(d, addr, val_in, l); 1231 } 1232 1233 /***********************************************************/ 1234 /* generic PCI irq support */ 1235 1236 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1237 static void pci_irq_handler(void *opaque, int irq_num, int level) 1238 { 1239 PCIDevice *pci_dev = opaque; 1240 int change; 1241 1242 change = level - pci_irq_state(pci_dev, irq_num); 1243 if (!change) 1244 return; 1245 1246 pci_set_irq_state(pci_dev, irq_num, level); 1247 pci_update_irq_status(pci_dev); 1248 if (pci_irq_disabled(pci_dev)) 1249 return; 1250 pci_change_irq_level(pci_dev, irq_num, change); 1251 } 1252 1253 static inline int pci_intx(PCIDevice *pci_dev) 1254 { 1255 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1256 } 1257 1258 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1259 { 1260 int intx = pci_intx(pci_dev); 1261 1262 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1263 } 1264 1265 void pci_set_irq(PCIDevice *pci_dev, int level) 1266 { 1267 int intx = pci_intx(pci_dev); 1268 pci_irq_handler(pci_dev, intx, level); 1269 } 1270 1271 /* Special hooks used by device assignment */ 1272 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1273 { 1274 assert(pci_bus_is_root(bus)); 1275 bus->route_intx_to_irq = route_intx_to_irq; 1276 } 1277 1278 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1279 { 1280 PCIBus *bus; 1281 1282 do { 1283 bus = dev->bus; 1284 pin = bus->map_irq(dev, pin); 1285 dev = bus->parent_dev; 1286 } while (dev); 1287 1288 if (!bus->route_intx_to_irq) { 1289 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1290 object_get_typename(OBJECT(bus->qbus.parent))); 1291 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1292 } 1293 1294 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1295 } 1296 1297 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1298 { 1299 return old->mode != new->mode || old->irq != new->irq; 1300 } 1301 1302 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1303 { 1304 PCIDevice *dev; 1305 PCIBus *sec; 1306 int i; 1307 1308 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1309 dev = bus->devices[i]; 1310 if (dev && dev->intx_routing_notifier) { 1311 dev->intx_routing_notifier(dev); 1312 } 1313 } 1314 1315 QLIST_FOREACH(sec, &bus->child, sibling) { 1316 pci_bus_fire_intx_routing_notifier(sec); 1317 } 1318 } 1319 1320 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1321 PCIINTxRoutingNotifier notifier) 1322 { 1323 dev->intx_routing_notifier = notifier; 1324 } 1325 1326 /* 1327 * PCI-to-PCI bridge specification 1328 * 9.1: Interrupt routing. Table 9-1 1329 * 1330 * the PCI Express Base Specification, Revision 2.1 1331 * 2.2.8.1: INTx interrutp signaling - Rules 1332 * the Implementation Note 1333 * Table 2-20 1334 */ 1335 /* 1336 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1337 * 0-origin unlike PCI interrupt pin register. 1338 */ 1339 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1340 { 1341 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1342 } 1343 1344 /***********************************************************/ 1345 /* monitor info on PCI */ 1346 1347 typedef struct { 1348 uint16_t class; 1349 const char *desc; 1350 const char *fw_name; 1351 uint16_t fw_ign_bits; 1352 } pci_class_desc; 1353 1354 static const pci_class_desc pci_class_descriptions[] = 1355 { 1356 { 0x0001, "VGA controller", "display"}, 1357 { 0x0100, "SCSI controller", "scsi"}, 1358 { 0x0101, "IDE controller", "ide"}, 1359 { 0x0102, "Floppy controller", "fdc"}, 1360 { 0x0103, "IPI controller", "ipi"}, 1361 { 0x0104, "RAID controller", "raid"}, 1362 { 0x0106, "SATA controller"}, 1363 { 0x0107, "SAS controller"}, 1364 { 0x0180, "Storage controller"}, 1365 { 0x0200, "Ethernet controller", "ethernet"}, 1366 { 0x0201, "Token Ring controller", "token-ring"}, 1367 { 0x0202, "FDDI controller", "fddi"}, 1368 { 0x0203, "ATM controller", "atm"}, 1369 { 0x0280, "Network controller"}, 1370 { 0x0300, "VGA controller", "display", 0x00ff}, 1371 { 0x0301, "XGA controller"}, 1372 { 0x0302, "3D controller"}, 1373 { 0x0380, "Display controller"}, 1374 { 0x0400, "Video controller", "video"}, 1375 { 0x0401, "Audio controller", "sound"}, 1376 { 0x0402, "Phone"}, 1377 { 0x0403, "Audio controller", "sound"}, 1378 { 0x0480, "Multimedia controller"}, 1379 { 0x0500, "RAM controller", "memory"}, 1380 { 0x0501, "Flash controller", "flash"}, 1381 { 0x0580, "Memory controller"}, 1382 { 0x0600, "Host bridge", "host"}, 1383 { 0x0601, "ISA bridge", "isa"}, 1384 { 0x0602, "EISA bridge", "eisa"}, 1385 { 0x0603, "MC bridge", "mca"}, 1386 { 0x0604, "PCI bridge", "pci-bridge"}, 1387 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1388 { 0x0606, "NUBUS bridge", "nubus"}, 1389 { 0x0607, "CARDBUS bridge", "cardbus"}, 1390 { 0x0608, "RACEWAY bridge"}, 1391 { 0x0680, "Bridge"}, 1392 { 0x0700, "Serial port", "serial"}, 1393 { 0x0701, "Parallel port", "parallel"}, 1394 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1395 { 0x0801, "DMA controller", "dma-controller"}, 1396 { 0x0802, "Timer", "timer"}, 1397 { 0x0803, "RTC", "rtc"}, 1398 { 0x0900, "Keyboard", "keyboard"}, 1399 { 0x0901, "Pen", "pen"}, 1400 { 0x0902, "Mouse", "mouse"}, 1401 { 0x0A00, "Dock station", "dock", 0x00ff}, 1402 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1403 { 0x0c00, "Fireware contorller", "fireware"}, 1404 { 0x0c01, "Access bus controller", "access-bus"}, 1405 { 0x0c02, "SSA controller", "ssa"}, 1406 { 0x0c03, "USB controller", "usb"}, 1407 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1408 { 0x0c05, "SMBus"}, 1409 { 0, NULL} 1410 }; 1411 1412 static void pci_for_each_device_under_bus(PCIBus *bus, 1413 void (*fn)(PCIBus *b, PCIDevice *d, 1414 void *opaque), 1415 void *opaque) 1416 { 1417 PCIDevice *d; 1418 int devfn; 1419 1420 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1421 d = bus->devices[devfn]; 1422 if (d) { 1423 fn(bus, d, opaque); 1424 } 1425 } 1426 } 1427 1428 void pci_for_each_device(PCIBus *bus, int bus_num, 1429 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1430 void *opaque) 1431 { 1432 bus = pci_find_bus_nr(bus, bus_num); 1433 1434 if (bus) { 1435 pci_for_each_device_under_bus(bus, fn, opaque); 1436 } 1437 } 1438 1439 static const pci_class_desc *get_class_desc(int class) 1440 { 1441 const pci_class_desc *desc; 1442 1443 desc = pci_class_descriptions; 1444 while (desc->desc && class != desc->class) { 1445 desc++; 1446 } 1447 1448 return desc; 1449 } 1450 1451 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1452 1453 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1454 { 1455 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1456 int i; 1457 1458 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1459 const PCIIORegion *r = &dev->io_regions[i]; 1460 PciMemoryRegionList *region; 1461 1462 if (!r->size) { 1463 continue; 1464 } 1465 1466 region = g_malloc0(sizeof(*region)); 1467 region->value = g_malloc0(sizeof(*region->value)); 1468 1469 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1470 region->value->type = g_strdup("io"); 1471 } else { 1472 region->value->type = g_strdup("memory"); 1473 region->value->has_prefetch = true; 1474 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1475 region->value->has_mem_type_64 = true; 1476 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1477 } 1478 1479 region->value->bar = i; 1480 region->value->address = r->addr; 1481 region->value->size = r->size; 1482 1483 /* XXX: waiting for the qapi to support GSList */ 1484 if (!cur_item) { 1485 head = cur_item = region; 1486 } else { 1487 cur_item->next = region; 1488 cur_item = region; 1489 } 1490 } 1491 1492 return head; 1493 } 1494 1495 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1496 int bus_num) 1497 { 1498 PciBridgeInfo *info; 1499 PciMemoryRange *range; 1500 1501 info = g_new0(PciBridgeInfo, 1); 1502 1503 info->bus = g_new0(PciBusInfo, 1); 1504 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1505 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1506 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1507 1508 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1509 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1510 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1511 1512 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1513 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1514 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1515 1516 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1517 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1518 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1519 1520 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1521 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1522 if (child_bus) { 1523 info->has_devices = true; 1524 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1525 } 1526 } 1527 1528 return info; 1529 } 1530 1531 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1532 int bus_num) 1533 { 1534 const pci_class_desc *desc; 1535 PciDeviceInfo *info; 1536 uint8_t type; 1537 int class; 1538 1539 info = g_new0(PciDeviceInfo, 1); 1540 info->bus = bus_num; 1541 info->slot = PCI_SLOT(dev->devfn); 1542 info->function = PCI_FUNC(dev->devfn); 1543 1544 info->class_info = g_new0(PciDeviceClass, 1); 1545 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1546 info->class_info->q_class = class; 1547 desc = get_class_desc(class); 1548 if (desc->desc) { 1549 info->class_info->has_desc = true; 1550 info->class_info->desc = g_strdup(desc->desc); 1551 } 1552 1553 info->id = g_new0(PciDeviceId, 1); 1554 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1555 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1556 info->regions = qmp_query_pci_regions(dev); 1557 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1558 1559 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1560 info->has_irq = true; 1561 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1562 } 1563 1564 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1565 if (type == PCI_HEADER_TYPE_BRIDGE) { 1566 info->has_pci_bridge = true; 1567 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1568 } 1569 1570 return info; 1571 } 1572 1573 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1574 { 1575 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1576 PCIDevice *dev; 1577 int devfn; 1578 1579 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1580 dev = bus->devices[devfn]; 1581 if (dev) { 1582 info = g_malloc0(sizeof(*info)); 1583 info->value = qmp_query_pci_device(dev, bus, bus_num); 1584 1585 /* XXX: waiting for the qapi to support GSList */ 1586 if (!cur_item) { 1587 head = cur_item = info; 1588 } else { 1589 cur_item->next = info; 1590 cur_item = info; 1591 } 1592 } 1593 } 1594 1595 return head; 1596 } 1597 1598 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1599 { 1600 PciInfo *info = NULL; 1601 1602 bus = pci_find_bus_nr(bus, bus_num); 1603 if (bus) { 1604 info = g_malloc0(sizeof(*info)); 1605 info->bus = bus_num; 1606 info->devices = qmp_query_pci_devices(bus, bus_num); 1607 } 1608 1609 return info; 1610 } 1611 1612 PciInfoList *qmp_query_pci(Error **errp) 1613 { 1614 PciInfoList *info, *head = NULL, *cur_item = NULL; 1615 PCIHostState *host_bridge; 1616 1617 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1618 info = g_malloc0(sizeof(*info)); 1619 info->value = qmp_query_pci_bus(host_bridge->bus, 1620 pci_bus_num(host_bridge->bus)); 1621 1622 /* XXX: waiting for the qapi to support GSList */ 1623 if (!cur_item) { 1624 head = cur_item = info; 1625 } else { 1626 cur_item->next = info; 1627 cur_item = info; 1628 } 1629 } 1630 1631 return head; 1632 } 1633 1634 static const char * const pci_nic_models[] = { 1635 "ne2k_pci", 1636 "i82551", 1637 "i82557b", 1638 "i82559er", 1639 "rtl8139", 1640 "e1000", 1641 "pcnet", 1642 "virtio", 1643 NULL 1644 }; 1645 1646 static const char * const pci_nic_names[] = { 1647 "ne2k_pci", 1648 "i82551", 1649 "i82557b", 1650 "i82559er", 1651 "rtl8139", 1652 "e1000", 1653 "pcnet", 1654 "virtio-net-pci", 1655 NULL 1656 }; 1657 1658 /* Initialize a PCI NIC. */ 1659 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1660 const char *default_model, 1661 const char *default_devaddr) 1662 { 1663 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1664 Error *err = NULL; 1665 PCIBus *bus; 1666 PCIDevice *pci_dev; 1667 DeviceState *dev; 1668 int devfn; 1669 int i; 1670 1671 if (qemu_show_nic_models(nd->model, pci_nic_models)) { 1672 exit(0); 1673 } 1674 1675 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1676 if (i < 0) { 1677 exit(1); 1678 } 1679 1680 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1681 if (!bus) { 1682 error_report("Invalid PCI device address %s for device %s", 1683 devaddr, pci_nic_names[i]); 1684 exit(1); 1685 } 1686 1687 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1688 dev = &pci_dev->qdev; 1689 qdev_set_nic_properties(dev, nd); 1690 1691 object_property_set_bool(OBJECT(dev), true, "realized", &err); 1692 if (err) { 1693 error_report_err(err); 1694 object_unparent(OBJECT(dev)); 1695 exit(1); 1696 } 1697 1698 return pci_dev; 1699 } 1700 1701 PCIDevice *pci_vga_init(PCIBus *bus) 1702 { 1703 switch (vga_interface_type) { 1704 case VGA_CIRRUS: 1705 return pci_create_simple(bus, -1, "cirrus-vga"); 1706 case VGA_QXL: 1707 return pci_create_simple(bus, -1, "qxl-vga"); 1708 case VGA_STD: 1709 return pci_create_simple(bus, -1, "VGA"); 1710 case VGA_VMWARE: 1711 return pci_create_simple(bus, -1, "vmware-svga"); 1712 case VGA_VIRTIO: 1713 return pci_create_simple(bus, -1, "virtio-vga"); 1714 case VGA_NONE: 1715 default: /* Other non-PCI types. Checking for unsupported types is already 1716 done in vl.c. */ 1717 return NULL; 1718 } 1719 } 1720 1721 /* Whether a given bus number is in range of the secondary 1722 * bus of the given bridge device. */ 1723 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1724 { 1725 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1726 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1727 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1728 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1729 } 1730 1731 /* Whether a given bus number is in a range of a root bus */ 1732 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1733 { 1734 int i; 1735 1736 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1737 PCIDevice *dev = bus->devices[i]; 1738 1739 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1740 if (pci_secondary_bus_in_range(dev, bus_num)) { 1741 return true; 1742 } 1743 } 1744 } 1745 1746 return false; 1747 } 1748 1749 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1750 { 1751 PCIBus *sec; 1752 1753 if (!bus) { 1754 return NULL; 1755 } 1756 1757 if (pci_bus_num(bus) == bus_num) { 1758 return bus; 1759 } 1760 1761 /* Consider all bus numbers in range for the host pci bridge. */ 1762 if (!pci_bus_is_root(bus) && 1763 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1764 return NULL; 1765 } 1766 1767 /* try child bus */ 1768 for (; bus; bus = sec) { 1769 QLIST_FOREACH(sec, &bus->child, sibling) { 1770 if (pci_bus_num(sec) == bus_num) { 1771 return sec; 1772 } 1773 /* PXB buses assumed to be children of bus 0 */ 1774 if (pci_bus_is_root(sec)) { 1775 if (pci_root_bus_in_range(sec, bus_num)) { 1776 break; 1777 } 1778 } else { 1779 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1780 break; 1781 } 1782 } 1783 } 1784 } 1785 1786 return NULL; 1787 } 1788 1789 void pci_for_each_bus_depth_first(PCIBus *bus, 1790 void *(*begin)(PCIBus *bus, void *parent_state), 1791 void (*end)(PCIBus *bus, void *state), 1792 void *parent_state) 1793 { 1794 PCIBus *sec; 1795 void *state; 1796 1797 if (!bus) { 1798 return; 1799 } 1800 1801 if (begin) { 1802 state = begin(bus, parent_state); 1803 } else { 1804 state = parent_state; 1805 } 1806 1807 QLIST_FOREACH(sec, &bus->child, sibling) { 1808 pci_for_each_bus_depth_first(sec, begin, end, state); 1809 } 1810 1811 if (end) { 1812 end(bus, state); 1813 } 1814 } 1815 1816 1817 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1818 { 1819 bus = pci_find_bus_nr(bus, bus_num); 1820 1821 if (!bus) 1822 return NULL; 1823 1824 return bus->devices[devfn]; 1825 } 1826 1827 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 1828 { 1829 PCIDevice *pci_dev = (PCIDevice *)qdev; 1830 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1831 Error *local_err = NULL; 1832 PCIBus *bus; 1833 bool is_default_rom; 1834 1835 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1836 if (pc->is_express) { 1837 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1838 } 1839 1840 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1841 pci_dev = do_pci_register_device(pci_dev, bus, 1842 object_get_typename(OBJECT(qdev)), 1843 pci_dev->devfn, errp); 1844 if (pci_dev == NULL) 1845 return; 1846 1847 if (pc->realize) { 1848 pc->realize(pci_dev, &local_err); 1849 if (local_err) { 1850 error_propagate(errp, local_err); 1851 do_pci_unregister_device(pci_dev); 1852 return; 1853 } 1854 } 1855 1856 /* rom loading */ 1857 is_default_rom = false; 1858 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1859 pci_dev->romfile = g_strdup(pc->romfile); 1860 is_default_rom = true; 1861 } 1862 1863 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 1864 if (local_err) { 1865 error_propagate(errp, local_err); 1866 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 1867 return; 1868 } 1869 } 1870 1871 static void pci_default_realize(PCIDevice *dev, Error **errp) 1872 { 1873 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1874 1875 if (pc->init) { 1876 if (pc->init(dev) < 0) { 1877 error_setg(errp, "Device initialization failed"); 1878 return; 1879 } 1880 } 1881 } 1882 1883 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1884 const char *name) 1885 { 1886 DeviceState *dev; 1887 1888 dev = qdev_create(&bus->qbus, name); 1889 qdev_prop_set_int32(dev, "addr", devfn); 1890 qdev_prop_set_bit(dev, "multifunction", multifunction); 1891 return PCI_DEVICE(dev); 1892 } 1893 1894 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1895 bool multifunction, 1896 const char *name) 1897 { 1898 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1899 qdev_init_nofail(&dev->qdev); 1900 return dev; 1901 } 1902 1903 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1904 { 1905 return pci_create_multifunction(bus, devfn, false, name); 1906 } 1907 1908 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1909 { 1910 return pci_create_simple_multifunction(bus, devfn, false, name); 1911 } 1912 1913 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1914 { 1915 int offset = PCI_CONFIG_HEADER_SIZE; 1916 int i; 1917 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1918 if (pdev->used[i]) 1919 offset = i + 1; 1920 else if (i - offset + 1 == size) 1921 return offset; 1922 } 1923 return 0; 1924 } 1925 1926 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1927 uint8_t *prev_p) 1928 { 1929 uint8_t next, prev; 1930 1931 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1932 return 0; 1933 1934 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1935 prev = next + PCI_CAP_LIST_NEXT) 1936 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1937 break; 1938 1939 if (prev_p) 1940 *prev_p = prev; 1941 return next; 1942 } 1943 1944 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1945 { 1946 uint8_t next, prev, found = 0; 1947 1948 if (!(pdev->used[offset])) { 1949 return 0; 1950 } 1951 1952 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1953 1954 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1955 prev = next + PCI_CAP_LIST_NEXT) { 1956 if (next <= offset && next > found) { 1957 found = next; 1958 } 1959 } 1960 return found; 1961 } 1962 1963 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1964 This is needed for an option rom which is used for more than one device. */ 1965 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1966 { 1967 uint16_t vendor_id; 1968 uint16_t device_id; 1969 uint16_t rom_vendor_id; 1970 uint16_t rom_device_id; 1971 uint16_t rom_magic; 1972 uint16_t pcir_offset; 1973 uint8_t checksum; 1974 1975 /* Words in rom data are little endian (like in PCI configuration), 1976 so they can be read / written with pci_get_word / pci_set_word. */ 1977 1978 /* Only a valid rom will be patched. */ 1979 rom_magic = pci_get_word(ptr); 1980 if (rom_magic != 0xaa55) { 1981 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1982 return; 1983 } 1984 pcir_offset = pci_get_word(ptr + 0x18); 1985 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1986 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1987 return; 1988 } 1989 1990 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1991 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1992 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1993 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1994 1995 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1996 vendor_id, device_id, rom_vendor_id, rom_device_id); 1997 1998 checksum = ptr[6]; 1999 2000 if (vendor_id != rom_vendor_id) { 2001 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2002 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2003 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2004 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2005 ptr[6] = checksum; 2006 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2007 } 2008 2009 if (device_id != rom_device_id) { 2010 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2011 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2012 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2013 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2014 ptr[6] = checksum; 2015 pci_set_word(ptr + pcir_offset + 6, device_id); 2016 } 2017 } 2018 2019 /* Add an option rom for the device */ 2020 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2021 Error **errp) 2022 { 2023 int size; 2024 char *path; 2025 void *ptr; 2026 char name[32]; 2027 const VMStateDescription *vmsd; 2028 2029 if (!pdev->romfile) 2030 return; 2031 if (strlen(pdev->romfile) == 0) 2032 return; 2033 2034 if (!pdev->rom_bar) { 2035 /* 2036 * Load rom via fw_cfg instead of creating a rom bar, 2037 * for 0.11 compatibility. 2038 */ 2039 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2040 2041 /* 2042 * Hot-plugged devices can't use the option ROM 2043 * if the rom bar is disabled. 2044 */ 2045 if (DEVICE(pdev)->hotplugged) { 2046 error_setg(errp, "Hot-plugged device without ROM bar" 2047 " can't have an option ROM"); 2048 return; 2049 } 2050 2051 if (class == 0x0300) { 2052 rom_add_vga(pdev->romfile); 2053 } else { 2054 rom_add_option(pdev->romfile, -1); 2055 } 2056 return; 2057 } 2058 2059 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2060 if (path == NULL) { 2061 path = g_strdup(pdev->romfile); 2062 } 2063 2064 size = get_image_size(path); 2065 if (size < 0) { 2066 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2067 g_free(path); 2068 return; 2069 } else if (size == 0) { 2070 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2071 g_free(path); 2072 return; 2073 } 2074 size = pow2ceil(size); 2075 2076 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2077 2078 if (vmsd) { 2079 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2080 } else { 2081 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2082 } 2083 pdev->has_rom = true; 2084 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort); 2085 vmstate_register_ram(&pdev->rom, &pdev->qdev); 2086 ptr = memory_region_get_ram_ptr(&pdev->rom); 2087 load_image(path, ptr); 2088 g_free(path); 2089 2090 if (is_default_rom) { 2091 /* Only the default rom images will be patched (if needed). */ 2092 pci_patch_ids(pdev, ptr, size); 2093 } 2094 2095 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2096 } 2097 2098 static void pci_del_option_rom(PCIDevice *pdev) 2099 { 2100 if (!pdev->has_rom) 2101 return; 2102 2103 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2104 pdev->has_rom = false; 2105 } 2106 2107 /* 2108 * if offset = 0, 2109 * Find and reserve space and add capability to the linked list 2110 * in pci config space 2111 */ 2112 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2113 uint8_t offset, uint8_t size) 2114 { 2115 int ret; 2116 Error *local_err = NULL; 2117 2118 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err); 2119 if (local_err) { 2120 assert(ret < 0); 2121 error_report_err(local_err); 2122 } else { 2123 /* success implies a positive offset in config space */ 2124 assert(ret > 0); 2125 } 2126 return ret; 2127 } 2128 2129 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 2130 uint8_t offset, uint8_t size, 2131 Error **errp) 2132 { 2133 uint8_t *config; 2134 int i, overlapping_cap; 2135 2136 if (!offset) { 2137 offset = pci_find_space(pdev, size); 2138 if (!offset) { 2139 error_setg(errp, "out of PCI config space"); 2140 return -ENOSPC; 2141 } 2142 } else { 2143 /* Verify that capabilities don't overlap. Note: device assignment 2144 * depends on this check to verify that the device is not broken. 2145 * Should never trigger for emulated devices, but it's helpful 2146 * for debugging these. */ 2147 for (i = offset; i < offset + size; i++) { 2148 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2149 if (overlapping_cap) { 2150 error_setg(errp, "%s:%02x:%02x.%x " 2151 "Attempt to add PCI capability %x at offset " 2152 "%x overlaps existing capability %x at offset %x", 2153 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2154 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2155 cap_id, offset, overlapping_cap, i); 2156 return -EINVAL; 2157 } 2158 } 2159 } 2160 2161 config = pdev->config + offset; 2162 config[PCI_CAP_LIST_ID] = cap_id; 2163 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2164 pdev->config[PCI_CAPABILITY_LIST] = offset; 2165 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2166 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2167 /* Make capability read-only by default */ 2168 memset(pdev->wmask + offset, 0, size); 2169 /* Check capability by default */ 2170 memset(pdev->cmask + offset, 0xFF, size); 2171 return offset; 2172 } 2173 2174 /* Unlink capability from the pci config space. */ 2175 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2176 { 2177 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2178 if (!offset) 2179 return; 2180 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2181 /* Make capability writable again */ 2182 memset(pdev->wmask + offset, 0xff, size); 2183 memset(pdev->w1cmask + offset, 0, size); 2184 /* Clear cmask as device-specific registers can't be checked */ 2185 memset(pdev->cmask + offset, 0, size); 2186 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2187 2188 if (!pdev->config[PCI_CAPABILITY_LIST]) 2189 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2190 } 2191 2192 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2193 { 2194 return pci_find_capability_list(pdev, cap_id, NULL); 2195 } 2196 2197 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2198 { 2199 PCIDevice *d = (PCIDevice *)dev; 2200 const pci_class_desc *desc; 2201 char ctxt[64]; 2202 PCIIORegion *r; 2203 int i, class; 2204 2205 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2206 desc = pci_class_descriptions; 2207 while (desc->desc && class != desc->class) 2208 desc++; 2209 if (desc->desc) { 2210 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2211 } else { 2212 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2213 } 2214 2215 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2216 "pci id %04x:%04x (sub %04x:%04x)\n", 2217 indent, "", ctxt, pci_bus_num(d->bus), 2218 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2219 pci_get_word(d->config + PCI_VENDOR_ID), 2220 pci_get_word(d->config + PCI_DEVICE_ID), 2221 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2222 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2223 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2224 r = &d->io_regions[i]; 2225 if (!r->size) 2226 continue; 2227 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2228 " [0x%"FMT_PCIBUS"]\n", 2229 indent, "", 2230 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2231 r->addr, r->addr + r->size - 1); 2232 } 2233 } 2234 2235 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2236 { 2237 PCIDevice *d = (PCIDevice *)dev; 2238 const char *name = NULL; 2239 const pci_class_desc *desc = pci_class_descriptions; 2240 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2241 2242 while (desc->desc && 2243 (class & ~desc->fw_ign_bits) != 2244 (desc->class & ~desc->fw_ign_bits)) { 2245 desc++; 2246 } 2247 2248 if (desc->desc) { 2249 name = desc->fw_name; 2250 } 2251 2252 if (name) { 2253 pstrcpy(buf, len, name); 2254 } else { 2255 snprintf(buf, len, "pci%04x,%04x", 2256 pci_get_word(d->config + PCI_VENDOR_ID), 2257 pci_get_word(d->config + PCI_DEVICE_ID)); 2258 } 2259 2260 return buf; 2261 } 2262 2263 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2264 { 2265 PCIDevice *d = (PCIDevice *)dev; 2266 char path[50], name[33]; 2267 int off; 2268 2269 off = snprintf(path, sizeof(path), "%s@%x", 2270 pci_dev_fw_name(dev, name, sizeof name), 2271 PCI_SLOT(d->devfn)); 2272 if (PCI_FUNC(d->devfn)) 2273 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2274 return g_strdup(path); 2275 } 2276 2277 static char *pcibus_get_dev_path(DeviceState *dev) 2278 { 2279 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2280 PCIDevice *t; 2281 int slot_depth; 2282 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2283 * 00 is added here to make this format compatible with 2284 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2285 * Slot.Function list specifies the slot and function numbers for all 2286 * devices on the path from root to the specific device. */ 2287 const char *root_bus_path; 2288 int root_bus_len; 2289 char slot[] = ":SS.F"; 2290 int slot_len = sizeof slot - 1 /* For '\0' */; 2291 int path_len; 2292 char *path, *p; 2293 int s; 2294 2295 root_bus_path = pci_root_bus_path(d); 2296 root_bus_len = strlen(root_bus_path); 2297 2298 /* Calculate # of slots on path between device and root. */; 2299 slot_depth = 0; 2300 for (t = d; t; t = t->bus->parent_dev) { 2301 ++slot_depth; 2302 } 2303 2304 path_len = root_bus_len + slot_len * slot_depth; 2305 2306 /* Allocate memory, fill in the terminating null byte. */ 2307 path = g_malloc(path_len + 1 /* For '\0' */); 2308 path[path_len] = '\0'; 2309 2310 memcpy(path, root_bus_path, root_bus_len); 2311 2312 /* Fill in slot numbers. We walk up from device to root, so need to print 2313 * them in the reverse order, last to first. */ 2314 p = path + path_len; 2315 for (t = d; t; t = t->bus->parent_dev) { 2316 p -= slot_len; 2317 s = snprintf(slot, sizeof slot, ":%02x.%x", 2318 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2319 assert(s == slot_len); 2320 memcpy(p, slot, slot_len); 2321 } 2322 2323 return path; 2324 } 2325 2326 static int pci_qdev_find_recursive(PCIBus *bus, 2327 const char *id, PCIDevice **pdev) 2328 { 2329 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2330 if (!qdev) { 2331 return -ENODEV; 2332 } 2333 2334 /* roughly check if given qdev is pci device */ 2335 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2336 *pdev = PCI_DEVICE(qdev); 2337 return 0; 2338 } 2339 return -EINVAL; 2340 } 2341 2342 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2343 { 2344 PCIHostState *host_bridge; 2345 int rc = -ENODEV; 2346 2347 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2348 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2349 if (!tmp) { 2350 rc = 0; 2351 break; 2352 } 2353 if (tmp != -ENODEV) { 2354 rc = tmp; 2355 } 2356 } 2357 2358 return rc; 2359 } 2360 2361 MemoryRegion *pci_address_space(PCIDevice *dev) 2362 { 2363 return dev->bus->address_space_mem; 2364 } 2365 2366 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2367 { 2368 return dev->bus->address_space_io; 2369 } 2370 2371 static void pci_device_class_init(ObjectClass *klass, void *data) 2372 { 2373 DeviceClass *k = DEVICE_CLASS(klass); 2374 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 2375 2376 k->realize = pci_qdev_realize; 2377 k->unrealize = pci_qdev_unrealize; 2378 k->bus_type = TYPE_PCI_BUS; 2379 k->props = pci_props; 2380 pc->realize = pci_default_realize; 2381 } 2382 2383 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2384 { 2385 PCIBus *bus = PCI_BUS(dev->bus); 2386 PCIBus *iommu_bus = bus; 2387 2388 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2389 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus); 2390 } 2391 if (iommu_bus && iommu_bus->iommu_fn) { 2392 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2393 } 2394 return &address_space_memory; 2395 } 2396 2397 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2398 { 2399 bus->iommu_fn = fn; 2400 bus->iommu_opaque = opaque; 2401 } 2402 2403 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2404 { 2405 Range *range = opaque; 2406 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2407 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2408 int i; 2409 2410 if (!(cmd & PCI_COMMAND_MEMORY)) { 2411 return; 2412 } 2413 2414 if (pc->is_bridge) { 2415 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2416 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2417 2418 base = MAX(base, 0x1ULL << 32); 2419 2420 if (limit >= base) { 2421 Range pref_range; 2422 pref_range.begin = base; 2423 pref_range.end = limit + 1; 2424 range_extend(range, &pref_range); 2425 } 2426 } 2427 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2428 PCIIORegion *r = &dev->io_regions[i]; 2429 Range region_range; 2430 2431 if (!r->size || 2432 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2433 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2434 continue; 2435 } 2436 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2437 region_range.end = region_range.begin + r->size; 2438 2439 if (region_range.begin == PCI_BAR_UNMAPPED) { 2440 continue; 2441 } 2442 2443 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2444 2445 if (region_range.end - 1 >= region_range.begin) { 2446 range_extend(range, ®ion_range); 2447 } 2448 } 2449 } 2450 2451 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2452 { 2453 range->begin = range->end = 0; 2454 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2455 } 2456 2457 static const TypeInfo pci_device_type_info = { 2458 .name = TYPE_PCI_DEVICE, 2459 .parent = TYPE_DEVICE, 2460 .instance_size = sizeof(PCIDevice), 2461 .abstract = true, 2462 .class_size = sizeof(PCIDeviceClass), 2463 .class_init = pci_device_class_init, 2464 }; 2465 2466 static void pci_register_types(void) 2467 { 2468 type_register_static(&pci_bus_info); 2469 type_register_static(&pcie_bus_info); 2470 type_register_static(&pci_device_type_info); 2471 } 2472 2473 type_init(pci_register_types) 2474