1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/qemu-file-types.h" 35 #include "migration/vmstate.h" 36 #include "monitor/monitor.h" 37 #include "net/net.h" 38 #include "sysemu/numa.h" 39 #include "sysemu/sysemu.h" 40 #include "hw/loader.h" 41 #include "qemu/error-report.h" 42 #include "qemu/range.h" 43 #include "trace.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci/msix.h" 46 #include "exec/address-spaces.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "qapi/error.h" 50 #include "qapi/qapi-commands-pci.h" 51 #include "qemu/cutils.h" 52 53 //#define DEBUG_PCI 54 #ifdef DEBUG_PCI 55 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 56 #else 57 # define PCI_DPRINTF(format, ...) do { } while (0) 58 #endif 59 60 bool pci_available = true; 61 62 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 63 static char *pcibus_get_dev_path(DeviceState *dev); 64 static char *pcibus_get_fw_dev_path(DeviceState *dev); 65 static void pcibus_reset(BusState *qbus); 66 67 static Property pci_props[] = { 68 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 69 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 70 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 71 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 72 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 73 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 74 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 75 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 76 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 77 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 78 failover_pair_id), 79 DEFINE_PROP_END_OF_LIST() 80 }; 81 82 static const VMStateDescription vmstate_pcibus = { 83 .name = "PCIBUS", 84 .version_id = 1, 85 .minimum_version_id = 1, 86 .fields = (VMStateField[]) { 87 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 89 nirq, 0, vmstate_info_int32, 90 int32_t), 91 VMSTATE_END_OF_LIST() 92 } 93 }; 94 95 static void pci_init_bus_master(PCIDevice *pci_dev) 96 { 97 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 98 99 memory_region_init_alias(&pci_dev->bus_master_enable_region, 100 OBJECT(pci_dev), "bus master", 101 dma_as->root, 0, memory_region_size(dma_as->root)); 102 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 103 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 104 &pci_dev->bus_master_enable_region); 105 } 106 107 static void pcibus_machine_done(Notifier *notifier, void *data) 108 { 109 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 110 int i; 111 112 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 113 if (bus->devices[i]) { 114 pci_init_bus_master(bus->devices[i]); 115 } 116 } 117 } 118 119 static void pci_bus_realize(BusState *qbus, Error **errp) 120 { 121 PCIBus *bus = PCI_BUS(qbus); 122 123 bus->machine_done.notify = pcibus_machine_done; 124 qemu_add_machine_init_done_notifier(&bus->machine_done); 125 126 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 127 } 128 129 static void pcie_bus_realize(BusState *qbus, Error **errp) 130 { 131 PCIBus *bus = PCI_BUS(qbus); 132 133 pci_bus_realize(qbus, errp); 134 135 /* 136 * A PCI-E bus can support extended config space if it's the root 137 * bus, or if the bus/bridge above it does as well 138 */ 139 if (pci_bus_is_root(bus)) { 140 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 141 } else { 142 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 143 144 if (pci_bus_allows_extended_config_space(parent_bus)) { 145 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 146 } 147 } 148 } 149 150 static void pci_bus_unrealize(BusState *qbus) 151 { 152 PCIBus *bus = PCI_BUS(qbus); 153 154 qemu_remove_machine_init_done_notifier(&bus->machine_done); 155 156 vmstate_unregister(NULL, &vmstate_pcibus, bus); 157 } 158 159 static int pcibus_num(PCIBus *bus) 160 { 161 if (pci_bus_is_root(bus)) { 162 return 0; /* pci host bridge */ 163 } 164 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 165 } 166 167 static uint16_t pcibus_numa_node(PCIBus *bus) 168 { 169 return NUMA_NODE_UNASSIGNED; 170 } 171 172 static void pci_bus_class_init(ObjectClass *klass, void *data) 173 { 174 BusClass *k = BUS_CLASS(klass); 175 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 176 177 k->print_dev = pcibus_dev_print; 178 k->get_dev_path = pcibus_get_dev_path; 179 k->get_fw_dev_path = pcibus_get_fw_dev_path; 180 k->realize = pci_bus_realize; 181 k->unrealize = pci_bus_unrealize; 182 k->reset = pcibus_reset; 183 184 pbc->bus_num = pcibus_num; 185 pbc->numa_node = pcibus_numa_node; 186 } 187 188 static const TypeInfo pci_bus_info = { 189 .name = TYPE_PCI_BUS, 190 .parent = TYPE_BUS, 191 .instance_size = sizeof(PCIBus), 192 .class_size = sizeof(PCIBusClass), 193 .class_init = pci_bus_class_init, 194 }; 195 196 static const TypeInfo pcie_interface_info = { 197 .name = INTERFACE_PCIE_DEVICE, 198 .parent = TYPE_INTERFACE, 199 }; 200 201 static const TypeInfo conventional_pci_interface_info = { 202 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 203 .parent = TYPE_INTERFACE, 204 }; 205 206 static void pcie_bus_class_init(ObjectClass *klass, void *data) 207 { 208 BusClass *k = BUS_CLASS(klass); 209 210 k->realize = pcie_bus_realize; 211 } 212 213 static const TypeInfo pcie_bus_info = { 214 .name = TYPE_PCIE_BUS, 215 .parent = TYPE_PCI_BUS, 216 .class_init = pcie_bus_class_init, 217 }; 218 219 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 220 static void pci_update_mappings(PCIDevice *d); 221 static void pci_irq_handler(void *opaque, int irq_num, int level); 222 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 223 static void pci_del_option_rom(PCIDevice *pdev); 224 225 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 226 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 227 228 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 229 230 int pci_bar(PCIDevice *d, int reg) 231 { 232 uint8_t type; 233 234 if (reg != PCI_ROM_SLOT) 235 return PCI_BASE_ADDRESS_0 + reg * 4; 236 237 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 238 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 239 } 240 241 static inline int pci_irq_state(PCIDevice *d, int irq_num) 242 { 243 return (d->irq_state >> irq_num) & 0x1; 244 } 245 246 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 247 { 248 d->irq_state &= ~(0x1 << irq_num); 249 d->irq_state |= level << irq_num; 250 } 251 252 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 253 { 254 assert(irq_num >= 0); 255 assert(irq_num < bus->nirq); 256 bus->irq_count[irq_num] += change; 257 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 258 } 259 260 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 261 { 262 PCIBus *bus; 263 for (;;) { 264 bus = pci_get_bus(pci_dev); 265 irq_num = bus->map_irq(pci_dev, irq_num); 266 if (bus->set_irq) 267 break; 268 pci_dev = bus->parent_dev; 269 } 270 pci_bus_change_irq_level(bus, irq_num, change); 271 } 272 273 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 274 { 275 assert(irq_num >= 0); 276 assert(irq_num < bus->nirq); 277 return !!bus->irq_count[irq_num]; 278 } 279 280 /* Update interrupt status bit in config space on interrupt 281 * state change. */ 282 static void pci_update_irq_status(PCIDevice *dev) 283 { 284 if (dev->irq_state) { 285 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 286 } else { 287 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 288 } 289 } 290 291 void pci_device_deassert_intx(PCIDevice *dev) 292 { 293 int i; 294 for (i = 0; i < PCI_NUM_PINS; ++i) { 295 pci_irq_handler(dev, i, 0); 296 } 297 } 298 299 static void pci_do_device_reset(PCIDevice *dev) 300 { 301 int r; 302 303 pci_device_deassert_intx(dev); 304 assert(dev->irq_state == 0); 305 306 /* Clear all writable bits */ 307 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 308 pci_get_word(dev->wmask + PCI_COMMAND) | 309 pci_get_word(dev->w1cmask + PCI_COMMAND)); 310 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 311 pci_get_word(dev->wmask + PCI_STATUS) | 312 pci_get_word(dev->w1cmask + PCI_STATUS)); 313 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 314 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 315 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 316 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 317 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 318 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 319 PCIIORegion *region = &dev->io_regions[r]; 320 if (!region->size) { 321 continue; 322 } 323 324 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 325 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 326 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 327 } else { 328 pci_set_long(dev->config + pci_bar(dev, r), region->type); 329 } 330 } 331 pci_update_mappings(dev); 332 333 msi_reset(dev); 334 msix_reset(dev); 335 } 336 337 /* 338 * This function is called on #RST and FLR. 339 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 340 */ 341 void pci_device_reset(PCIDevice *dev) 342 { 343 qdev_reset_all(&dev->qdev); 344 pci_do_device_reset(dev); 345 } 346 347 /* 348 * Trigger pci bus reset under a given bus. 349 * Called via qbus_reset_all on RST# assert, after the devices 350 * have been reset qdev_reset_all-ed already. 351 */ 352 static void pcibus_reset(BusState *qbus) 353 { 354 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 355 int i; 356 357 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 358 if (bus->devices[i]) { 359 pci_do_device_reset(bus->devices[i]); 360 } 361 } 362 363 for (i = 0; i < bus->nirq; i++) { 364 assert(bus->irq_count[i] == 0); 365 } 366 } 367 368 static void pci_host_bus_register(DeviceState *host) 369 { 370 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 371 372 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 373 } 374 375 static void pci_host_bus_unregister(DeviceState *host) 376 { 377 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 378 379 QLIST_REMOVE(host_bridge, next); 380 } 381 382 PCIBus *pci_device_root_bus(const PCIDevice *d) 383 { 384 PCIBus *bus = pci_get_bus(d); 385 386 while (!pci_bus_is_root(bus)) { 387 d = bus->parent_dev; 388 assert(d != NULL); 389 390 bus = pci_get_bus(d); 391 } 392 393 return bus; 394 } 395 396 const char *pci_root_bus_path(PCIDevice *dev) 397 { 398 PCIBus *rootbus = pci_device_root_bus(dev); 399 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 400 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 401 402 assert(host_bridge->bus == rootbus); 403 404 if (hc->root_bus_path) { 405 return (*hc->root_bus_path)(host_bridge, rootbus); 406 } 407 408 return rootbus->qbus.name; 409 } 410 411 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 412 MemoryRegion *address_space_mem, 413 MemoryRegion *address_space_io, 414 uint8_t devfn_min) 415 { 416 assert(PCI_FUNC(devfn_min) == 0); 417 bus->devfn_min = devfn_min; 418 bus->slot_reserved_mask = 0x0; 419 bus->address_space_mem = address_space_mem; 420 bus->address_space_io = address_space_io; 421 bus->flags |= PCI_BUS_IS_ROOT; 422 423 /* host bridge */ 424 QLIST_INIT(&bus->child); 425 426 pci_host_bus_register(parent); 427 } 428 429 static void pci_bus_uninit(PCIBus *bus) 430 { 431 pci_host_bus_unregister(BUS(bus)->parent); 432 } 433 434 bool pci_bus_is_express(PCIBus *bus) 435 { 436 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 437 } 438 439 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 440 const char *name, 441 MemoryRegion *address_space_mem, 442 MemoryRegion *address_space_io, 443 uint8_t devfn_min, const char *typename) 444 { 445 qbus_create_inplace(bus, bus_size, typename, parent, name); 446 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 447 devfn_min); 448 } 449 450 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 451 MemoryRegion *address_space_mem, 452 MemoryRegion *address_space_io, 453 uint8_t devfn_min, const char *typename) 454 { 455 PCIBus *bus; 456 457 bus = PCI_BUS(qbus_create(typename, parent, name)); 458 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 459 devfn_min); 460 return bus; 461 } 462 463 void pci_root_bus_cleanup(PCIBus *bus) 464 { 465 pci_bus_uninit(bus); 466 /* the caller of the unplug hotplug handler will delete this device */ 467 qbus_unrealize(BUS(bus)); 468 } 469 470 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 471 void *irq_opaque, int nirq) 472 { 473 bus->set_irq = set_irq; 474 bus->map_irq = map_irq; 475 bus->irq_opaque = irq_opaque; 476 bus->nirq = nirq; 477 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 478 } 479 480 void pci_bus_irqs_cleanup(PCIBus *bus) 481 { 482 bus->set_irq = NULL; 483 bus->map_irq = NULL; 484 bus->irq_opaque = NULL; 485 bus->nirq = 0; 486 g_free(bus->irq_count); 487 } 488 489 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 490 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 491 void *irq_opaque, 492 MemoryRegion *address_space_mem, 493 MemoryRegion *address_space_io, 494 uint8_t devfn_min, int nirq, 495 const char *typename) 496 { 497 PCIBus *bus; 498 499 bus = pci_root_bus_new(parent, name, address_space_mem, 500 address_space_io, devfn_min, typename); 501 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 502 return bus; 503 } 504 505 void pci_unregister_root_bus(PCIBus *bus) 506 { 507 pci_bus_irqs_cleanup(bus); 508 pci_root_bus_cleanup(bus); 509 } 510 511 int pci_bus_num(PCIBus *s) 512 { 513 return PCI_BUS_GET_CLASS(s)->bus_num(s); 514 } 515 516 int pci_bus_numa_node(PCIBus *bus) 517 { 518 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 519 } 520 521 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 522 const VMStateField *field) 523 { 524 PCIDevice *s = container_of(pv, PCIDevice, config); 525 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 526 uint8_t *config; 527 int i; 528 529 assert(size == pci_config_size(s)); 530 config = g_malloc(size); 531 532 qemu_get_buffer(f, config, size); 533 for (i = 0; i < size; ++i) { 534 if ((config[i] ^ s->config[i]) & 535 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 536 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 537 "cmask: %x wmask: %x w1cmask:%x", __func__, 538 i, config[i], s->config[i], 539 s->cmask[i], s->wmask[i], s->w1cmask[i]); 540 g_free(config); 541 return -EINVAL; 542 } 543 } 544 memcpy(s->config, config, size); 545 546 pci_update_mappings(s); 547 if (pc->is_bridge) { 548 PCIBridge *b = PCI_BRIDGE(s); 549 pci_bridge_update_mappings(b); 550 } 551 552 memory_region_set_enabled(&s->bus_master_enable_region, 553 pci_get_word(s->config + PCI_COMMAND) 554 & PCI_COMMAND_MASTER); 555 556 g_free(config); 557 return 0; 558 } 559 560 /* just put buffer */ 561 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 562 const VMStateField *field, JSONWriter *vmdesc) 563 { 564 const uint8_t **v = pv; 565 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 566 qemu_put_buffer(f, *v, size); 567 568 return 0; 569 } 570 571 static VMStateInfo vmstate_info_pci_config = { 572 .name = "pci config", 573 .get = get_pci_config_device, 574 .put = put_pci_config_device, 575 }; 576 577 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 578 const VMStateField *field) 579 { 580 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 581 uint32_t irq_state[PCI_NUM_PINS]; 582 int i; 583 for (i = 0; i < PCI_NUM_PINS; ++i) { 584 irq_state[i] = qemu_get_be32(f); 585 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 586 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 587 irq_state[i]); 588 return -EINVAL; 589 } 590 } 591 592 for (i = 0; i < PCI_NUM_PINS; ++i) { 593 pci_set_irq_state(s, i, irq_state[i]); 594 } 595 596 return 0; 597 } 598 599 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 600 const VMStateField *field, JSONWriter *vmdesc) 601 { 602 int i; 603 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 604 605 for (i = 0; i < PCI_NUM_PINS; ++i) { 606 qemu_put_be32(f, pci_irq_state(s, i)); 607 } 608 609 return 0; 610 } 611 612 static VMStateInfo vmstate_info_pci_irq_state = { 613 .name = "pci irq state", 614 .get = get_pci_irq_state, 615 .put = put_pci_irq_state, 616 }; 617 618 static bool migrate_is_pcie(void *opaque, int version_id) 619 { 620 return pci_is_express((PCIDevice *)opaque); 621 } 622 623 static bool migrate_is_not_pcie(void *opaque, int version_id) 624 { 625 return !pci_is_express((PCIDevice *)opaque); 626 } 627 628 const VMStateDescription vmstate_pci_device = { 629 .name = "PCIDevice", 630 .version_id = 2, 631 .minimum_version_id = 1, 632 .fields = (VMStateField[]) { 633 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 634 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 635 migrate_is_not_pcie, 636 0, vmstate_info_pci_config, 637 PCI_CONFIG_SPACE_SIZE), 638 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 639 migrate_is_pcie, 640 0, vmstate_info_pci_config, 641 PCIE_CONFIG_SPACE_SIZE), 642 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 643 vmstate_info_pci_irq_state, 644 PCI_NUM_PINS * sizeof(int32_t)), 645 VMSTATE_END_OF_LIST() 646 } 647 }; 648 649 650 void pci_device_save(PCIDevice *s, QEMUFile *f) 651 { 652 /* Clear interrupt status bit: it is implicit 653 * in irq_state which we are saving. 654 * This makes us compatible with old devices 655 * which never set or clear this bit. */ 656 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 657 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 658 /* Restore the interrupt status bit. */ 659 pci_update_irq_status(s); 660 } 661 662 int pci_device_load(PCIDevice *s, QEMUFile *f) 663 { 664 int ret; 665 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 666 /* Restore the interrupt status bit. */ 667 pci_update_irq_status(s); 668 return ret; 669 } 670 671 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 672 { 673 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 674 pci_default_sub_vendor_id); 675 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 676 pci_default_sub_device_id); 677 } 678 679 /* 680 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 681 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 682 */ 683 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 684 unsigned int *slotp, unsigned int *funcp) 685 { 686 const char *p; 687 char *e; 688 unsigned long val; 689 unsigned long dom = 0, bus = 0; 690 unsigned int slot = 0; 691 unsigned int func = 0; 692 693 p = addr; 694 val = strtoul(p, &e, 16); 695 if (e == p) 696 return -1; 697 if (*e == ':') { 698 bus = val; 699 p = e + 1; 700 val = strtoul(p, &e, 16); 701 if (e == p) 702 return -1; 703 if (*e == ':') { 704 dom = bus; 705 bus = val; 706 p = e + 1; 707 val = strtoul(p, &e, 16); 708 if (e == p) 709 return -1; 710 } 711 } 712 713 slot = val; 714 715 if (funcp != NULL) { 716 if (*e != '.') 717 return -1; 718 719 p = e + 1; 720 val = strtoul(p, &e, 16); 721 if (e == p) 722 return -1; 723 724 func = val; 725 } 726 727 /* if funcp == NULL func is 0 */ 728 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 729 return -1; 730 731 if (*e) 732 return -1; 733 734 *domp = dom; 735 *busp = bus; 736 *slotp = slot; 737 if (funcp != NULL) 738 *funcp = func; 739 return 0; 740 } 741 742 static void pci_init_cmask(PCIDevice *dev) 743 { 744 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 745 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 746 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 747 dev->cmask[PCI_REVISION_ID] = 0xff; 748 dev->cmask[PCI_CLASS_PROG] = 0xff; 749 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 750 dev->cmask[PCI_HEADER_TYPE] = 0xff; 751 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 752 } 753 754 static void pci_init_wmask(PCIDevice *dev) 755 { 756 int config_size = pci_config_size(dev); 757 758 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 759 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 760 pci_set_word(dev->wmask + PCI_COMMAND, 761 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 762 PCI_COMMAND_INTX_DISABLE); 763 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 764 765 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 766 config_size - PCI_CONFIG_HEADER_SIZE); 767 } 768 769 static void pci_init_w1cmask(PCIDevice *dev) 770 { 771 /* 772 * Note: It's okay to set w1cmask even for readonly bits as 773 * long as their value is hardwired to 0. 774 */ 775 pci_set_word(dev->w1cmask + PCI_STATUS, 776 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 777 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 778 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 779 } 780 781 static void pci_init_mask_bridge(PCIDevice *d) 782 { 783 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 784 PCI_SEC_LETENCY_TIMER */ 785 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 786 787 /* base and limit */ 788 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 789 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 790 pci_set_word(d->wmask + PCI_MEMORY_BASE, 791 PCI_MEMORY_RANGE_MASK & 0xffff); 792 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 793 PCI_MEMORY_RANGE_MASK & 0xffff); 794 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 795 PCI_PREF_RANGE_MASK & 0xffff); 796 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 797 PCI_PREF_RANGE_MASK & 0xffff); 798 799 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 800 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 801 802 /* Supported memory and i/o types */ 803 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 804 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 805 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 806 PCI_PREF_RANGE_TYPE_64); 807 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 808 PCI_PREF_RANGE_TYPE_64); 809 810 /* 811 * TODO: Bridges default to 10-bit VGA decoding but we currently only 812 * implement 16-bit decoding (no alias support). 813 */ 814 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 815 PCI_BRIDGE_CTL_PARITY | 816 PCI_BRIDGE_CTL_SERR | 817 PCI_BRIDGE_CTL_ISA | 818 PCI_BRIDGE_CTL_VGA | 819 PCI_BRIDGE_CTL_VGA_16BIT | 820 PCI_BRIDGE_CTL_MASTER_ABORT | 821 PCI_BRIDGE_CTL_BUS_RESET | 822 PCI_BRIDGE_CTL_FAST_BACK | 823 PCI_BRIDGE_CTL_DISCARD | 824 PCI_BRIDGE_CTL_SEC_DISCARD | 825 PCI_BRIDGE_CTL_DISCARD_SERR); 826 /* Below does not do anything as we never set this bit, put here for 827 * completeness. */ 828 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 829 PCI_BRIDGE_CTL_DISCARD_STATUS); 830 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 831 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 832 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 833 PCI_PREF_RANGE_TYPE_MASK); 834 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 835 PCI_PREF_RANGE_TYPE_MASK); 836 } 837 838 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 839 { 840 uint8_t slot = PCI_SLOT(dev->devfn); 841 uint8_t func; 842 843 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 844 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 845 } 846 847 /* 848 * multifunction bit is interpreted in two ways as follows. 849 * - all functions must set the bit to 1. 850 * Example: Intel X53 851 * - function 0 must set the bit, but the rest function (> 0) 852 * is allowed to leave the bit to 0. 853 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 854 * 855 * So OS (at least Linux) checks the bit of only function 0, 856 * and doesn't see the bit of function > 0. 857 * 858 * The below check allows both interpretation. 859 */ 860 if (PCI_FUNC(dev->devfn)) { 861 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 862 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 863 /* function 0 should set multifunction bit */ 864 error_setg(errp, "PCI: single function device can't be populated " 865 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 866 return; 867 } 868 return; 869 } 870 871 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 872 return; 873 } 874 /* function 0 indicates single function, so function > 0 must be NULL */ 875 for (func = 1; func < PCI_FUNC_MAX; ++func) { 876 if (bus->devices[PCI_DEVFN(slot, func)]) { 877 error_setg(errp, "PCI: %x.0 indicates single function, " 878 "but %x.%x is already populated.", 879 slot, slot, func); 880 return; 881 } 882 } 883 } 884 885 static void pci_config_alloc(PCIDevice *pci_dev) 886 { 887 int config_size = pci_config_size(pci_dev); 888 889 pci_dev->config = g_malloc0(config_size); 890 pci_dev->cmask = g_malloc0(config_size); 891 pci_dev->wmask = g_malloc0(config_size); 892 pci_dev->w1cmask = g_malloc0(config_size); 893 pci_dev->used = g_malloc0(config_size); 894 } 895 896 static void pci_config_free(PCIDevice *pci_dev) 897 { 898 g_free(pci_dev->config); 899 g_free(pci_dev->cmask); 900 g_free(pci_dev->wmask); 901 g_free(pci_dev->w1cmask); 902 g_free(pci_dev->used); 903 } 904 905 static void do_pci_unregister_device(PCIDevice *pci_dev) 906 { 907 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 908 pci_config_free(pci_dev); 909 910 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 911 memory_region_del_subregion(&pci_dev->bus_master_container_region, 912 &pci_dev->bus_master_enable_region); 913 } 914 address_space_destroy(&pci_dev->bus_master_as); 915 } 916 917 /* Extract PCIReqIDCache into BDF format */ 918 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 919 { 920 uint8_t bus_n; 921 uint16_t result; 922 923 switch (cache->type) { 924 case PCI_REQ_ID_BDF: 925 result = pci_get_bdf(cache->dev); 926 break; 927 case PCI_REQ_ID_SECONDARY_BUS: 928 bus_n = pci_dev_bus_num(cache->dev); 929 result = PCI_BUILD_BDF(bus_n, 0); 930 break; 931 default: 932 error_report("Invalid PCI requester ID cache type: %d", 933 cache->type); 934 exit(1); 935 break; 936 } 937 938 return result; 939 } 940 941 /* Parse bridges up to the root complex and return requester ID 942 * cache for specific device. For full PCIe topology, the cache 943 * result would be exactly the same as getting BDF of the device. 944 * However, several tricks are required when system mixed up with 945 * legacy PCI devices and PCIe-to-PCI bridges. 946 * 947 * Here we cache the proxy device (and type) not requester ID since 948 * bus number might change from time to time. 949 */ 950 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 951 { 952 PCIDevice *parent; 953 PCIReqIDCache cache = { 954 .dev = dev, 955 .type = PCI_REQ_ID_BDF, 956 }; 957 958 while (!pci_bus_is_root(pci_get_bus(dev))) { 959 /* We are under PCI/PCIe bridges */ 960 parent = pci_get_bus(dev)->parent_dev; 961 if (pci_is_express(parent)) { 962 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 963 /* When we pass through PCIe-to-PCI/PCIX bridges, we 964 * override the requester ID using secondary bus 965 * number of parent bridge with zeroed devfn 966 * (pcie-to-pci bridge spec chap 2.3). */ 967 cache.type = PCI_REQ_ID_SECONDARY_BUS; 968 cache.dev = dev; 969 } 970 } else { 971 /* Legacy PCI, override requester ID with the bridge's 972 * BDF upstream. When the root complex connects to 973 * legacy PCI devices (including buses), it can only 974 * obtain requester ID info from directly attached 975 * devices. If devices are attached under bridges, only 976 * the requester ID of the bridge that is directly 977 * attached to the root complex can be recognized. */ 978 cache.type = PCI_REQ_ID_BDF; 979 cache.dev = parent; 980 } 981 dev = parent; 982 } 983 984 return cache; 985 } 986 987 uint16_t pci_requester_id(PCIDevice *dev) 988 { 989 return pci_req_id_cache_extract(&dev->requester_id_cache); 990 } 991 992 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 993 { 994 return !(bus->devices[devfn]); 995 } 996 997 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 998 { 999 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1000 } 1001 1002 /* -1 for devfn means auto assign */ 1003 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1004 const char *name, int devfn, 1005 Error **errp) 1006 { 1007 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1008 PCIConfigReadFunc *config_read = pc->config_read; 1009 PCIConfigWriteFunc *config_write = pc->config_write; 1010 Error *local_err = NULL; 1011 DeviceState *dev = DEVICE(pci_dev); 1012 PCIBus *bus = pci_get_bus(pci_dev); 1013 1014 /* Only pci bridges can be attached to extra PCI root buses */ 1015 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1016 error_setg(errp, 1017 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1018 bus->parent_dev->name); 1019 return NULL; 1020 } 1021 1022 if (devfn < 0) { 1023 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1024 devfn += PCI_FUNC_MAX) { 1025 if (pci_bus_devfn_available(bus, devfn) && 1026 !pci_bus_devfn_reserved(bus, devfn)) { 1027 goto found; 1028 } 1029 } 1030 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1031 "or reserved", name); 1032 return NULL; 1033 found: ; 1034 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1035 error_setg(errp, "PCI: slot %d function %d not available for %s," 1036 " reserved", 1037 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1038 return NULL; 1039 } else if (!pci_bus_devfn_available(bus, devfn)) { 1040 error_setg(errp, "PCI: slot %d function %d not available for %s," 1041 " in use by %s", 1042 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1043 bus->devices[devfn]->name); 1044 return NULL; 1045 } else if (dev->hotplugged && 1046 pci_get_function_0(pci_dev)) { 1047 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1048 " new func %s cannot be exposed to guest.", 1049 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1050 pci_get_function_0(pci_dev)->name, 1051 name); 1052 1053 return NULL; 1054 } 1055 1056 pci_dev->devfn = devfn; 1057 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1058 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1059 1060 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1061 "bus master container", UINT64_MAX); 1062 address_space_init(&pci_dev->bus_master_as, 1063 &pci_dev->bus_master_container_region, pci_dev->name); 1064 1065 if (phase_check(PHASE_MACHINE_READY)) { 1066 pci_init_bus_master(pci_dev); 1067 } 1068 pci_dev->irq_state = 0; 1069 pci_config_alloc(pci_dev); 1070 1071 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1072 pci_config_set_device_id(pci_dev->config, pc->device_id); 1073 pci_config_set_revision(pci_dev->config, pc->revision); 1074 pci_config_set_class(pci_dev->config, pc->class_id); 1075 1076 if (!pc->is_bridge) { 1077 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1078 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1079 pc->subsystem_vendor_id); 1080 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1081 pc->subsystem_id); 1082 } else { 1083 pci_set_default_subsystem_id(pci_dev); 1084 } 1085 } else { 1086 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1087 assert(!pc->subsystem_vendor_id); 1088 assert(!pc->subsystem_id); 1089 } 1090 pci_init_cmask(pci_dev); 1091 pci_init_wmask(pci_dev); 1092 pci_init_w1cmask(pci_dev); 1093 if (pc->is_bridge) { 1094 pci_init_mask_bridge(pci_dev); 1095 } 1096 pci_init_multifunction(bus, pci_dev, &local_err); 1097 if (local_err) { 1098 error_propagate(errp, local_err); 1099 do_pci_unregister_device(pci_dev); 1100 return NULL; 1101 } 1102 1103 if (!config_read) 1104 config_read = pci_default_read_config; 1105 if (!config_write) 1106 config_write = pci_default_write_config; 1107 pci_dev->config_read = config_read; 1108 pci_dev->config_write = config_write; 1109 bus->devices[devfn] = pci_dev; 1110 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1111 return pci_dev; 1112 } 1113 1114 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1115 { 1116 PCIIORegion *r; 1117 int i; 1118 1119 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1120 r = &pci_dev->io_regions[i]; 1121 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1122 continue; 1123 memory_region_del_subregion(r->address_space, r->memory); 1124 } 1125 1126 pci_unregister_vga(pci_dev); 1127 } 1128 1129 static void pci_qdev_unrealize(DeviceState *dev) 1130 { 1131 PCIDevice *pci_dev = PCI_DEVICE(dev); 1132 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1133 1134 pci_unregister_io_regions(pci_dev); 1135 pci_del_option_rom(pci_dev); 1136 1137 if (pc->exit) { 1138 pc->exit(pci_dev); 1139 } 1140 1141 pci_device_deassert_intx(pci_dev); 1142 do_pci_unregister_device(pci_dev); 1143 } 1144 1145 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1146 uint8_t type, MemoryRegion *memory) 1147 { 1148 PCIIORegion *r; 1149 uint32_t addr; /* offset in pci config space */ 1150 uint64_t wmask; 1151 pcibus_t size = memory_region_size(memory); 1152 uint8_t hdr_type; 1153 1154 assert(region_num >= 0); 1155 assert(region_num < PCI_NUM_REGIONS); 1156 assert(is_power_of_2(size)); 1157 1158 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1159 hdr_type = 1160 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1161 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1162 1163 r = &pci_dev->io_regions[region_num]; 1164 r->addr = PCI_BAR_UNMAPPED; 1165 r->size = size; 1166 r->type = type; 1167 r->memory = memory; 1168 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1169 ? pci_get_bus(pci_dev)->address_space_io 1170 : pci_get_bus(pci_dev)->address_space_mem; 1171 1172 wmask = ~(size - 1); 1173 if (region_num == PCI_ROM_SLOT) { 1174 /* ROM enable bit is writable */ 1175 wmask |= PCI_ROM_ADDRESS_ENABLE; 1176 } 1177 1178 addr = pci_bar(pci_dev, region_num); 1179 pci_set_long(pci_dev->config + addr, type); 1180 1181 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1182 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1183 pci_set_quad(pci_dev->wmask + addr, wmask); 1184 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1185 } else { 1186 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1187 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1188 } 1189 } 1190 1191 static void pci_update_vga(PCIDevice *pci_dev) 1192 { 1193 uint16_t cmd; 1194 1195 if (!pci_dev->has_vga) { 1196 return; 1197 } 1198 1199 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1200 1201 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1202 cmd & PCI_COMMAND_MEMORY); 1203 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1204 cmd & PCI_COMMAND_IO); 1205 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1206 cmd & PCI_COMMAND_IO); 1207 } 1208 1209 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1210 MemoryRegion *io_lo, MemoryRegion *io_hi) 1211 { 1212 PCIBus *bus = pci_get_bus(pci_dev); 1213 1214 assert(!pci_dev->has_vga); 1215 1216 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1217 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1218 memory_region_add_subregion_overlap(bus->address_space_mem, 1219 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1220 1221 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1222 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1223 memory_region_add_subregion_overlap(bus->address_space_io, 1224 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1225 1226 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1227 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1228 memory_region_add_subregion_overlap(bus->address_space_io, 1229 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1230 pci_dev->has_vga = true; 1231 1232 pci_update_vga(pci_dev); 1233 } 1234 1235 void pci_unregister_vga(PCIDevice *pci_dev) 1236 { 1237 PCIBus *bus = pci_get_bus(pci_dev); 1238 1239 if (!pci_dev->has_vga) { 1240 return; 1241 } 1242 1243 memory_region_del_subregion(bus->address_space_mem, 1244 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1245 memory_region_del_subregion(bus->address_space_io, 1246 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1247 memory_region_del_subregion(bus->address_space_io, 1248 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1249 pci_dev->has_vga = false; 1250 } 1251 1252 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1253 { 1254 return pci_dev->io_regions[region_num].addr; 1255 } 1256 1257 static pcibus_t pci_bar_address(PCIDevice *d, 1258 int reg, uint8_t type, pcibus_t size) 1259 { 1260 pcibus_t new_addr, last_addr; 1261 int bar = pci_bar(d, reg); 1262 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1263 Object *machine = qdev_get_machine(); 1264 ObjectClass *oc = object_get_class(machine); 1265 MachineClass *mc = MACHINE_CLASS(oc); 1266 bool allow_0_address = mc->pci_allow_0_address; 1267 1268 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1269 if (!(cmd & PCI_COMMAND_IO)) { 1270 return PCI_BAR_UNMAPPED; 1271 } 1272 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1273 last_addr = new_addr + size - 1; 1274 /* Check if 32 bit BAR wraps around explicitly. 1275 * TODO: make priorities correct and remove this work around. 1276 */ 1277 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1278 (!allow_0_address && new_addr == 0)) { 1279 return PCI_BAR_UNMAPPED; 1280 } 1281 return new_addr; 1282 } 1283 1284 if (!(cmd & PCI_COMMAND_MEMORY)) { 1285 return PCI_BAR_UNMAPPED; 1286 } 1287 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1288 new_addr = pci_get_quad(d->config + bar); 1289 } else { 1290 new_addr = pci_get_long(d->config + bar); 1291 } 1292 /* the ROM slot has a specific enable bit */ 1293 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1294 return PCI_BAR_UNMAPPED; 1295 } 1296 new_addr &= ~(size - 1); 1297 last_addr = new_addr + size - 1; 1298 /* NOTE: we do not support wrapping */ 1299 /* XXX: as we cannot support really dynamic 1300 mappings, we handle specific values as invalid 1301 mappings. */ 1302 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1303 (!allow_0_address && new_addr == 0)) { 1304 return PCI_BAR_UNMAPPED; 1305 } 1306 1307 /* Now pcibus_t is 64bit. 1308 * Check if 32 bit BAR wraps around explicitly. 1309 * Without this, PC ide doesn't work well. 1310 * TODO: remove this work around. 1311 */ 1312 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1313 return PCI_BAR_UNMAPPED; 1314 } 1315 1316 /* 1317 * OS is allowed to set BAR beyond its addressable 1318 * bits. For example, 32 bit OS can set 64bit bar 1319 * to >4G. Check it. TODO: we might need to support 1320 * it in the future for e.g. PAE. 1321 */ 1322 if (last_addr >= HWADDR_MAX) { 1323 return PCI_BAR_UNMAPPED; 1324 } 1325 1326 return new_addr; 1327 } 1328 1329 static void pci_update_mappings(PCIDevice *d) 1330 { 1331 PCIIORegion *r; 1332 int i; 1333 pcibus_t new_addr; 1334 1335 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1336 r = &d->io_regions[i]; 1337 1338 /* this region isn't registered */ 1339 if (!r->size) 1340 continue; 1341 1342 new_addr = pci_bar_address(d, i, r->type, r->size); 1343 1344 /* This bar isn't changed */ 1345 if (new_addr == r->addr) 1346 continue; 1347 1348 /* now do the real mapping */ 1349 if (r->addr != PCI_BAR_UNMAPPED) { 1350 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1351 PCI_SLOT(d->devfn), 1352 PCI_FUNC(d->devfn), 1353 i, r->addr, r->size); 1354 memory_region_del_subregion(r->address_space, r->memory); 1355 } 1356 r->addr = new_addr; 1357 if (r->addr != PCI_BAR_UNMAPPED) { 1358 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1359 PCI_SLOT(d->devfn), 1360 PCI_FUNC(d->devfn), 1361 i, r->addr, r->size); 1362 memory_region_add_subregion_overlap(r->address_space, 1363 r->addr, r->memory, 1); 1364 } 1365 } 1366 1367 pci_update_vga(d); 1368 } 1369 1370 static inline int pci_irq_disabled(PCIDevice *d) 1371 { 1372 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1373 } 1374 1375 /* Called after interrupt disabled field update in config space, 1376 * assert/deassert interrupts if necessary. 1377 * Gets original interrupt disable bit value (before update). */ 1378 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1379 { 1380 int i, disabled = pci_irq_disabled(d); 1381 if (disabled == was_irq_disabled) 1382 return; 1383 for (i = 0; i < PCI_NUM_PINS; ++i) { 1384 int state = pci_irq_state(d, i); 1385 pci_change_irq_level(d, i, disabled ? -state : state); 1386 } 1387 } 1388 1389 uint32_t pci_default_read_config(PCIDevice *d, 1390 uint32_t address, int len) 1391 { 1392 uint32_t val = 0; 1393 1394 assert(address + len <= pci_config_size(d)); 1395 1396 if (pci_is_express_downstream_port(d) && 1397 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1398 pcie_sync_bridge_lnk(d); 1399 } 1400 memcpy(&val, d->config + address, len); 1401 return le32_to_cpu(val); 1402 } 1403 1404 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1405 { 1406 int i, was_irq_disabled = pci_irq_disabled(d); 1407 uint32_t val = val_in; 1408 1409 assert(addr + l <= pci_config_size(d)); 1410 1411 for (i = 0; i < l; val >>= 8, ++i) { 1412 uint8_t wmask = d->wmask[addr + i]; 1413 uint8_t w1cmask = d->w1cmask[addr + i]; 1414 assert(!(wmask & w1cmask)); 1415 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1416 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1417 } 1418 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1419 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1420 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1421 range_covers_byte(addr, l, PCI_COMMAND)) 1422 pci_update_mappings(d); 1423 1424 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1425 pci_update_irq_disabled(d, was_irq_disabled); 1426 memory_region_set_enabled(&d->bus_master_enable_region, 1427 pci_get_word(d->config + PCI_COMMAND) 1428 & PCI_COMMAND_MASTER); 1429 } 1430 1431 msi_write_config(d, addr, val_in, l); 1432 msix_write_config(d, addr, val_in, l); 1433 } 1434 1435 /***********************************************************/ 1436 /* generic PCI irq support */ 1437 1438 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1439 static void pci_irq_handler(void *opaque, int irq_num, int level) 1440 { 1441 PCIDevice *pci_dev = opaque; 1442 int change; 1443 1444 change = level - pci_irq_state(pci_dev, irq_num); 1445 if (!change) 1446 return; 1447 1448 pci_set_irq_state(pci_dev, irq_num, level); 1449 pci_update_irq_status(pci_dev); 1450 if (pci_irq_disabled(pci_dev)) 1451 return; 1452 pci_change_irq_level(pci_dev, irq_num, change); 1453 } 1454 1455 static inline int pci_intx(PCIDevice *pci_dev) 1456 { 1457 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1458 } 1459 1460 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1461 { 1462 int intx = pci_intx(pci_dev); 1463 1464 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1465 } 1466 1467 void pci_set_irq(PCIDevice *pci_dev, int level) 1468 { 1469 int intx = pci_intx(pci_dev); 1470 pci_irq_handler(pci_dev, intx, level); 1471 } 1472 1473 /* Special hooks used by device assignment */ 1474 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1475 { 1476 assert(pci_bus_is_root(bus)); 1477 bus->route_intx_to_irq = route_intx_to_irq; 1478 } 1479 1480 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1481 { 1482 PCIBus *bus; 1483 1484 do { 1485 bus = pci_get_bus(dev); 1486 pin = bus->map_irq(dev, pin); 1487 dev = bus->parent_dev; 1488 } while (dev); 1489 1490 if (!bus->route_intx_to_irq) { 1491 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1492 object_get_typename(OBJECT(bus->qbus.parent))); 1493 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1494 } 1495 1496 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1497 } 1498 1499 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1500 { 1501 return old->mode != new->mode || old->irq != new->irq; 1502 } 1503 1504 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1505 { 1506 PCIDevice *dev; 1507 PCIBus *sec; 1508 int i; 1509 1510 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1511 dev = bus->devices[i]; 1512 if (dev && dev->intx_routing_notifier) { 1513 dev->intx_routing_notifier(dev); 1514 } 1515 } 1516 1517 QLIST_FOREACH(sec, &bus->child, sibling) { 1518 pci_bus_fire_intx_routing_notifier(sec); 1519 } 1520 } 1521 1522 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1523 PCIINTxRoutingNotifier notifier) 1524 { 1525 dev->intx_routing_notifier = notifier; 1526 } 1527 1528 /* 1529 * PCI-to-PCI bridge specification 1530 * 9.1: Interrupt routing. Table 9-1 1531 * 1532 * the PCI Express Base Specification, Revision 2.1 1533 * 2.2.8.1: INTx interrutp signaling - Rules 1534 * the Implementation Note 1535 * Table 2-20 1536 */ 1537 /* 1538 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1539 * 0-origin unlike PCI interrupt pin register. 1540 */ 1541 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1542 { 1543 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1544 } 1545 1546 /***********************************************************/ 1547 /* monitor info on PCI */ 1548 1549 typedef struct { 1550 uint16_t class; 1551 const char *desc; 1552 const char *fw_name; 1553 uint16_t fw_ign_bits; 1554 } pci_class_desc; 1555 1556 static const pci_class_desc pci_class_descriptions[] = 1557 { 1558 { 0x0001, "VGA controller", "display"}, 1559 { 0x0100, "SCSI controller", "scsi"}, 1560 { 0x0101, "IDE controller", "ide"}, 1561 { 0x0102, "Floppy controller", "fdc"}, 1562 { 0x0103, "IPI controller", "ipi"}, 1563 { 0x0104, "RAID controller", "raid"}, 1564 { 0x0106, "SATA controller"}, 1565 { 0x0107, "SAS controller"}, 1566 { 0x0180, "Storage controller"}, 1567 { 0x0200, "Ethernet controller", "ethernet"}, 1568 { 0x0201, "Token Ring controller", "token-ring"}, 1569 { 0x0202, "FDDI controller", "fddi"}, 1570 { 0x0203, "ATM controller", "atm"}, 1571 { 0x0280, "Network controller"}, 1572 { 0x0300, "VGA controller", "display", 0x00ff}, 1573 { 0x0301, "XGA controller"}, 1574 { 0x0302, "3D controller"}, 1575 { 0x0380, "Display controller"}, 1576 { 0x0400, "Video controller", "video"}, 1577 { 0x0401, "Audio controller", "sound"}, 1578 { 0x0402, "Phone"}, 1579 { 0x0403, "Audio controller", "sound"}, 1580 { 0x0480, "Multimedia controller"}, 1581 { 0x0500, "RAM controller", "memory"}, 1582 { 0x0501, "Flash controller", "flash"}, 1583 { 0x0580, "Memory controller"}, 1584 { 0x0600, "Host bridge", "host"}, 1585 { 0x0601, "ISA bridge", "isa"}, 1586 { 0x0602, "EISA bridge", "eisa"}, 1587 { 0x0603, "MC bridge", "mca"}, 1588 { 0x0604, "PCI bridge", "pci-bridge"}, 1589 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1590 { 0x0606, "NUBUS bridge", "nubus"}, 1591 { 0x0607, "CARDBUS bridge", "cardbus"}, 1592 { 0x0608, "RACEWAY bridge"}, 1593 { 0x0680, "Bridge"}, 1594 { 0x0700, "Serial port", "serial"}, 1595 { 0x0701, "Parallel port", "parallel"}, 1596 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1597 { 0x0801, "DMA controller", "dma-controller"}, 1598 { 0x0802, "Timer", "timer"}, 1599 { 0x0803, "RTC", "rtc"}, 1600 { 0x0900, "Keyboard", "keyboard"}, 1601 { 0x0901, "Pen", "pen"}, 1602 { 0x0902, "Mouse", "mouse"}, 1603 { 0x0A00, "Dock station", "dock", 0x00ff}, 1604 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1605 { 0x0c00, "Fireware contorller", "fireware"}, 1606 { 0x0c01, "Access bus controller", "access-bus"}, 1607 { 0x0c02, "SSA controller", "ssa"}, 1608 { 0x0c03, "USB controller", "usb"}, 1609 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1610 { 0x0c05, "SMBus"}, 1611 { 0, NULL} 1612 }; 1613 1614 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1615 void (*fn)(PCIBus *b, 1616 PCIDevice *d, 1617 void *opaque), 1618 void *opaque) 1619 { 1620 PCIDevice *d; 1621 int devfn; 1622 1623 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1624 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1625 if (d) { 1626 fn(bus, d, opaque); 1627 } 1628 } 1629 } 1630 1631 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1632 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1633 void *opaque) 1634 { 1635 bus = pci_find_bus_nr(bus, bus_num); 1636 1637 if (bus) { 1638 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1639 } 1640 } 1641 1642 static void pci_for_each_device_under_bus(PCIBus *bus, 1643 void (*fn)(PCIBus *b, PCIDevice *d, 1644 void *opaque), 1645 void *opaque) 1646 { 1647 PCIDevice *d; 1648 int devfn; 1649 1650 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1651 d = bus->devices[devfn]; 1652 if (d) { 1653 fn(bus, d, opaque); 1654 } 1655 } 1656 } 1657 1658 void pci_for_each_device(PCIBus *bus, int bus_num, 1659 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1660 void *opaque) 1661 { 1662 bus = pci_find_bus_nr(bus, bus_num); 1663 1664 if (bus) { 1665 pci_for_each_device_under_bus(bus, fn, opaque); 1666 } 1667 } 1668 1669 static const pci_class_desc *get_class_desc(int class) 1670 { 1671 const pci_class_desc *desc; 1672 1673 desc = pci_class_descriptions; 1674 while (desc->desc && class != desc->class) { 1675 desc++; 1676 } 1677 1678 return desc; 1679 } 1680 1681 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1682 1683 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1684 { 1685 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1686 int i; 1687 1688 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1689 const PCIIORegion *r = &dev->io_regions[i]; 1690 PciMemoryRegionList *region; 1691 1692 if (!r->size) { 1693 continue; 1694 } 1695 1696 region = g_malloc0(sizeof(*region)); 1697 region->value = g_malloc0(sizeof(*region->value)); 1698 1699 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1700 region->value->type = g_strdup("io"); 1701 } else { 1702 region->value->type = g_strdup("memory"); 1703 region->value->has_prefetch = true; 1704 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1705 region->value->has_mem_type_64 = true; 1706 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1707 } 1708 1709 region->value->bar = i; 1710 region->value->address = r->addr; 1711 region->value->size = r->size; 1712 1713 /* XXX: waiting for the qapi to support GSList */ 1714 if (!cur_item) { 1715 head = cur_item = region; 1716 } else { 1717 cur_item->next = region; 1718 cur_item = region; 1719 } 1720 } 1721 1722 return head; 1723 } 1724 1725 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1726 int bus_num) 1727 { 1728 PciBridgeInfo *info; 1729 PciMemoryRange *range; 1730 1731 info = g_new0(PciBridgeInfo, 1); 1732 1733 info->bus = g_new0(PciBusInfo, 1); 1734 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1735 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1736 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1737 1738 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1739 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1740 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1741 1742 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1743 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1744 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1745 1746 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1747 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1748 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1749 1750 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1751 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1752 if (child_bus) { 1753 info->has_devices = true; 1754 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1755 } 1756 } 1757 1758 return info; 1759 } 1760 1761 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1762 int bus_num) 1763 { 1764 const pci_class_desc *desc; 1765 PciDeviceInfo *info; 1766 uint8_t type; 1767 int class; 1768 1769 info = g_new0(PciDeviceInfo, 1); 1770 info->bus = bus_num; 1771 info->slot = PCI_SLOT(dev->devfn); 1772 info->function = PCI_FUNC(dev->devfn); 1773 1774 info->class_info = g_new0(PciDeviceClass, 1); 1775 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1776 info->class_info->q_class = class; 1777 desc = get_class_desc(class); 1778 if (desc->desc) { 1779 info->class_info->has_desc = true; 1780 info->class_info->desc = g_strdup(desc->desc); 1781 } 1782 1783 info->id = g_new0(PciDeviceId, 1); 1784 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1785 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1786 info->regions = qmp_query_pci_regions(dev); 1787 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1788 1789 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1790 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1791 info->has_irq = true; 1792 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1793 } 1794 1795 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1796 if (type == PCI_HEADER_TYPE_BRIDGE) { 1797 info->has_pci_bridge = true; 1798 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1799 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1800 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1801 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1802 info->id->subsystem_vendor = 1803 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1804 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1805 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1806 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1807 info->id->subsystem_vendor = 1808 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1809 } 1810 1811 return info; 1812 } 1813 1814 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1815 { 1816 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1817 PCIDevice *dev; 1818 int devfn; 1819 1820 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1821 dev = bus->devices[devfn]; 1822 if (dev) { 1823 info = g_malloc0(sizeof(*info)); 1824 info->value = qmp_query_pci_device(dev, bus, bus_num); 1825 1826 /* XXX: waiting for the qapi to support GSList */ 1827 if (!cur_item) { 1828 head = cur_item = info; 1829 } else { 1830 cur_item->next = info; 1831 cur_item = info; 1832 } 1833 } 1834 } 1835 1836 return head; 1837 } 1838 1839 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1840 { 1841 PciInfo *info = NULL; 1842 1843 bus = pci_find_bus_nr(bus, bus_num); 1844 if (bus) { 1845 info = g_malloc0(sizeof(*info)); 1846 info->bus = bus_num; 1847 info->devices = qmp_query_pci_devices(bus, bus_num); 1848 } 1849 1850 return info; 1851 } 1852 1853 PciInfoList *qmp_query_pci(Error **errp) 1854 { 1855 PciInfoList *info, *head = NULL, *cur_item = NULL; 1856 PCIHostState *host_bridge; 1857 1858 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1859 info = g_malloc0(sizeof(*info)); 1860 info->value = qmp_query_pci_bus(host_bridge->bus, 1861 pci_bus_num(host_bridge->bus)); 1862 1863 /* XXX: waiting for the qapi to support GSList */ 1864 if (!cur_item) { 1865 head = cur_item = info; 1866 } else { 1867 cur_item->next = info; 1868 cur_item = info; 1869 } 1870 } 1871 1872 return head; 1873 } 1874 1875 /* Initialize a PCI NIC. */ 1876 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1877 const char *default_model, 1878 const char *default_devaddr) 1879 { 1880 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1881 GSList *list; 1882 GPtrArray *pci_nic_models; 1883 PCIBus *bus; 1884 PCIDevice *pci_dev; 1885 DeviceState *dev; 1886 int devfn; 1887 int i; 1888 int dom, busnr; 1889 unsigned slot; 1890 1891 if (nd->model && !strcmp(nd->model, "virtio")) { 1892 g_free(nd->model); 1893 nd->model = g_strdup("virtio-net-pci"); 1894 } 1895 1896 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1897 pci_nic_models = g_ptr_array_new(); 1898 while (list) { 1899 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1900 TYPE_DEVICE); 1901 GSList *next; 1902 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1903 dc->user_creatable) { 1904 const char *name = object_class_get_name(list->data); 1905 /* 1906 * A network device might also be something else than a NIC, see 1907 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1908 * property, too. Unfortunately, some devices like virtio-net only 1909 * create this property during instance_init, so we have to create 1910 * a temporary instance here to be able to check it. 1911 */ 1912 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1913 if (object_property_find(obj, "netdev")) { 1914 g_ptr_array_add(pci_nic_models, (gpointer)name); 1915 } 1916 object_unref(obj); 1917 } 1918 next = list->next; 1919 g_slist_free_1(list); 1920 list = next; 1921 } 1922 g_ptr_array_add(pci_nic_models, NULL); 1923 1924 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1925 exit(0); 1926 } 1927 1928 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1929 default_model); 1930 if (i < 0) { 1931 exit(1); 1932 } 1933 1934 if (!rootbus) { 1935 error_report("No primary PCI bus"); 1936 exit(1); 1937 } 1938 1939 assert(!rootbus->parent_dev); 1940 1941 if (!devaddr) { 1942 devfn = -1; 1943 busnr = 0; 1944 } else { 1945 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1946 error_report("Invalid PCI device address %s for device %s", 1947 devaddr, nd->model); 1948 exit(1); 1949 } 1950 1951 if (dom != 0) { 1952 error_report("No support for non-zero PCI domains"); 1953 exit(1); 1954 } 1955 1956 devfn = PCI_DEVFN(slot, 0); 1957 } 1958 1959 bus = pci_find_bus_nr(rootbus, busnr); 1960 if (!bus) { 1961 error_report("Invalid PCI device address %s for device %s", 1962 devaddr, nd->model); 1963 exit(1); 1964 } 1965 1966 pci_dev = pci_new(devfn, nd->model); 1967 dev = &pci_dev->qdev; 1968 qdev_set_nic_properties(dev, nd); 1969 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1970 g_ptr_array_free(pci_nic_models, true); 1971 return pci_dev; 1972 } 1973 1974 PCIDevice *pci_vga_init(PCIBus *bus) 1975 { 1976 switch (vga_interface_type) { 1977 case VGA_CIRRUS: 1978 return pci_create_simple(bus, -1, "cirrus-vga"); 1979 case VGA_QXL: 1980 return pci_create_simple(bus, -1, "qxl-vga"); 1981 case VGA_STD: 1982 return pci_create_simple(bus, -1, "VGA"); 1983 case VGA_VMWARE: 1984 return pci_create_simple(bus, -1, "vmware-svga"); 1985 case VGA_VIRTIO: 1986 return pci_create_simple(bus, -1, "virtio-vga"); 1987 case VGA_NONE: 1988 default: /* Other non-PCI types. Checking for unsupported types is already 1989 done in vl.c. */ 1990 return NULL; 1991 } 1992 } 1993 1994 /* Whether a given bus number is in range of the secondary 1995 * bus of the given bridge device. */ 1996 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1997 { 1998 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1999 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 2000 dev->config[PCI_SECONDARY_BUS] <= bus_num && 2001 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 2002 } 2003 2004 /* Whether a given bus number is in a range of a root bus */ 2005 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 2006 { 2007 int i; 2008 2009 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 2010 PCIDevice *dev = bus->devices[i]; 2011 2012 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 2013 if (pci_secondary_bus_in_range(dev, bus_num)) { 2014 return true; 2015 } 2016 } 2017 } 2018 2019 return false; 2020 } 2021 2022 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2023 { 2024 PCIBus *sec; 2025 2026 if (!bus) { 2027 return NULL; 2028 } 2029 2030 if (pci_bus_num(bus) == bus_num) { 2031 return bus; 2032 } 2033 2034 /* Consider all bus numbers in range for the host pci bridge. */ 2035 if (!pci_bus_is_root(bus) && 2036 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2037 return NULL; 2038 } 2039 2040 /* try child bus */ 2041 for (; bus; bus = sec) { 2042 QLIST_FOREACH(sec, &bus->child, sibling) { 2043 if (pci_bus_num(sec) == bus_num) { 2044 return sec; 2045 } 2046 /* PXB buses assumed to be children of bus 0 */ 2047 if (pci_bus_is_root(sec)) { 2048 if (pci_root_bus_in_range(sec, bus_num)) { 2049 break; 2050 } 2051 } else { 2052 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2053 break; 2054 } 2055 } 2056 } 2057 } 2058 2059 return NULL; 2060 } 2061 2062 void pci_for_each_bus_depth_first(PCIBus *bus, 2063 void *(*begin)(PCIBus *bus, void *parent_state), 2064 void (*end)(PCIBus *bus, void *state), 2065 void *parent_state) 2066 { 2067 PCIBus *sec; 2068 void *state; 2069 2070 if (!bus) { 2071 return; 2072 } 2073 2074 if (begin) { 2075 state = begin(bus, parent_state); 2076 } else { 2077 state = parent_state; 2078 } 2079 2080 QLIST_FOREACH(sec, &bus->child, sibling) { 2081 pci_for_each_bus_depth_first(sec, begin, end, state); 2082 } 2083 2084 if (end) { 2085 end(bus, state); 2086 } 2087 } 2088 2089 2090 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2091 { 2092 bus = pci_find_bus_nr(bus, bus_num); 2093 2094 if (!bus) 2095 return NULL; 2096 2097 return bus->devices[devfn]; 2098 } 2099 2100 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2101 { 2102 PCIDevice *pci_dev = (PCIDevice *)qdev; 2103 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2104 ObjectClass *klass = OBJECT_CLASS(pc); 2105 Error *local_err = NULL; 2106 bool is_default_rom; 2107 uint16_t class_id; 2108 2109 /* initialize cap_present for pci_is_express() and pci_config_size(), 2110 * Note that hybrid PCIs are not set automatically and need to manage 2111 * QEMU_PCI_CAP_EXPRESS manually */ 2112 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2113 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2114 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2115 } 2116 2117 pci_dev = do_pci_register_device(pci_dev, 2118 object_get_typename(OBJECT(qdev)), 2119 pci_dev->devfn, errp); 2120 if (pci_dev == NULL) 2121 return; 2122 2123 if (pc->realize) { 2124 pc->realize(pci_dev, &local_err); 2125 if (local_err) { 2126 error_propagate(errp, local_err); 2127 do_pci_unregister_device(pci_dev); 2128 return; 2129 } 2130 } 2131 2132 if (pci_dev->failover_pair_id) { 2133 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2134 error_setg(errp, "failover primary device must be on " 2135 "PCIExpress bus"); 2136 pci_qdev_unrealize(DEVICE(pci_dev)); 2137 return; 2138 } 2139 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2140 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2141 error_setg(errp, "failover primary device is not an " 2142 "Ethernet device"); 2143 pci_qdev_unrealize(DEVICE(pci_dev)); 2144 return; 2145 } 2146 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2147 && (PCI_FUNC(pci_dev->devfn) == 0)) { 2148 qdev->allow_unplug_during_migration = true; 2149 } else { 2150 error_setg(errp, "failover: primary device must be in its own " 2151 "PCI slot"); 2152 pci_qdev_unrealize(DEVICE(pci_dev)); 2153 return; 2154 } 2155 qdev->allow_unplug_during_migration = true; 2156 } 2157 2158 /* rom loading */ 2159 is_default_rom = false; 2160 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2161 pci_dev->romfile = g_strdup(pc->romfile); 2162 is_default_rom = true; 2163 } 2164 2165 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2166 if (local_err) { 2167 error_propagate(errp, local_err); 2168 pci_qdev_unrealize(DEVICE(pci_dev)); 2169 return; 2170 } 2171 } 2172 2173 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2174 const char *name) 2175 { 2176 DeviceState *dev; 2177 2178 dev = qdev_new(name); 2179 qdev_prop_set_int32(dev, "addr", devfn); 2180 qdev_prop_set_bit(dev, "multifunction", multifunction); 2181 return PCI_DEVICE(dev); 2182 } 2183 2184 PCIDevice *pci_new(int devfn, const char *name) 2185 { 2186 return pci_new_multifunction(devfn, false, name); 2187 } 2188 2189 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2190 { 2191 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2192 } 2193 2194 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2195 bool multifunction, 2196 const char *name) 2197 { 2198 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2199 pci_realize_and_unref(dev, bus, &error_fatal); 2200 return dev; 2201 } 2202 2203 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2204 { 2205 return pci_create_simple_multifunction(bus, devfn, false, name); 2206 } 2207 2208 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2209 { 2210 int offset = PCI_CONFIG_HEADER_SIZE; 2211 int i; 2212 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2213 if (pdev->used[i]) 2214 offset = i + 1; 2215 else if (i - offset + 1 == size) 2216 return offset; 2217 } 2218 return 0; 2219 } 2220 2221 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2222 uint8_t *prev_p) 2223 { 2224 uint8_t next, prev; 2225 2226 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2227 return 0; 2228 2229 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2230 prev = next + PCI_CAP_LIST_NEXT) 2231 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2232 break; 2233 2234 if (prev_p) 2235 *prev_p = prev; 2236 return next; 2237 } 2238 2239 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2240 { 2241 uint8_t next, prev, found = 0; 2242 2243 if (!(pdev->used[offset])) { 2244 return 0; 2245 } 2246 2247 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2248 2249 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2250 prev = next + PCI_CAP_LIST_NEXT) { 2251 if (next <= offset && next > found) { 2252 found = next; 2253 } 2254 } 2255 return found; 2256 } 2257 2258 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2259 This is needed for an option rom which is used for more than one device. */ 2260 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2261 { 2262 uint16_t vendor_id; 2263 uint16_t device_id; 2264 uint16_t rom_vendor_id; 2265 uint16_t rom_device_id; 2266 uint16_t rom_magic; 2267 uint16_t pcir_offset; 2268 uint8_t checksum; 2269 2270 /* Words in rom data are little endian (like in PCI configuration), 2271 so they can be read / written with pci_get_word / pci_set_word. */ 2272 2273 /* Only a valid rom will be patched. */ 2274 rom_magic = pci_get_word(ptr); 2275 if (rom_magic != 0xaa55) { 2276 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2277 return; 2278 } 2279 pcir_offset = pci_get_word(ptr + 0x18); 2280 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2281 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2282 return; 2283 } 2284 2285 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2286 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2287 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2288 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2289 2290 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2291 vendor_id, device_id, rom_vendor_id, rom_device_id); 2292 2293 checksum = ptr[6]; 2294 2295 if (vendor_id != rom_vendor_id) { 2296 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2297 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2298 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2299 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2300 ptr[6] = checksum; 2301 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2302 } 2303 2304 if (device_id != rom_device_id) { 2305 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2306 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2307 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2308 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2309 ptr[6] = checksum; 2310 pci_set_word(ptr + pcir_offset + 6, device_id); 2311 } 2312 } 2313 2314 /* Add an option rom for the device */ 2315 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2316 Error **errp) 2317 { 2318 int size; 2319 char *path; 2320 void *ptr; 2321 char name[32]; 2322 const VMStateDescription *vmsd; 2323 2324 if (!pdev->romfile) 2325 return; 2326 if (strlen(pdev->romfile) == 0) 2327 return; 2328 2329 if (!pdev->rom_bar) { 2330 /* 2331 * Load rom via fw_cfg instead of creating a rom bar, 2332 * for 0.11 compatibility. 2333 */ 2334 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2335 2336 /* 2337 * Hot-plugged devices can't use the option ROM 2338 * if the rom bar is disabled. 2339 */ 2340 if (DEVICE(pdev)->hotplugged) { 2341 error_setg(errp, "Hot-plugged device without ROM bar" 2342 " can't have an option ROM"); 2343 return; 2344 } 2345 2346 if (class == 0x0300) { 2347 rom_add_vga(pdev->romfile); 2348 } else { 2349 rom_add_option(pdev->romfile, -1); 2350 } 2351 return; 2352 } 2353 2354 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2355 if (path == NULL) { 2356 path = g_strdup(pdev->romfile); 2357 } 2358 2359 size = get_image_size(path); 2360 if (size < 0) { 2361 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2362 g_free(path); 2363 return; 2364 } else if (size == 0) { 2365 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2366 g_free(path); 2367 return; 2368 } 2369 size = pow2ceil(size); 2370 2371 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2372 2373 if (vmsd) { 2374 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2375 } else { 2376 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2377 } 2378 pdev->has_rom = true; 2379 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2380 ptr = memory_region_get_ram_ptr(&pdev->rom); 2381 if (load_image_size(path, ptr, size) < 0) { 2382 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2383 g_free(path); 2384 return; 2385 } 2386 g_free(path); 2387 2388 if (is_default_rom) { 2389 /* Only the default rom images will be patched (if needed). */ 2390 pci_patch_ids(pdev, ptr, size); 2391 } 2392 2393 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2394 } 2395 2396 static void pci_del_option_rom(PCIDevice *pdev) 2397 { 2398 if (!pdev->has_rom) 2399 return; 2400 2401 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2402 pdev->has_rom = false; 2403 } 2404 2405 /* 2406 * On success, pci_add_capability() returns a positive value 2407 * that the offset of the pci capability. 2408 * On failure, it sets an error and returns a negative error 2409 * code. 2410 */ 2411 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2412 uint8_t offset, uint8_t size, 2413 Error **errp) 2414 { 2415 uint8_t *config; 2416 int i, overlapping_cap; 2417 2418 if (!offset) { 2419 offset = pci_find_space(pdev, size); 2420 /* out of PCI config space is programming error */ 2421 assert(offset); 2422 } else { 2423 /* Verify that capabilities don't overlap. Note: device assignment 2424 * depends on this check to verify that the device is not broken. 2425 * Should never trigger for emulated devices, but it's helpful 2426 * for debugging these. */ 2427 for (i = offset; i < offset + size; i++) { 2428 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2429 if (overlapping_cap) { 2430 error_setg(errp, "%s:%02x:%02x.%x " 2431 "Attempt to add PCI capability %x at offset " 2432 "%x overlaps existing capability %x at offset %x", 2433 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2434 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2435 cap_id, offset, overlapping_cap, i); 2436 return -EINVAL; 2437 } 2438 } 2439 } 2440 2441 config = pdev->config + offset; 2442 config[PCI_CAP_LIST_ID] = cap_id; 2443 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2444 pdev->config[PCI_CAPABILITY_LIST] = offset; 2445 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2446 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2447 /* Make capability read-only by default */ 2448 memset(pdev->wmask + offset, 0, size); 2449 /* Check capability by default */ 2450 memset(pdev->cmask + offset, 0xFF, size); 2451 return offset; 2452 } 2453 2454 /* Unlink capability from the pci config space. */ 2455 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2456 { 2457 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2458 if (!offset) 2459 return; 2460 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2461 /* Make capability writable again */ 2462 memset(pdev->wmask + offset, 0xff, size); 2463 memset(pdev->w1cmask + offset, 0, size); 2464 /* Clear cmask as device-specific registers can't be checked */ 2465 memset(pdev->cmask + offset, 0, size); 2466 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2467 2468 if (!pdev->config[PCI_CAPABILITY_LIST]) 2469 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2470 } 2471 2472 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2473 { 2474 return pci_find_capability_list(pdev, cap_id, NULL); 2475 } 2476 2477 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2478 { 2479 PCIDevice *d = (PCIDevice *)dev; 2480 const pci_class_desc *desc; 2481 char ctxt[64]; 2482 PCIIORegion *r; 2483 int i, class; 2484 2485 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2486 desc = pci_class_descriptions; 2487 while (desc->desc && class != desc->class) 2488 desc++; 2489 if (desc->desc) { 2490 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2491 } else { 2492 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2493 } 2494 2495 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2496 "pci id %04x:%04x (sub %04x:%04x)\n", 2497 indent, "", ctxt, pci_dev_bus_num(d), 2498 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2499 pci_get_word(d->config + PCI_VENDOR_ID), 2500 pci_get_word(d->config + PCI_DEVICE_ID), 2501 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2502 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2503 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2504 r = &d->io_regions[i]; 2505 if (!r->size) 2506 continue; 2507 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2508 " [0x%"FMT_PCIBUS"]\n", 2509 indent, "", 2510 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2511 r->addr, r->addr + r->size - 1); 2512 } 2513 } 2514 2515 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2516 { 2517 PCIDevice *d = (PCIDevice *)dev; 2518 const char *name = NULL; 2519 const pci_class_desc *desc = pci_class_descriptions; 2520 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2521 2522 while (desc->desc && 2523 (class & ~desc->fw_ign_bits) != 2524 (desc->class & ~desc->fw_ign_bits)) { 2525 desc++; 2526 } 2527 2528 if (desc->desc) { 2529 name = desc->fw_name; 2530 } 2531 2532 if (name) { 2533 pstrcpy(buf, len, name); 2534 } else { 2535 snprintf(buf, len, "pci%04x,%04x", 2536 pci_get_word(d->config + PCI_VENDOR_ID), 2537 pci_get_word(d->config + PCI_DEVICE_ID)); 2538 } 2539 2540 return buf; 2541 } 2542 2543 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2544 { 2545 PCIDevice *d = (PCIDevice *)dev; 2546 char path[50], name[33]; 2547 int off; 2548 2549 off = snprintf(path, sizeof(path), "%s@%x", 2550 pci_dev_fw_name(dev, name, sizeof name), 2551 PCI_SLOT(d->devfn)); 2552 if (PCI_FUNC(d->devfn)) 2553 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2554 return g_strdup(path); 2555 } 2556 2557 static char *pcibus_get_dev_path(DeviceState *dev) 2558 { 2559 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2560 PCIDevice *t; 2561 int slot_depth; 2562 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2563 * 00 is added here to make this format compatible with 2564 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2565 * Slot.Function list specifies the slot and function numbers for all 2566 * devices on the path from root to the specific device. */ 2567 const char *root_bus_path; 2568 int root_bus_len; 2569 char slot[] = ":SS.F"; 2570 int slot_len = sizeof slot - 1 /* For '\0' */; 2571 int path_len; 2572 char *path, *p; 2573 int s; 2574 2575 root_bus_path = pci_root_bus_path(d); 2576 root_bus_len = strlen(root_bus_path); 2577 2578 /* Calculate # of slots on path between device and root. */; 2579 slot_depth = 0; 2580 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2581 ++slot_depth; 2582 } 2583 2584 path_len = root_bus_len + slot_len * slot_depth; 2585 2586 /* Allocate memory, fill in the terminating null byte. */ 2587 path = g_malloc(path_len + 1 /* For '\0' */); 2588 path[path_len] = '\0'; 2589 2590 memcpy(path, root_bus_path, root_bus_len); 2591 2592 /* Fill in slot numbers. We walk up from device to root, so need to print 2593 * them in the reverse order, last to first. */ 2594 p = path + path_len; 2595 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2596 p -= slot_len; 2597 s = snprintf(slot, sizeof slot, ":%02x.%x", 2598 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2599 assert(s == slot_len); 2600 memcpy(p, slot, slot_len); 2601 } 2602 2603 return path; 2604 } 2605 2606 static int pci_qdev_find_recursive(PCIBus *bus, 2607 const char *id, PCIDevice **pdev) 2608 { 2609 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2610 if (!qdev) { 2611 return -ENODEV; 2612 } 2613 2614 /* roughly check if given qdev is pci device */ 2615 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2616 *pdev = PCI_DEVICE(qdev); 2617 return 0; 2618 } 2619 return -EINVAL; 2620 } 2621 2622 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2623 { 2624 PCIHostState *host_bridge; 2625 int rc = -ENODEV; 2626 2627 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2628 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2629 if (!tmp) { 2630 rc = 0; 2631 break; 2632 } 2633 if (tmp != -ENODEV) { 2634 rc = tmp; 2635 } 2636 } 2637 2638 return rc; 2639 } 2640 2641 MemoryRegion *pci_address_space(PCIDevice *dev) 2642 { 2643 return pci_get_bus(dev)->address_space_mem; 2644 } 2645 2646 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2647 { 2648 return pci_get_bus(dev)->address_space_io; 2649 } 2650 2651 static void pci_device_class_init(ObjectClass *klass, void *data) 2652 { 2653 DeviceClass *k = DEVICE_CLASS(klass); 2654 2655 k->realize = pci_qdev_realize; 2656 k->unrealize = pci_qdev_unrealize; 2657 k->bus_type = TYPE_PCI_BUS; 2658 device_class_set_props(k, pci_props); 2659 } 2660 2661 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2662 { 2663 if (!object_class_is_abstract(klass)) { 2664 ObjectClass *conventional = 2665 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2666 ObjectClass *pcie = 2667 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2668 assert(conventional || pcie); 2669 } 2670 } 2671 2672 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2673 { 2674 PCIBus *bus = pci_get_bus(dev); 2675 PCIBus *iommu_bus = bus; 2676 uint8_t devfn = dev->devfn; 2677 2678 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2679 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2680 2681 /* 2682 * The requester ID of the provided device may be aliased, as seen from 2683 * the IOMMU, due to topology limitations. The IOMMU relies on a 2684 * requester ID to provide a unique AddressSpace for devices, but 2685 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2686 * to-PCI bridge creates and accepts transactions on behalf of down- 2687 * stream devices. When doing so, all downstream devices are masked 2688 * (aliased) behind a single requester ID. The requester ID used 2689 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2690 * bridges, with a PCIe capability indicating such, follow the 2691 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2692 * where the bridge uses the seconary bus as the bridge portion of the 2693 * requester ID and devfn of 00.0. For other bridges, typically those 2694 * found on the root complex such as the dmi-to-pci-bridge, we follow 2695 * the convention of typical bare-metal hardware, which uses the 2696 * requester ID of the bridge itself. There are device specific 2697 * exceptions to these rules, but these are the defaults that the 2698 * Linux kernel uses when determining DMA aliases itself and believed 2699 * to be true for the bare metal equivalents of the devices emulated 2700 * in QEMU. 2701 */ 2702 if (!pci_bus_is_express(iommu_bus)) { 2703 PCIDevice *parent = iommu_bus->parent_dev; 2704 2705 if (pci_is_express(parent) && 2706 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2707 devfn = PCI_DEVFN(0, 0); 2708 bus = iommu_bus; 2709 } else { 2710 devfn = parent->devfn; 2711 bus = parent_bus; 2712 } 2713 } 2714 2715 iommu_bus = parent_bus; 2716 } 2717 if (iommu_bus && iommu_bus->iommu_fn) { 2718 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2719 } 2720 return &address_space_memory; 2721 } 2722 2723 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2724 { 2725 bus->iommu_fn = fn; 2726 bus->iommu_opaque = opaque; 2727 } 2728 2729 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2730 { 2731 Range *range = opaque; 2732 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2733 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2734 int i; 2735 2736 if (!(cmd & PCI_COMMAND_MEMORY)) { 2737 return; 2738 } 2739 2740 if (pc->is_bridge) { 2741 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2742 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2743 2744 base = MAX(base, 0x1ULL << 32); 2745 2746 if (limit >= base) { 2747 Range pref_range; 2748 range_set_bounds(&pref_range, base, limit); 2749 range_extend(range, &pref_range); 2750 } 2751 } 2752 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2753 PCIIORegion *r = &dev->io_regions[i]; 2754 pcibus_t lob, upb; 2755 Range region_range; 2756 2757 if (!r->size || 2758 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2759 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2760 continue; 2761 } 2762 2763 lob = pci_bar_address(dev, i, r->type, r->size); 2764 upb = lob + r->size - 1; 2765 if (lob == PCI_BAR_UNMAPPED) { 2766 continue; 2767 } 2768 2769 lob = MAX(lob, 0x1ULL << 32); 2770 2771 if (upb >= lob) { 2772 range_set_bounds(®ion_range, lob, upb); 2773 range_extend(range, ®ion_range); 2774 } 2775 } 2776 } 2777 2778 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2779 { 2780 range_make_empty(range); 2781 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2782 } 2783 2784 static bool pcie_has_upstream_port(PCIDevice *dev) 2785 { 2786 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2787 2788 /* Device associated with an upstream port. 2789 * As there are several types of these, it's easier to check the 2790 * parent device: upstream ports are always connected to 2791 * root or downstream ports. 2792 */ 2793 return parent_dev && 2794 pci_is_express(parent_dev) && 2795 parent_dev->exp.exp_cap && 2796 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2797 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2798 } 2799 2800 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2801 { 2802 PCIBus *bus = pci_get_bus(pci_dev); 2803 2804 if(pcie_has_upstream_port(pci_dev)) { 2805 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2806 return bus->devices[0]; 2807 } else { 2808 /* Other bus types might support multiple devices at slots 0-31 */ 2809 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2810 } 2811 } 2812 2813 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2814 { 2815 MSIMessage msg; 2816 if (msix_enabled(dev)) { 2817 msg = msix_get_message(dev, vector); 2818 } else if (msi_enabled(dev)) { 2819 msg = msi_get_message(dev, vector); 2820 } else { 2821 /* Should never happen */ 2822 error_report("%s: unknown interrupt type", __func__); 2823 abort(); 2824 } 2825 return msg; 2826 } 2827 2828 static const TypeInfo pci_device_type_info = { 2829 .name = TYPE_PCI_DEVICE, 2830 .parent = TYPE_DEVICE, 2831 .instance_size = sizeof(PCIDevice), 2832 .abstract = true, 2833 .class_size = sizeof(PCIDeviceClass), 2834 .class_init = pci_device_class_init, 2835 .class_base_init = pci_device_class_base_init, 2836 }; 2837 2838 static void pci_register_types(void) 2839 { 2840 type_register_static(&pci_bus_info); 2841 type_register_static(&pcie_bus_info); 2842 type_register_static(&conventional_pci_interface_info); 2843 type_register_static(&pcie_interface_info); 2844 type_register_static(&pci_device_type_info); 2845 } 2846 2847 type_init(pci_register_types) 2848