1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "hw/irq.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bridge.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/qemu-file-types.h" 34 #include "migration/vmstate.h" 35 #include "monitor/monitor.h" 36 #include "net/net.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/loader.h" 40 #include "qemu/error-report.h" 41 #include "qemu/range.h" 42 #include "trace.h" 43 #include "hw/pci/msi.h" 44 #include "hw/pci/msix.h" 45 #include "exec/address-spaces.h" 46 #include "hw/hotplug.h" 47 #include "hw/boards.h" 48 #include "qapi/error.h" 49 #include "qapi/qapi-commands-misc.h" 50 #include "qemu/cutils.h" 51 52 //#define DEBUG_PCI 53 #ifdef DEBUG_PCI 54 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 55 #else 56 # define PCI_DPRINTF(format, ...) do { } while (0) 57 #endif 58 59 bool pci_available = true; 60 61 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 62 static char *pcibus_get_dev_path(DeviceState *dev); 63 static char *pcibus_get_fw_dev_path(DeviceState *dev); 64 static void pcibus_reset(BusState *qbus); 65 66 static Property pci_props[] = { 67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 70 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 72 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 73 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 74 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 75 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 76 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 77 failover_pair_id), 78 DEFINE_PROP_END_OF_LIST() 79 }; 80 81 static const VMStateDescription vmstate_pcibus = { 82 .name = "PCIBUS", 83 .version_id = 1, 84 .minimum_version_id = 1, 85 .fields = (VMStateField[]) { 86 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 87 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 88 nirq, 0, vmstate_info_int32, 89 int32_t), 90 VMSTATE_END_OF_LIST() 91 } 92 }; 93 94 static void pci_init_bus_master(PCIDevice *pci_dev) 95 { 96 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 97 98 memory_region_init_alias(&pci_dev->bus_master_enable_region, 99 OBJECT(pci_dev), "bus master", 100 dma_as->root, 0, memory_region_size(dma_as->root)); 101 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 102 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 103 &pci_dev->bus_master_enable_region); 104 } 105 106 static void pcibus_machine_done(Notifier *notifier, void *data) 107 { 108 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 109 int i; 110 111 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 112 if (bus->devices[i]) { 113 pci_init_bus_master(bus->devices[i]); 114 } 115 } 116 } 117 118 static void pci_bus_realize(BusState *qbus, Error **errp) 119 { 120 PCIBus *bus = PCI_BUS(qbus); 121 122 bus->machine_done.notify = pcibus_machine_done; 123 qemu_add_machine_init_done_notifier(&bus->machine_done); 124 125 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 126 } 127 128 static void pcie_bus_realize(BusState *qbus, Error **errp) 129 { 130 PCIBus *bus = PCI_BUS(qbus); 131 132 pci_bus_realize(qbus, errp); 133 134 /* 135 * A PCI-E bus can support extended config space if it's the root 136 * bus, or if the bus/bridge above it does as well 137 */ 138 if (pci_bus_is_root(bus)) { 139 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 140 } else { 141 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 142 143 if (pci_bus_allows_extended_config_space(parent_bus)) { 144 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 145 } 146 } 147 } 148 149 static void pci_bus_unrealize(BusState *qbus, Error **errp) 150 { 151 PCIBus *bus = PCI_BUS(qbus); 152 153 qemu_remove_machine_init_done_notifier(&bus->machine_done); 154 155 vmstate_unregister(NULL, &vmstate_pcibus, bus); 156 } 157 158 static int pcibus_num(PCIBus *bus) 159 { 160 if (pci_bus_is_root(bus)) { 161 return 0; /* pci host bridge */ 162 } 163 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 164 } 165 166 static uint16_t pcibus_numa_node(PCIBus *bus) 167 { 168 return NUMA_NODE_UNASSIGNED; 169 } 170 171 static void pci_bus_class_init(ObjectClass *klass, void *data) 172 { 173 BusClass *k = BUS_CLASS(klass); 174 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 175 176 k->print_dev = pcibus_dev_print; 177 k->get_dev_path = pcibus_get_dev_path; 178 k->get_fw_dev_path = pcibus_get_fw_dev_path; 179 k->realize = pci_bus_realize; 180 k->unrealize = pci_bus_unrealize; 181 k->reset = pcibus_reset; 182 183 pbc->bus_num = pcibus_num; 184 pbc->numa_node = pcibus_numa_node; 185 } 186 187 static const TypeInfo pci_bus_info = { 188 .name = TYPE_PCI_BUS, 189 .parent = TYPE_BUS, 190 .instance_size = sizeof(PCIBus), 191 .class_size = sizeof(PCIBusClass), 192 .class_init = pci_bus_class_init, 193 }; 194 195 static const TypeInfo pcie_interface_info = { 196 .name = INTERFACE_PCIE_DEVICE, 197 .parent = TYPE_INTERFACE, 198 }; 199 200 static const TypeInfo conventional_pci_interface_info = { 201 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 202 .parent = TYPE_INTERFACE, 203 }; 204 205 static void pcie_bus_class_init(ObjectClass *klass, void *data) 206 { 207 BusClass *k = BUS_CLASS(klass); 208 209 k->realize = pcie_bus_realize; 210 } 211 212 static const TypeInfo pcie_bus_info = { 213 .name = TYPE_PCIE_BUS, 214 .parent = TYPE_PCI_BUS, 215 .class_init = pcie_bus_class_init, 216 }; 217 218 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 219 static void pci_update_mappings(PCIDevice *d); 220 static void pci_irq_handler(void *opaque, int irq_num, int level); 221 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 222 static void pci_del_option_rom(PCIDevice *pdev); 223 224 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 225 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 226 227 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 228 229 int pci_bar(PCIDevice *d, int reg) 230 { 231 uint8_t type; 232 233 if (reg != PCI_ROM_SLOT) 234 return PCI_BASE_ADDRESS_0 + reg * 4; 235 236 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 237 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 238 } 239 240 static inline int pci_irq_state(PCIDevice *d, int irq_num) 241 { 242 return (d->irq_state >> irq_num) & 0x1; 243 } 244 245 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 246 { 247 d->irq_state &= ~(0x1 << irq_num); 248 d->irq_state |= level << irq_num; 249 } 250 251 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 252 { 253 PCIBus *bus; 254 for (;;) { 255 bus = pci_get_bus(pci_dev); 256 irq_num = bus->map_irq(pci_dev, irq_num); 257 if (bus->set_irq) 258 break; 259 pci_dev = bus->parent_dev; 260 } 261 bus->irq_count[irq_num] += change; 262 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 263 } 264 265 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 266 { 267 assert(irq_num >= 0); 268 assert(irq_num < bus->nirq); 269 return !!bus->irq_count[irq_num]; 270 } 271 272 /* Update interrupt status bit in config space on interrupt 273 * state change. */ 274 static void pci_update_irq_status(PCIDevice *dev) 275 { 276 if (dev->irq_state) { 277 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 278 } else { 279 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 280 } 281 } 282 283 void pci_device_deassert_intx(PCIDevice *dev) 284 { 285 int i; 286 for (i = 0; i < PCI_NUM_PINS; ++i) { 287 pci_irq_handler(dev, i, 0); 288 } 289 } 290 291 static void pci_do_device_reset(PCIDevice *dev) 292 { 293 int r; 294 295 pci_device_deassert_intx(dev); 296 assert(dev->irq_state == 0); 297 298 /* Clear all writable bits */ 299 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 300 pci_get_word(dev->wmask + PCI_COMMAND) | 301 pci_get_word(dev->w1cmask + PCI_COMMAND)); 302 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 303 pci_get_word(dev->wmask + PCI_STATUS) | 304 pci_get_word(dev->w1cmask + PCI_STATUS)); 305 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 306 dev->config[PCI_INTERRUPT_LINE] = 0x0; 307 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 308 PCIIORegion *region = &dev->io_regions[r]; 309 if (!region->size) { 310 continue; 311 } 312 313 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 314 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 315 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 316 } else { 317 pci_set_long(dev->config + pci_bar(dev, r), region->type); 318 } 319 } 320 pci_update_mappings(dev); 321 322 msi_reset(dev); 323 msix_reset(dev); 324 } 325 326 /* 327 * This function is called on #RST and FLR. 328 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 329 */ 330 void pci_device_reset(PCIDevice *dev) 331 { 332 qdev_reset_all(&dev->qdev); 333 pci_do_device_reset(dev); 334 } 335 336 /* 337 * Trigger pci bus reset under a given bus. 338 * Called via qbus_reset_all on RST# assert, after the devices 339 * have been reset qdev_reset_all-ed already. 340 */ 341 static void pcibus_reset(BusState *qbus) 342 { 343 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 344 int i; 345 346 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 347 if (bus->devices[i]) { 348 pci_do_device_reset(bus->devices[i]); 349 } 350 } 351 352 for (i = 0; i < bus->nirq; i++) { 353 assert(bus->irq_count[i] == 0); 354 } 355 } 356 357 static void pci_host_bus_register(DeviceState *host) 358 { 359 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 360 361 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 362 } 363 364 static void pci_host_bus_unregister(DeviceState *host) 365 { 366 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 367 368 QLIST_REMOVE(host_bridge, next); 369 } 370 371 PCIBus *pci_device_root_bus(const PCIDevice *d) 372 { 373 PCIBus *bus = pci_get_bus(d); 374 375 while (!pci_bus_is_root(bus)) { 376 d = bus->parent_dev; 377 assert(d != NULL); 378 379 bus = pci_get_bus(d); 380 } 381 382 return bus; 383 } 384 385 const char *pci_root_bus_path(PCIDevice *dev) 386 { 387 PCIBus *rootbus = pci_device_root_bus(dev); 388 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 389 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 390 391 assert(host_bridge->bus == rootbus); 392 393 if (hc->root_bus_path) { 394 return (*hc->root_bus_path)(host_bridge, rootbus); 395 } 396 397 return rootbus->qbus.name; 398 } 399 400 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 401 MemoryRegion *address_space_mem, 402 MemoryRegion *address_space_io, 403 uint8_t devfn_min) 404 { 405 assert(PCI_FUNC(devfn_min) == 0); 406 bus->devfn_min = devfn_min; 407 bus->slot_reserved_mask = 0x0; 408 bus->address_space_mem = address_space_mem; 409 bus->address_space_io = address_space_io; 410 bus->flags |= PCI_BUS_IS_ROOT; 411 412 /* host bridge */ 413 QLIST_INIT(&bus->child); 414 415 pci_host_bus_register(parent); 416 } 417 418 static void pci_bus_uninit(PCIBus *bus) 419 { 420 pci_host_bus_unregister(BUS(bus)->parent); 421 } 422 423 bool pci_bus_is_express(PCIBus *bus) 424 { 425 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 426 } 427 428 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 429 const char *name, 430 MemoryRegion *address_space_mem, 431 MemoryRegion *address_space_io, 432 uint8_t devfn_min, const char *typename) 433 { 434 qbus_create_inplace(bus, bus_size, typename, parent, name); 435 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 436 devfn_min); 437 } 438 439 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 440 MemoryRegion *address_space_mem, 441 MemoryRegion *address_space_io, 442 uint8_t devfn_min, const char *typename) 443 { 444 PCIBus *bus; 445 446 bus = PCI_BUS(qbus_create(typename, parent, name)); 447 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 448 devfn_min); 449 return bus; 450 } 451 452 void pci_root_bus_cleanup(PCIBus *bus) 453 { 454 pci_bus_uninit(bus); 455 /* the caller of the unplug hotplug handler will delete this device */ 456 object_property_set_bool(OBJECT(bus), false, "realized", NULL); 457 } 458 459 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 460 void *irq_opaque, int nirq) 461 { 462 bus->set_irq = set_irq; 463 bus->map_irq = map_irq; 464 bus->irq_opaque = irq_opaque; 465 bus->nirq = nirq; 466 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 467 } 468 469 void pci_bus_irqs_cleanup(PCIBus *bus) 470 { 471 bus->set_irq = NULL; 472 bus->map_irq = NULL; 473 bus->irq_opaque = NULL; 474 bus->nirq = 0; 475 g_free(bus->irq_count); 476 } 477 478 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 479 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 480 void *irq_opaque, 481 MemoryRegion *address_space_mem, 482 MemoryRegion *address_space_io, 483 uint8_t devfn_min, int nirq, 484 const char *typename) 485 { 486 PCIBus *bus; 487 488 bus = pci_root_bus_new(parent, name, address_space_mem, 489 address_space_io, devfn_min, typename); 490 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 491 return bus; 492 } 493 494 void pci_unregister_root_bus(PCIBus *bus) 495 { 496 pci_bus_irqs_cleanup(bus); 497 pci_root_bus_cleanup(bus); 498 } 499 500 int pci_bus_num(PCIBus *s) 501 { 502 return PCI_BUS_GET_CLASS(s)->bus_num(s); 503 } 504 505 int pci_bus_numa_node(PCIBus *bus) 506 { 507 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 508 } 509 510 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 511 const VMStateField *field) 512 { 513 PCIDevice *s = container_of(pv, PCIDevice, config); 514 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 515 uint8_t *config; 516 int i; 517 518 assert(size == pci_config_size(s)); 519 config = g_malloc(size); 520 521 qemu_get_buffer(f, config, size); 522 for (i = 0; i < size; ++i) { 523 if ((config[i] ^ s->config[i]) & 524 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 525 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 526 "cmask: %x wmask: %x w1cmask:%x", __func__, 527 i, config[i], s->config[i], 528 s->cmask[i], s->wmask[i], s->w1cmask[i]); 529 g_free(config); 530 return -EINVAL; 531 } 532 } 533 memcpy(s->config, config, size); 534 535 pci_update_mappings(s); 536 if (pc->is_bridge) { 537 PCIBridge *b = PCI_BRIDGE(s); 538 pci_bridge_update_mappings(b); 539 } 540 541 memory_region_set_enabled(&s->bus_master_enable_region, 542 pci_get_word(s->config + PCI_COMMAND) 543 & PCI_COMMAND_MASTER); 544 545 g_free(config); 546 return 0; 547 } 548 549 /* just put buffer */ 550 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 551 const VMStateField *field, QJSON *vmdesc) 552 { 553 const uint8_t **v = pv; 554 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 555 qemu_put_buffer(f, *v, size); 556 557 return 0; 558 } 559 560 static VMStateInfo vmstate_info_pci_config = { 561 .name = "pci config", 562 .get = get_pci_config_device, 563 .put = put_pci_config_device, 564 }; 565 566 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 567 const VMStateField *field) 568 { 569 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 570 uint32_t irq_state[PCI_NUM_PINS]; 571 int i; 572 for (i = 0; i < PCI_NUM_PINS; ++i) { 573 irq_state[i] = qemu_get_be32(f); 574 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 575 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 576 irq_state[i]); 577 return -EINVAL; 578 } 579 } 580 581 for (i = 0; i < PCI_NUM_PINS; ++i) { 582 pci_set_irq_state(s, i, irq_state[i]); 583 } 584 585 return 0; 586 } 587 588 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 589 const VMStateField *field, QJSON *vmdesc) 590 { 591 int i; 592 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 593 594 for (i = 0; i < PCI_NUM_PINS; ++i) { 595 qemu_put_be32(f, pci_irq_state(s, i)); 596 } 597 598 return 0; 599 } 600 601 static VMStateInfo vmstate_info_pci_irq_state = { 602 .name = "pci irq state", 603 .get = get_pci_irq_state, 604 .put = put_pci_irq_state, 605 }; 606 607 static bool migrate_is_pcie(void *opaque, int version_id) 608 { 609 return pci_is_express((PCIDevice *)opaque); 610 } 611 612 static bool migrate_is_not_pcie(void *opaque, int version_id) 613 { 614 return !pci_is_express((PCIDevice *)opaque); 615 } 616 617 const VMStateDescription vmstate_pci_device = { 618 .name = "PCIDevice", 619 .version_id = 2, 620 .minimum_version_id = 1, 621 .fields = (VMStateField[]) { 622 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 623 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 624 migrate_is_not_pcie, 625 0, vmstate_info_pci_config, 626 PCI_CONFIG_SPACE_SIZE), 627 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 628 migrate_is_pcie, 629 0, vmstate_info_pci_config, 630 PCIE_CONFIG_SPACE_SIZE), 631 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 632 vmstate_info_pci_irq_state, 633 PCI_NUM_PINS * sizeof(int32_t)), 634 VMSTATE_END_OF_LIST() 635 } 636 }; 637 638 639 void pci_device_save(PCIDevice *s, QEMUFile *f) 640 { 641 /* Clear interrupt status bit: it is implicit 642 * in irq_state which we are saving. 643 * This makes us compatible with old devices 644 * which never set or clear this bit. */ 645 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 646 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 647 /* Restore the interrupt status bit. */ 648 pci_update_irq_status(s); 649 } 650 651 int pci_device_load(PCIDevice *s, QEMUFile *f) 652 { 653 int ret; 654 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 655 /* Restore the interrupt status bit. */ 656 pci_update_irq_status(s); 657 return ret; 658 } 659 660 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 661 { 662 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 663 pci_default_sub_vendor_id); 664 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 665 pci_default_sub_device_id); 666 } 667 668 /* 669 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 670 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 671 */ 672 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 673 unsigned int *slotp, unsigned int *funcp) 674 { 675 const char *p; 676 char *e; 677 unsigned long val; 678 unsigned long dom = 0, bus = 0; 679 unsigned int slot = 0; 680 unsigned int func = 0; 681 682 p = addr; 683 val = strtoul(p, &e, 16); 684 if (e == p) 685 return -1; 686 if (*e == ':') { 687 bus = val; 688 p = e + 1; 689 val = strtoul(p, &e, 16); 690 if (e == p) 691 return -1; 692 if (*e == ':') { 693 dom = bus; 694 bus = val; 695 p = e + 1; 696 val = strtoul(p, &e, 16); 697 if (e == p) 698 return -1; 699 } 700 } 701 702 slot = val; 703 704 if (funcp != NULL) { 705 if (*e != '.') 706 return -1; 707 708 p = e + 1; 709 val = strtoul(p, &e, 16); 710 if (e == p) 711 return -1; 712 713 func = val; 714 } 715 716 /* if funcp == NULL func is 0 */ 717 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 718 return -1; 719 720 if (*e) 721 return -1; 722 723 *domp = dom; 724 *busp = bus; 725 *slotp = slot; 726 if (funcp != NULL) 727 *funcp = func; 728 return 0; 729 } 730 731 static void pci_init_cmask(PCIDevice *dev) 732 { 733 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 734 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 735 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 736 dev->cmask[PCI_REVISION_ID] = 0xff; 737 dev->cmask[PCI_CLASS_PROG] = 0xff; 738 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 739 dev->cmask[PCI_HEADER_TYPE] = 0xff; 740 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 741 } 742 743 static void pci_init_wmask(PCIDevice *dev) 744 { 745 int config_size = pci_config_size(dev); 746 747 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 748 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 749 pci_set_word(dev->wmask + PCI_COMMAND, 750 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 751 PCI_COMMAND_INTX_DISABLE); 752 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 753 754 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 755 config_size - PCI_CONFIG_HEADER_SIZE); 756 } 757 758 static void pci_init_w1cmask(PCIDevice *dev) 759 { 760 /* 761 * Note: It's okay to set w1cmask even for readonly bits as 762 * long as their value is hardwired to 0. 763 */ 764 pci_set_word(dev->w1cmask + PCI_STATUS, 765 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 766 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 767 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 768 } 769 770 static void pci_init_mask_bridge(PCIDevice *d) 771 { 772 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 773 PCI_SEC_LETENCY_TIMER */ 774 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 775 776 /* base and limit */ 777 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 778 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 779 pci_set_word(d->wmask + PCI_MEMORY_BASE, 780 PCI_MEMORY_RANGE_MASK & 0xffff); 781 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 782 PCI_MEMORY_RANGE_MASK & 0xffff); 783 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 784 PCI_PREF_RANGE_MASK & 0xffff); 785 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 786 PCI_PREF_RANGE_MASK & 0xffff); 787 788 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 789 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 790 791 /* Supported memory and i/o types */ 792 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 793 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 794 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 795 PCI_PREF_RANGE_TYPE_64); 796 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 797 PCI_PREF_RANGE_TYPE_64); 798 799 /* 800 * TODO: Bridges default to 10-bit VGA decoding but we currently only 801 * implement 16-bit decoding (no alias support). 802 */ 803 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 804 PCI_BRIDGE_CTL_PARITY | 805 PCI_BRIDGE_CTL_SERR | 806 PCI_BRIDGE_CTL_ISA | 807 PCI_BRIDGE_CTL_VGA | 808 PCI_BRIDGE_CTL_VGA_16BIT | 809 PCI_BRIDGE_CTL_MASTER_ABORT | 810 PCI_BRIDGE_CTL_BUS_RESET | 811 PCI_BRIDGE_CTL_FAST_BACK | 812 PCI_BRIDGE_CTL_DISCARD | 813 PCI_BRIDGE_CTL_SEC_DISCARD | 814 PCI_BRIDGE_CTL_DISCARD_SERR); 815 /* Below does not do anything as we never set this bit, put here for 816 * completeness. */ 817 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 818 PCI_BRIDGE_CTL_DISCARD_STATUS); 819 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 820 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 821 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 822 PCI_PREF_RANGE_TYPE_MASK); 823 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 824 PCI_PREF_RANGE_TYPE_MASK); 825 } 826 827 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 828 { 829 uint8_t slot = PCI_SLOT(dev->devfn); 830 uint8_t func; 831 832 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 833 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 834 } 835 836 /* 837 * multifunction bit is interpreted in two ways as follows. 838 * - all functions must set the bit to 1. 839 * Example: Intel X53 840 * - function 0 must set the bit, but the rest function (> 0) 841 * is allowed to leave the bit to 0. 842 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 843 * 844 * So OS (at least Linux) checks the bit of only function 0, 845 * and doesn't see the bit of function > 0. 846 * 847 * The below check allows both interpretation. 848 */ 849 if (PCI_FUNC(dev->devfn)) { 850 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 851 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 852 /* function 0 should set multifunction bit */ 853 error_setg(errp, "PCI: single function device can't be populated " 854 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 855 return; 856 } 857 return; 858 } 859 860 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 861 return; 862 } 863 /* function 0 indicates single function, so function > 0 must be NULL */ 864 for (func = 1; func < PCI_FUNC_MAX; ++func) { 865 if (bus->devices[PCI_DEVFN(slot, func)]) { 866 error_setg(errp, "PCI: %x.0 indicates single function, " 867 "but %x.%x is already populated.", 868 slot, slot, func); 869 return; 870 } 871 } 872 } 873 874 static void pci_config_alloc(PCIDevice *pci_dev) 875 { 876 int config_size = pci_config_size(pci_dev); 877 878 pci_dev->config = g_malloc0(config_size); 879 pci_dev->cmask = g_malloc0(config_size); 880 pci_dev->wmask = g_malloc0(config_size); 881 pci_dev->w1cmask = g_malloc0(config_size); 882 pci_dev->used = g_malloc0(config_size); 883 } 884 885 static void pci_config_free(PCIDevice *pci_dev) 886 { 887 g_free(pci_dev->config); 888 g_free(pci_dev->cmask); 889 g_free(pci_dev->wmask); 890 g_free(pci_dev->w1cmask); 891 g_free(pci_dev->used); 892 } 893 894 static void do_pci_unregister_device(PCIDevice *pci_dev) 895 { 896 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 897 pci_config_free(pci_dev); 898 899 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 900 memory_region_del_subregion(&pci_dev->bus_master_container_region, 901 &pci_dev->bus_master_enable_region); 902 } 903 address_space_destroy(&pci_dev->bus_master_as); 904 } 905 906 /* Extract PCIReqIDCache into BDF format */ 907 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 908 { 909 uint8_t bus_n; 910 uint16_t result; 911 912 switch (cache->type) { 913 case PCI_REQ_ID_BDF: 914 result = pci_get_bdf(cache->dev); 915 break; 916 case PCI_REQ_ID_SECONDARY_BUS: 917 bus_n = pci_dev_bus_num(cache->dev); 918 result = PCI_BUILD_BDF(bus_n, 0); 919 break; 920 default: 921 error_report("Invalid PCI requester ID cache type: %d", 922 cache->type); 923 exit(1); 924 break; 925 } 926 927 return result; 928 } 929 930 /* Parse bridges up to the root complex and return requester ID 931 * cache for specific device. For full PCIe topology, the cache 932 * result would be exactly the same as getting BDF of the device. 933 * However, several tricks are required when system mixed up with 934 * legacy PCI devices and PCIe-to-PCI bridges. 935 * 936 * Here we cache the proxy device (and type) not requester ID since 937 * bus number might change from time to time. 938 */ 939 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 940 { 941 PCIDevice *parent; 942 PCIReqIDCache cache = { 943 .dev = dev, 944 .type = PCI_REQ_ID_BDF, 945 }; 946 947 while (!pci_bus_is_root(pci_get_bus(dev))) { 948 /* We are under PCI/PCIe bridges */ 949 parent = pci_get_bus(dev)->parent_dev; 950 if (pci_is_express(parent)) { 951 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 952 /* When we pass through PCIe-to-PCI/PCIX bridges, we 953 * override the requester ID using secondary bus 954 * number of parent bridge with zeroed devfn 955 * (pcie-to-pci bridge spec chap 2.3). */ 956 cache.type = PCI_REQ_ID_SECONDARY_BUS; 957 cache.dev = dev; 958 } 959 } else { 960 /* Legacy PCI, override requester ID with the bridge's 961 * BDF upstream. When the root complex connects to 962 * legacy PCI devices (including buses), it can only 963 * obtain requester ID info from directly attached 964 * devices. If devices are attached under bridges, only 965 * the requester ID of the bridge that is directly 966 * attached to the root complex can be recognized. */ 967 cache.type = PCI_REQ_ID_BDF; 968 cache.dev = parent; 969 } 970 dev = parent; 971 } 972 973 return cache; 974 } 975 976 uint16_t pci_requester_id(PCIDevice *dev) 977 { 978 return pci_req_id_cache_extract(&dev->requester_id_cache); 979 } 980 981 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 982 { 983 return !(bus->devices[devfn]); 984 } 985 986 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 987 { 988 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 989 } 990 991 /* -1 for devfn means auto assign */ 992 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 993 const char *name, int devfn, 994 Error **errp) 995 { 996 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 997 PCIConfigReadFunc *config_read = pc->config_read; 998 PCIConfigWriteFunc *config_write = pc->config_write; 999 Error *local_err = NULL; 1000 DeviceState *dev = DEVICE(pci_dev); 1001 PCIBus *bus = pci_get_bus(pci_dev); 1002 1003 /* Only pci bridges can be attached to extra PCI root buses */ 1004 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1005 error_setg(errp, 1006 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1007 bus->parent_dev->name); 1008 return NULL; 1009 } 1010 1011 if (devfn < 0) { 1012 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1013 devfn += PCI_FUNC_MAX) { 1014 if (pci_bus_devfn_available(bus, devfn) && 1015 !pci_bus_devfn_reserved(bus, devfn)) { 1016 goto found; 1017 } 1018 } 1019 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1020 "or reserved", name); 1021 return NULL; 1022 found: ; 1023 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1024 error_setg(errp, "PCI: slot %d function %d not available for %s," 1025 " reserved", 1026 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1027 return NULL; 1028 } else if (!pci_bus_devfn_available(bus, devfn)) { 1029 error_setg(errp, "PCI: slot %d function %d not available for %s," 1030 " in use by %s", 1031 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1032 bus->devices[devfn]->name); 1033 return NULL; 1034 } else if (dev->hotplugged && 1035 pci_get_function_0(pci_dev)) { 1036 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1037 " new func %s cannot be exposed to guest.", 1038 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1039 pci_get_function_0(pci_dev)->name, 1040 name); 1041 1042 return NULL; 1043 } 1044 1045 pci_dev->devfn = devfn; 1046 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1047 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1048 1049 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1050 "bus master container", UINT64_MAX); 1051 address_space_init(&pci_dev->bus_master_as, 1052 &pci_dev->bus_master_container_region, pci_dev->name); 1053 1054 if (qdev_hotplug) { 1055 pci_init_bus_master(pci_dev); 1056 } 1057 pci_dev->irq_state = 0; 1058 pci_config_alloc(pci_dev); 1059 1060 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1061 pci_config_set_device_id(pci_dev->config, pc->device_id); 1062 pci_config_set_revision(pci_dev->config, pc->revision); 1063 pci_config_set_class(pci_dev->config, pc->class_id); 1064 1065 if (!pc->is_bridge) { 1066 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1067 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1068 pc->subsystem_vendor_id); 1069 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1070 pc->subsystem_id); 1071 } else { 1072 pci_set_default_subsystem_id(pci_dev); 1073 } 1074 } else { 1075 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1076 assert(!pc->subsystem_vendor_id); 1077 assert(!pc->subsystem_id); 1078 } 1079 pci_init_cmask(pci_dev); 1080 pci_init_wmask(pci_dev); 1081 pci_init_w1cmask(pci_dev); 1082 if (pc->is_bridge) { 1083 pci_init_mask_bridge(pci_dev); 1084 } 1085 pci_init_multifunction(bus, pci_dev, &local_err); 1086 if (local_err) { 1087 error_propagate(errp, local_err); 1088 do_pci_unregister_device(pci_dev); 1089 return NULL; 1090 } 1091 1092 if (!config_read) 1093 config_read = pci_default_read_config; 1094 if (!config_write) 1095 config_write = pci_default_write_config; 1096 pci_dev->config_read = config_read; 1097 pci_dev->config_write = config_write; 1098 bus->devices[devfn] = pci_dev; 1099 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1100 return pci_dev; 1101 } 1102 1103 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1104 { 1105 PCIIORegion *r; 1106 int i; 1107 1108 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1109 r = &pci_dev->io_regions[i]; 1110 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1111 continue; 1112 memory_region_del_subregion(r->address_space, r->memory); 1113 } 1114 1115 pci_unregister_vga(pci_dev); 1116 } 1117 1118 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1119 { 1120 PCIDevice *pci_dev = PCI_DEVICE(dev); 1121 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1122 1123 pci_unregister_io_regions(pci_dev); 1124 pci_del_option_rom(pci_dev); 1125 1126 if (pc->exit) { 1127 pc->exit(pci_dev); 1128 } 1129 1130 pci_device_deassert_intx(pci_dev); 1131 do_pci_unregister_device(pci_dev); 1132 } 1133 1134 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1135 uint8_t type, MemoryRegion *memory) 1136 { 1137 PCIIORegion *r; 1138 uint32_t addr; /* offset in pci config space */ 1139 uint64_t wmask; 1140 pcibus_t size = memory_region_size(memory); 1141 1142 assert(region_num >= 0); 1143 assert(region_num < PCI_NUM_REGIONS); 1144 if (size & (size-1)) { 1145 error_report("ERROR: PCI region size must be pow2 " 1146 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size); 1147 exit(1); 1148 } 1149 1150 r = &pci_dev->io_regions[region_num]; 1151 r->addr = PCI_BAR_UNMAPPED; 1152 r->size = size; 1153 r->type = type; 1154 r->memory = memory; 1155 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1156 ? pci_get_bus(pci_dev)->address_space_io 1157 : pci_get_bus(pci_dev)->address_space_mem; 1158 1159 wmask = ~(size - 1); 1160 if (region_num == PCI_ROM_SLOT) { 1161 /* ROM enable bit is writable */ 1162 wmask |= PCI_ROM_ADDRESS_ENABLE; 1163 } 1164 1165 addr = pci_bar(pci_dev, region_num); 1166 pci_set_long(pci_dev->config + addr, type); 1167 1168 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1169 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1170 pci_set_quad(pci_dev->wmask + addr, wmask); 1171 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1172 } else { 1173 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1174 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1175 } 1176 } 1177 1178 static void pci_update_vga(PCIDevice *pci_dev) 1179 { 1180 uint16_t cmd; 1181 1182 if (!pci_dev->has_vga) { 1183 return; 1184 } 1185 1186 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1187 1188 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1189 cmd & PCI_COMMAND_MEMORY); 1190 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1191 cmd & PCI_COMMAND_IO); 1192 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1193 cmd & PCI_COMMAND_IO); 1194 } 1195 1196 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1197 MemoryRegion *io_lo, MemoryRegion *io_hi) 1198 { 1199 PCIBus *bus = pci_get_bus(pci_dev); 1200 1201 assert(!pci_dev->has_vga); 1202 1203 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1204 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1205 memory_region_add_subregion_overlap(bus->address_space_mem, 1206 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1207 1208 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1209 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1210 memory_region_add_subregion_overlap(bus->address_space_io, 1211 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1212 1213 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1214 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1215 memory_region_add_subregion_overlap(bus->address_space_io, 1216 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1217 pci_dev->has_vga = true; 1218 1219 pci_update_vga(pci_dev); 1220 } 1221 1222 void pci_unregister_vga(PCIDevice *pci_dev) 1223 { 1224 PCIBus *bus = pci_get_bus(pci_dev); 1225 1226 if (!pci_dev->has_vga) { 1227 return; 1228 } 1229 1230 memory_region_del_subregion(bus->address_space_mem, 1231 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1232 memory_region_del_subregion(bus->address_space_io, 1233 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1234 memory_region_del_subregion(bus->address_space_io, 1235 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1236 pci_dev->has_vga = false; 1237 } 1238 1239 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1240 { 1241 return pci_dev->io_regions[region_num].addr; 1242 } 1243 1244 static pcibus_t pci_bar_address(PCIDevice *d, 1245 int reg, uint8_t type, pcibus_t size) 1246 { 1247 pcibus_t new_addr, last_addr; 1248 int bar = pci_bar(d, reg); 1249 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1250 Object *machine = qdev_get_machine(); 1251 ObjectClass *oc = object_get_class(machine); 1252 MachineClass *mc = MACHINE_CLASS(oc); 1253 bool allow_0_address = mc->pci_allow_0_address; 1254 1255 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1256 if (!(cmd & PCI_COMMAND_IO)) { 1257 return PCI_BAR_UNMAPPED; 1258 } 1259 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1260 last_addr = new_addr + size - 1; 1261 /* Check if 32 bit BAR wraps around explicitly. 1262 * TODO: make priorities correct and remove this work around. 1263 */ 1264 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1265 (!allow_0_address && new_addr == 0)) { 1266 return PCI_BAR_UNMAPPED; 1267 } 1268 return new_addr; 1269 } 1270 1271 if (!(cmd & PCI_COMMAND_MEMORY)) { 1272 return PCI_BAR_UNMAPPED; 1273 } 1274 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1275 new_addr = pci_get_quad(d->config + bar); 1276 } else { 1277 new_addr = pci_get_long(d->config + bar); 1278 } 1279 /* the ROM slot has a specific enable bit */ 1280 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1281 return PCI_BAR_UNMAPPED; 1282 } 1283 new_addr &= ~(size - 1); 1284 last_addr = new_addr + size - 1; 1285 /* NOTE: we do not support wrapping */ 1286 /* XXX: as we cannot support really dynamic 1287 mappings, we handle specific values as invalid 1288 mappings. */ 1289 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1290 (!allow_0_address && new_addr == 0)) { 1291 return PCI_BAR_UNMAPPED; 1292 } 1293 1294 /* Now pcibus_t is 64bit. 1295 * Check if 32 bit BAR wraps around explicitly. 1296 * Without this, PC ide doesn't work well. 1297 * TODO: remove this work around. 1298 */ 1299 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1300 return PCI_BAR_UNMAPPED; 1301 } 1302 1303 /* 1304 * OS is allowed to set BAR beyond its addressable 1305 * bits. For example, 32 bit OS can set 64bit bar 1306 * to >4G. Check it. TODO: we might need to support 1307 * it in the future for e.g. PAE. 1308 */ 1309 if (last_addr >= HWADDR_MAX) { 1310 return PCI_BAR_UNMAPPED; 1311 } 1312 1313 return new_addr; 1314 } 1315 1316 static void pci_update_mappings(PCIDevice *d) 1317 { 1318 PCIIORegion *r; 1319 int i; 1320 pcibus_t new_addr; 1321 1322 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1323 r = &d->io_regions[i]; 1324 1325 /* this region isn't registered */ 1326 if (!r->size) 1327 continue; 1328 1329 new_addr = pci_bar_address(d, i, r->type, r->size); 1330 1331 /* This bar isn't changed */ 1332 if (new_addr == r->addr) 1333 continue; 1334 1335 /* now do the real mapping */ 1336 if (r->addr != PCI_BAR_UNMAPPED) { 1337 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1338 PCI_SLOT(d->devfn), 1339 PCI_FUNC(d->devfn), 1340 i, r->addr, r->size); 1341 memory_region_del_subregion(r->address_space, r->memory); 1342 } 1343 r->addr = new_addr; 1344 if (r->addr != PCI_BAR_UNMAPPED) { 1345 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1346 PCI_SLOT(d->devfn), 1347 PCI_FUNC(d->devfn), 1348 i, r->addr, r->size); 1349 memory_region_add_subregion_overlap(r->address_space, 1350 r->addr, r->memory, 1); 1351 } 1352 } 1353 1354 pci_update_vga(d); 1355 } 1356 1357 static inline int pci_irq_disabled(PCIDevice *d) 1358 { 1359 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1360 } 1361 1362 /* Called after interrupt disabled field update in config space, 1363 * assert/deassert interrupts if necessary. 1364 * Gets original interrupt disable bit value (before update). */ 1365 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1366 { 1367 int i, disabled = pci_irq_disabled(d); 1368 if (disabled == was_irq_disabled) 1369 return; 1370 for (i = 0; i < PCI_NUM_PINS; ++i) { 1371 int state = pci_irq_state(d, i); 1372 pci_change_irq_level(d, i, disabled ? -state : state); 1373 } 1374 } 1375 1376 uint32_t pci_default_read_config(PCIDevice *d, 1377 uint32_t address, int len) 1378 { 1379 uint32_t val = 0; 1380 1381 if (pci_is_express_downstream_port(d) && 1382 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1383 pcie_sync_bridge_lnk(d); 1384 } 1385 memcpy(&val, d->config + address, len); 1386 return le32_to_cpu(val); 1387 } 1388 1389 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1390 { 1391 int i, was_irq_disabled = pci_irq_disabled(d); 1392 uint32_t val = val_in; 1393 1394 for (i = 0; i < l; val >>= 8, ++i) { 1395 uint8_t wmask = d->wmask[addr + i]; 1396 uint8_t w1cmask = d->w1cmask[addr + i]; 1397 assert(!(wmask & w1cmask)); 1398 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1399 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1400 } 1401 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1402 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1403 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1404 range_covers_byte(addr, l, PCI_COMMAND)) 1405 pci_update_mappings(d); 1406 1407 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1408 pci_update_irq_disabled(d, was_irq_disabled); 1409 memory_region_set_enabled(&d->bus_master_enable_region, 1410 pci_get_word(d->config + PCI_COMMAND) 1411 & PCI_COMMAND_MASTER); 1412 } 1413 1414 msi_write_config(d, addr, val_in, l); 1415 msix_write_config(d, addr, val_in, l); 1416 } 1417 1418 /***********************************************************/ 1419 /* generic PCI irq support */ 1420 1421 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1422 static void pci_irq_handler(void *opaque, int irq_num, int level) 1423 { 1424 PCIDevice *pci_dev = opaque; 1425 int change; 1426 1427 change = level - pci_irq_state(pci_dev, irq_num); 1428 if (!change) 1429 return; 1430 1431 pci_set_irq_state(pci_dev, irq_num, level); 1432 pci_update_irq_status(pci_dev); 1433 if (pci_irq_disabled(pci_dev)) 1434 return; 1435 pci_change_irq_level(pci_dev, irq_num, change); 1436 } 1437 1438 static inline int pci_intx(PCIDevice *pci_dev) 1439 { 1440 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1441 } 1442 1443 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1444 { 1445 int intx = pci_intx(pci_dev); 1446 1447 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1448 } 1449 1450 void pci_set_irq(PCIDevice *pci_dev, int level) 1451 { 1452 int intx = pci_intx(pci_dev); 1453 pci_irq_handler(pci_dev, intx, level); 1454 } 1455 1456 /* Special hooks used by device assignment */ 1457 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1458 { 1459 assert(pci_bus_is_root(bus)); 1460 bus->route_intx_to_irq = route_intx_to_irq; 1461 } 1462 1463 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1464 { 1465 PCIBus *bus; 1466 1467 do { 1468 bus = pci_get_bus(dev); 1469 pin = bus->map_irq(dev, pin); 1470 dev = bus->parent_dev; 1471 } while (dev); 1472 1473 if (!bus->route_intx_to_irq) { 1474 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1475 object_get_typename(OBJECT(bus->qbus.parent))); 1476 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1477 } 1478 1479 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1480 } 1481 1482 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1483 { 1484 return old->mode != new->mode || old->irq != new->irq; 1485 } 1486 1487 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1488 { 1489 PCIDevice *dev; 1490 PCIBus *sec; 1491 int i; 1492 1493 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1494 dev = bus->devices[i]; 1495 if (dev && dev->intx_routing_notifier) { 1496 dev->intx_routing_notifier(dev); 1497 } 1498 } 1499 1500 QLIST_FOREACH(sec, &bus->child, sibling) { 1501 pci_bus_fire_intx_routing_notifier(sec); 1502 } 1503 } 1504 1505 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1506 PCIINTxRoutingNotifier notifier) 1507 { 1508 dev->intx_routing_notifier = notifier; 1509 } 1510 1511 /* 1512 * PCI-to-PCI bridge specification 1513 * 9.1: Interrupt routing. Table 9-1 1514 * 1515 * the PCI Express Base Specification, Revision 2.1 1516 * 2.2.8.1: INTx interrutp signaling - Rules 1517 * the Implementation Note 1518 * Table 2-20 1519 */ 1520 /* 1521 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1522 * 0-origin unlike PCI interrupt pin register. 1523 */ 1524 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1525 { 1526 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1527 } 1528 1529 /***********************************************************/ 1530 /* monitor info on PCI */ 1531 1532 typedef struct { 1533 uint16_t class; 1534 const char *desc; 1535 const char *fw_name; 1536 uint16_t fw_ign_bits; 1537 } pci_class_desc; 1538 1539 static const pci_class_desc pci_class_descriptions[] = 1540 { 1541 { 0x0001, "VGA controller", "display"}, 1542 { 0x0100, "SCSI controller", "scsi"}, 1543 { 0x0101, "IDE controller", "ide"}, 1544 { 0x0102, "Floppy controller", "fdc"}, 1545 { 0x0103, "IPI controller", "ipi"}, 1546 { 0x0104, "RAID controller", "raid"}, 1547 { 0x0106, "SATA controller"}, 1548 { 0x0107, "SAS controller"}, 1549 { 0x0180, "Storage controller"}, 1550 { 0x0200, "Ethernet controller", "ethernet"}, 1551 { 0x0201, "Token Ring controller", "token-ring"}, 1552 { 0x0202, "FDDI controller", "fddi"}, 1553 { 0x0203, "ATM controller", "atm"}, 1554 { 0x0280, "Network controller"}, 1555 { 0x0300, "VGA controller", "display", 0x00ff}, 1556 { 0x0301, "XGA controller"}, 1557 { 0x0302, "3D controller"}, 1558 { 0x0380, "Display controller"}, 1559 { 0x0400, "Video controller", "video"}, 1560 { 0x0401, "Audio controller", "sound"}, 1561 { 0x0402, "Phone"}, 1562 { 0x0403, "Audio controller", "sound"}, 1563 { 0x0480, "Multimedia controller"}, 1564 { 0x0500, "RAM controller", "memory"}, 1565 { 0x0501, "Flash controller", "flash"}, 1566 { 0x0580, "Memory controller"}, 1567 { 0x0600, "Host bridge", "host"}, 1568 { 0x0601, "ISA bridge", "isa"}, 1569 { 0x0602, "EISA bridge", "eisa"}, 1570 { 0x0603, "MC bridge", "mca"}, 1571 { 0x0604, "PCI bridge", "pci-bridge"}, 1572 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1573 { 0x0606, "NUBUS bridge", "nubus"}, 1574 { 0x0607, "CARDBUS bridge", "cardbus"}, 1575 { 0x0608, "RACEWAY bridge"}, 1576 { 0x0680, "Bridge"}, 1577 { 0x0700, "Serial port", "serial"}, 1578 { 0x0701, "Parallel port", "parallel"}, 1579 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1580 { 0x0801, "DMA controller", "dma-controller"}, 1581 { 0x0802, "Timer", "timer"}, 1582 { 0x0803, "RTC", "rtc"}, 1583 { 0x0900, "Keyboard", "keyboard"}, 1584 { 0x0901, "Pen", "pen"}, 1585 { 0x0902, "Mouse", "mouse"}, 1586 { 0x0A00, "Dock station", "dock", 0x00ff}, 1587 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1588 { 0x0c00, "Fireware contorller", "fireware"}, 1589 { 0x0c01, "Access bus controller", "access-bus"}, 1590 { 0x0c02, "SSA controller", "ssa"}, 1591 { 0x0c03, "USB controller", "usb"}, 1592 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1593 { 0x0c05, "SMBus"}, 1594 { 0, NULL} 1595 }; 1596 1597 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1598 void (*fn)(PCIBus *b, 1599 PCIDevice *d, 1600 void *opaque), 1601 void *opaque) 1602 { 1603 PCIDevice *d; 1604 int devfn; 1605 1606 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1607 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1608 if (d) { 1609 fn(bus, d, opaque); 1610 } 1611 } 1612 } 1613 1614 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1615 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1616 void *opaque) 1617 { 1618 bus = pci_find_bus_nr(bus, bus_num); 1619 1620 if (bus) { 1621 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1622 } 1623 } 1624 1625 static void pci_for_each_device_under_bus(PCIBus *bus, 1626 void (*fn)(PCIBus *b, PCIDevice *d, 1627 void *opaque), 1628 void *opaque) 1629 { 1630 PCIDevice *d; 1631 int devfn; 1632 1633 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1634 d = bus->devices[devfn]; 1635 if (d) { 1636 fn(bus, d, opaque); 1637 } 1638 } 1639 } 1640 1641 void pci_for_each_device(PCIBus *bus, int bus_num, 1642 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1643 void *opaque) 1644 { 1645 bus = pci_find_bus_nr(bus, bus_num); 1646 1647 if (bus) { 1648 pci_for_each_device_under_bus(bus, fn, opaque); 1649 } 1650 } 1651 1652 static const pci_class_desc *get_class_desc(int class) 1653 { 1654 const pci_class_desc *desc; 1655 1656 desc = pci_class_descriptions; 1657 while (desc->desc && class != desc->class) { 1658 desc++; 1659 } 1660 1661 return desc; 1662 } 1663 1664 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1665 1666 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1667 { 1668 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1669 int i; 1670 1671 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1672 const PCIIORegion *r = &dev->io_regions[i]; 1673 PciMemoryRegionList *region; 1674 1675 if (!r->size) { 1676 continue; 1677 } 1678 1679 region = g_malloc0(sizeof(*region)); 1680 region->value = g_malloc0(sizeof(*region->value)); 1681 1682 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1683 region->value->type = g_strdup("io"); 1684 } else { 1685 region->value->type = g_strdup("memory"); 1686 region->value->has_prefetch = true; 1687 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1688 region->value->has_mem_type_64 = true; 1689 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1690 } 1691 1692 region->value->bar = i; 1693 region->value->address = r->addr; 1694 region->value->size = r->size; 1695 1696 /* XXX: waiting for the qapi to support GSList */ 1697 if (!cur_item) { 1698 head = cur_item = region; 1699 } else { 1700 cur_item->next = region; 1701 cur_item = region; 1702 } 1703 } 1704 1705 return head; 1706 } 1707 1708 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1709 int bus_num) 1710 { 1711 PciBridgeInfo *info; 1712 PciMemoryRange *range; 1713 1714 info = g_new0(PciBridgeInfo, 1); 1715 1716 info->bus = g_new0(PciBusInfo, 1); 1717 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1718 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1719 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1720 1721 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1722 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1723 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1724 1725 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1726 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1727 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1728 1729 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1730 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1731 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1732 1733 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1734 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1735 if (child_bus) { 1736 info->has_devices = true; 1737 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1738 } 1739 } 1740 1741 return info; 1742 } 1743 1744 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1745 int bus_num) 1746 { 1747 const pci_class_desc *desc; 1748 PciDeviceInfo *info; 1749 uint8_t type; 1750 int class; 1751 1752 info = g_new0(PciDeviceInfo, 1); 1753 info->bus = bus_num; 1754 info->slot = PCI_SLOT(dev->devfn); 1755 info->function = PCI_FUNC(dev->devfn); 1756 1757 info->class_info = g_new0(PciDeviceClass, 1); 1758 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1759 info->class_info->q_class = class; 1760 desc = get_class_desc(class); 1761 if (desc->desc) { 1762 info->class_info->has_desc = true; 1763 info->class_info->desc = g_strdup(desc->desc); 1764 } 1765 1766 info->id = g_new0(PciDeviceId, 1); 1767 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1768 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1769 info->regions = qmp_query_pci_regions(dev); 1770 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1771 1772 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1773 info->has_irq = true; 1774 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1775 } 1776 1777 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1778 if (type == PCI_HEADER_TYPE_BRIDGE) { 1779 info->has_pci_bridge = true; 1780 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1781 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1782 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1783 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1784 info->id->subsystem_vendor = 1785 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1786 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1787 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1788 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1789 info->id->subsystem_vendor = 1790 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1791 } 1792 1793 return info; 1794 } 1795 1796 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1797 { 1798 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1799 PCIDevice *dev; 1800 int devfn; 1801 1802 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1803 dev = bus->devices[devfn]; 1804 if (dev) { 1805 info = g_malloc0(sizeof(*info)); 1806 info->value = qmp_query_pci_device(dev, bus, bus_num); 1807 1808 /* XXX: waiting for the qapi to support GSList */ 1809 if (!cur_item) { 1810 head = cur_item = info; 1811 } else { 1812 cur_item->next = info; 1813 cur_item = info; 1814 } 1815 } 1816 } 1817 1818 return head; 1819 } 1820 1821 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1822 { 1823 PciInfo *info = NULL; 1824 1825 bus = pci_find_bus_nr(bus, bus_num); 1826 if (bus) { 1827 info = g_malloc0(sizeof(*info)); 1828 info->bus = bus_num; 1829 info->devices = qmp_query_pci_devices(bus, bus_num); 1830 } 1831 1832 return info; 1833 } 1834 1835 PciInfoList *qmp_query_pci(Error **errp) 1836 { 1837 PciInfoList *info, *head = NULL, *cur_item = NULL; 1838 PCIHostState *host_bridge; 1839 1840 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1841 info = g_malloc0(sizeof(*info)); 1842 info->value = qmp_query_pci_bus(host_bridge->bus, 1843 pci_bus_num(host_bridge->bus)); 1844 1845 /* XXX: waiting for the qapi to support GSList */ 1846 if (!cur_item) { 1847 head = cur_item = info; 1848 } else { 1849 cur_item->next = info; 1850 cur_item = info; 1851 } 1852 } 1853 1854 return head; 1855 } 1856 1857 /* Initialize a PCI NIC. */ 1858 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1859 const char *default_model, 1860 const char *default_devaddr) 1861 { 1862 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1863 GSList *list; 1864 GPtrArray *pci_nic_models; 1865 PCIBus *bus; 1866 PCIDevice *pci_dev; 1867 DeviceState *dev; 1868 int devfn; 1869 int i; 1870 int dom, busnr; 1871 unsigned slot; 1872 1873 if (nd->model && !strcmp(nd->model, "virtio")) { 1874 g_free(nd->model); 1875 nd->model = g_strdup("virtio-net-pci"); 1876 } 1877 1878 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1879 pci_nic_models = g_ptr_array_new(); 1880 while (list) { 1881 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1882 TYPE_DEVICE); 1883 GSList *next; 1884 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1885 dc->user_creatable) { 1886 const char *name = object_class_get_name(list->data); 1887 g_ptr_array_add(pci_nic_models, (gpointer)name); 1888 } 1889 next = list->next; 1890 g_slist_free_1(list); 1891 list = next; 1892 } 1893 g_ptr_array_add(pci_nic_models, NULL); 1894 1895 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1896 exit(0); 1897 } 1898 1899 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1900 default_model); 1901 if (i < 0) { 1902 exit(1); 1903 } 1904 1905 if (!rootbus) { 1906 error_report("No primary PCI bus"); 1907 exit(1); 1908 } 1909 1910 assert(!rootbus->parent_dev); 1911 1912 if (!devaddr) { 1913 devfn = -1; 1914 busnr = 0; 1915 } else { 1916 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1917 error_report("Invalid PCI device address %s for device %s", 1918 devaddr, nd->model); 1919 exit(1); 1920 } 1921 1922 if (dom != 0) { 1923 error_report("No support for non-zero PCI domains"); 1924 exit(1); 1925 } 1926 1927 devfn = PCI_DEVFN(slot, 0); 1928 } 1929 1930 bus = pci_find_bus_nr(rootbus, busnr); 1931 if (!bus) { 1932 error_report("Invalid PCI device address %s for device %s", 1933 devaddr, nd->model); 1934 exit(1); 1935 } 1936 1937 pci_dev = pci_create(bus, devfn, nd->model); 1938 dev = &pci_dev->qdev; 1939 qdev_set_nic_properties(dev, nd); 1940 qdev_init_nofail(dev); 1941 g_ptr_array_free(pci_nic_models, true); 1942 return pci_dev; 1943 } 1944 1945 PCIDevice *pci_vga_init(PCIBus *bus) 1946 { 1947 switch (vga_interface_type) { 1948 case VGA_CIRRUS: 1949 return pci_create_simple(bus, -1, "cirrus-vga"); 1950 case VGA_QXL: 1951 return pci_create_simple(bus, -1, "qxl-vga"); 1952 case VGA_STD: 1953 return pci_create_simple(bus, -1, "VGA"); 1954 case VGA_VMWARE: 1955 return pci_create_simple(bus, -1, "vmware-svga"); 1956 case VGA_VIRTIO: 1957 return pci_create_simple(bus, -1, "virtio-vga"); 1958 case VGA_NONE: 1959 default: /* Other non-PCI types. Checking for unsupported types is already 1960 done in vl.c. */ 1961 return NULL; 1962 } 1963 } 1964 1965 /* Whether a given bus number is in range of the secondary 1966 * bus of the given bridge device. */ 1967 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1968 { 1969 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1970 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1971 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1972 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1973 } 1974 1975 /* Whether a given bus number is in a range of a root bus */ 1976 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1977 { 1978 int i; 1979 1980 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1981 PCIDevice *dev = bus->devices[i]; 1982 1983 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1984 if (pci_secondary_bus_in_range(dev, bus_num)) { 1985 return true; 1986 } 1987 } 1988 } 1989 1990 return false; 1991 } 1992 1993 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1994 { 1995 PCIBus *sec; 1996 1997 if (!bus) { 1998 return NULL; 1999 } 2000 2001 if (pci_bus_num(bus) == bus_num) { 2002 return bus; 2003 } 2004 2005 /* Consider all bus numbers in range for the host pci bridge. */ 2006 if (!pci_bus_is_root(bus) && 2007 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2008 return NULL; 2009 } 2010 2011 /* try child bus */ 2012 for (; bus; bus = sec) { 2013 QLIST_FOREACH(sec, &bus->child, sibling) { 2014 if (pci_bus_num(sec) == bus_num) { 2015 return sec; 2016 } 2017 /* PXB buses assumed to be children of bus 0 */ 2018 if (pci_bus_is_root(sec)) { 2019 if (pci_root_bus_in_range(sec, bus_num)) { 2020 break; 2021 } 2022 } else { 2023 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2024 break; 2025 } 2026 } 2027 } 2028 } 2029 2030 return NULL; 2031 } 2032 2033 void pci_for_each_bus_depth_first(PCIBus *bus, 2034 void *(*begin)(PCIBus *bus, void *parent_state), 2035 void (*end)(PCIBus *bus, void *state), 2036 void *parent_state) 2037 { 2038 PCIBus *sec; 2039 void *state; 2040 2041 if (!bus) { 2042 return; 2043 } 2044 2045 if (begin) { 2046 state = begin(bus, parent_state); 2047 } else { 2048 state = parent_state; 2049 } 2050 2051 QLIST_FOREACH(sec, &bus->child, sibling) { 2052 pci_for_each_bus_depth_first(sec, begin, end, state); 2053 } 2054 2055 if (end) { 2056 end(bus, state); 2057 } 2058 } 2059 2060 2061 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2062 { 2063 bus = pci_find_bus_nr(bus, bus_num); 2064 2065 if (!bus) 2066 return NULL; 2067 2068 return bus->devices[devfn]; 2069 } 2070 2071 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2072 { 2073 PCIDevice *pci_dev = (PCIDevice *)qdev; 2074 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2075 ObjectClass *klass = OBJECT_CLASS(pc); 2076 Error *local_err = NULL; 2077 bool is_default_rom; 2078 uint16_t class_id; 2079 2080 /* initialize cap_present for pci_is_express() and pci_config_size(), 2081 * Note that hybrid PCIs are not set automatically and need to manage 2082 * QEMU_PCI_CAP_EXPRESS manually */ 2083 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2084 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2085 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2086 } 2087 2088 pci_dev = do_pci_register_device(pci_dev, 2089 object_get_typename(OBJECT(qdev)), 2090 pci_dev->devfn, errp); 2091 if (pci_dev == NULL) 2092 return; 2093 2094 if (pc->realize) { 2095 pc->realize(pci_dev, &local_err); 2096 if (local_err) { 2097 error_propagate(errp, local_err); 2098 do_pci_unregister_device(pci_dev); 2099 return; 2100 } 2101 } 2102 2103 if (pci_dev->failover_pair_id) { 2104 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2105 error_setg(errp, "failover primary device must be on " 2106 "PCIExpress bus"); 2107 error_propagate(errp, local_err); 2108 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2109 return; 2110 } 2111 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2112 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2113 error_setg(errp, "failover primary device is not an " 2114 "Ethernet device"); 2115 error_propagate(errp, local_err); 2116 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2117 return; 2118 } 2119 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2120 && (PCI_FUNC(pci_dev->devfn) == 0)) { 2121 qdev->allow_unplug_during_migration = true; 2122 } else { 2123 error_setg(errp, "failover: primary device must be in its own " 2124 "PCI slot"); 2125 error_propagate(errp, local_err); 2126 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2127 return; 2128 } 2129 qdev->allow_unplug_during_migration = true; 2130 } 2131 2132 /* rom loading */ 2133 is_default_rom = false; 2134 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2135 pci_dev->romfile = g_strdup(pc->romfile); 2136 is_default_rom = true; 2137 } 2138 2139 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2140 if (local_err) { 2141 error_propagate(errp, local_err); 2142 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2143 return; 2144 } 2145 } 2146 2147 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2148 const char *name) 2149 { 2150 DeviceState *dev; 2151 2152 dev = qdev_create(&bus->qbus, name); 2153 qdev_prop_set_int32(dev, "addr", devfn); 2154 qdev_prop_set_bit(dev, "multifunction", multifunction); 2155 return PCI_DEVICE(dev); 2156 } 2157 2158 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2159 bool multifunction, 2160 const char *name) 2161 { 2162 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2163 qdev_init_nofail(&dev->qdev); 2164 return dev; 2165 } 2166 2167 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2168 { 2169 return pci_create_multifunction(bus, devfn, false, name); 2170 } 2171 2172 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2173 { 2174 return pci_create_simple_multifunction(bus, devfn, false, name); 2175 } 2176 2177 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2178 { 2179 int offset = PCI_CONFIG_HEADER_SIZE; 2180 int i; 2181 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2182 if (pdev->used[i]) 2183 offset = i + 1; 2184 else if (i - offset + 1 == size) 2185 return offset; 2186 } 2187 return 0; 2188 } 2189 2190 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2191 uint8_t *prev_p) 2192 { 2193 uint8_t next, prev; 2194 2195 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2196 return 0; 2197 2198 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2199 prev = next + PCI_CAP_LIST_NEXT) 2200 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2201 break; 2202 2203 if (prev_p) 2204 *prev_p = prev; 2205 return next; 2206 } 2207 2208 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2209 { 2210 uint8_t next, prev, found = 0; 2211 2212 if (!(pdev->used[offset])) { 2213 return 0; 2214 } 2215 2216 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2217 2218 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2219 prev = next + PCI_CAP_LIST_NEXT) { 2220 if (next <= offset && next > found) { 2221 found = next; 2222 } 2223 } 2224 return found; 2225 } 2226 2227 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2228 This is needed for an option rom which is used for more than one device. */ 2229 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2230 { 2231 uint16_t vendor_id; 2232 uint16_t device_id; 2233 uint16_t rom_vendor_id; 2234 uint16_t rom_device_id; 2235 uint16_t rom_magic; 2236 uint16_t pcir_offset; 2237 uint8_t checksum; 2238 2239 /* Words in rom data are little endian (like in PCI configuration), 2240 so they can be read / written with pci_get_word / pci_set_word. */ 2241 2242 /* Only a valid rom will be patched. */ 2243 rom_magic = pci_get_word(ptr); 2244 if (rom_magic != 0xaa55) { 2245 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2246 return; 2247 } 2248 pcir_offset = pci_get_word(ptr + 0x18); 2249 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2250 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2251 return; 2252 } 2253 2254 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2255 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2256 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2257 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2258 2259 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2260 vendor_id, device_id, rom_vendor_id, rom_device_id); 2261 2262 checksum = ptr[6]; 2263 2264 if (vendor_id != rom_vendor_id) { 2265 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2266 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2267 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2268 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2269 ptr[6] = checksum; 2270 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2271 } 2272 2273 if (device_id != rom_device_id) { 2274 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2275 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2276 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2277 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2278 ptr[6] = checksum; 2279 pci_set_word(ptr + pcir_offset + 6, device_id); 2280 } 2281 } 2282 2283 /* Add an option rom for the device */ 2284 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2285 Error **errp) 2286 { 2287 int size; 2288 char *path; 2289 void *ptr; 2290 char name[32]; 2291 const VMStateDescription *vmsd; 2292 2293 if (!pdev->romfile) 2294 return; 2295 if (strlen(pdev->romfile) == 0) 2296 return; 2297 2298 if (!pdev->rom_bar) { 2299 /* 2300 * Load rom via fw_cfg instead of creating a rom bar, 2301 * for 0.11 compatibility. 2302 */ 2303 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2304 2305 /* 2306 * Hot-plugged devices can't use the option ROM 2307 * if the rom bar is disabled. 2308 */ 2309 if (DEVICE(pdev)->hotplugged) { 2310 error_setg(errp, "Hot-plugged device without ROM bar" 2311 " can't have an option ROM"); 2312 return; 2313 } 2314 2315 if (class == 0x0300) { 2316 rom_add_vga(pdev->romfile); 2317 } else { 2318 rom_add_option(pdev->romfile, -1); 2319 } 2320 return; 2321 } 2322 2323 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2324 if (path == NULL) { 2325 path = g_strdup(pdev->romfile); 2326 } 2327 2328 size = get_image_size(path); 2329 if (size < 0) { 2330 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2331 g_free(path); 2332 return; 2333 } else if (size == 0) { 2334 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2335 g_free(path); 2336 return; 2337 } 2338 size = pow2ceil(size); 2339 2340 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2341 2342 if (vmsd) { 2343 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2344 } else { 2345 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2346 } 2347 pdev->has_rom = true; 2348 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2349 ptr = memory_region_get_ram_ptr(&pdev->rom); 2350 if (load_image_size(path, ptr, size) < 0) { 2351 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2352 g_free(path); 2353 return; 2354 } 2355 g_free(path); 2356 2357 if (is_default_rom) { 2358 /* Only the default rom images will be patched (if needed). */ 2359 pci_patch_ids(pdev, ptr, size); 2360 } 2361 2362 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2363 } 2364 2365 static void pci_del_option_rom(PCIDevice *pdev) 2366 { 2367 if (!pdev->has_rom) 2368 return; 2369 2370 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2371 pdev->has_rom = false; 2372 } 2373 2374 /* 2375 * On success, pci_add_capability() returns a positive value 2376 * that the offset of the pci capability. 2377 * On failure, it sets an error and returns a negative error 2378 * code. 2379 */ 2380 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2381 uint8_t offset, uint8_t size, 2382 Error **errp) 2383 { 2384 uint8_t *config; 2385 int i, overlapping_cap; 2386 2387 if (!offset) { 2388 offset = pci_find_space(pdev, size); 2389 /* out of PCI config space is programming error */ 2390 assert(offset); 2391 } else { 2392 /* Verify that capabilities don't overlap. Note: device assignment 2393 * depends on this check to verify that the device is not broken. 2394 * Should never trigger for emulated devices, but it's helpful 2395 * for debugging these. */ 2396 for (i = offset; i < offset + size; i++) { 2397 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2398 if (overlapping_cap) { 2399 error_setg(errp, "%s:%02x:%02x.%x " 2400 "Attempt to add PCI capability %x at offset " 2401 "%x overlaps existing capability %x at offset %x", 2402 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2403 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2404 cap_id, offset, overlapping_cap, i); 2405 return -EINVAL; 2406 } 2407 } 2408 } 2409 2410 config = pdev->config + offset; 2411 config[PCI_CAP_LIST_ID] = cap_id; 2412 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2413 pdev->config[PCI_CAPABILITY_LIST] = offset; 2414 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2415 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2416 /* Make capability read-only by default */ 2417 memset(pdev->wmask + offset, 0, size); 2418 /* Check capability by default */ 2419 memset(pdev->cmask + offset, 0xFF, size); 2420 return offset; 2421 } 2422 2423 /* Unlink capability from the pci config space. */ 2424 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2425 { 2426 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2427 if (!offset) 2428 return; 2429 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2430 /* Make capability writable again */ 2431 memset(pdev->wmask + offset, 0xff, size); 2432 memset(pdev->w1cmask + offset, 0, size); 2433 /* Clear cmask as device-specific registers can't be checked */ 2434 memset(pdev->cmask + offset, 0, size); 2435 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2436 2437 if (!pdev->config[PCI_CAPABILITY_LIST]) 2438 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2439 } 2440 2441 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2442 { 2443 return pci_find_capability_list(pdev, cap_id, NULL); 2444 } 2445 2446 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2447 { 2448 PCIDevice *d = (PCIDevice *)dev; 2449 const pci_class_desc *desc; 2450 char ctxt[64]; 2451 PCIIORegion *r; 2452 int i, class; 2453 2454 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2455 desc = pci_class_descriptions; 2456 while (desc->desc && class != desc->class) 2457 desc++; 2458 if (desc->desc) { 2459 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2460 } else { 2461 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2462 } 2463 2464 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2465 "pci id %04x:%04x (sub %04x:%04x)\n", 2466 indent, "", ctxt, pci_dev_bus_num(d), 2467 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2468 pci_get_word(d->config + PCI_VENDOR_ID), 2469 pci_get_word(d->config + PCI_DEVICE_ID), 2470 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2471 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2472 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2473 r = &d->io_regions[i]; 2474 if (!r->size) 2475 continue; 2476 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2477 " [0x%"FMT_PCIBUS"]\n", 2478 indent, "", 2479 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2480 r->addr, r->addr + r->size - 1); 2481 } 2482 } 2483 2484 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2485 { 2486 PCIDevice *d = (PCIDevice *)dev; 2487 const char *name = NULL; 2488 const pci_class_desc *desc = pci_class_descriptions; 2489 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2490 2491 while (desc->desc && 2492 (class & ~desc->fw_ign_bits) != 2493 (desc->class & ~desc->fw_ign_bits)) { 2494 desc++; 2495 } 2496 2497 if (desc->desc) { 2498 name = desc->fw_name; 2499 } 2500 2501 if (name) { 2502 pstrcpy(buf, len, name); 2503 } else { 2504 snprintf(buf, len, "pci%04x,%04x", 2505 pci_get_word(d->config + PCI_VENDOR_ID), 2506 pci_get_word(d->config + PCI_DEVICE_ID)); 2507 } 2508 2509 return buf; 2510 } 2511 2512 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2513 { 2514 PCIDevice *d = (PCIDevice *)dev; 2515 char path[50], name[33]; 2516 int off; 2517 2518 off = snprintf(path, sizeof(path), "%s@%x", 2519 pci_dev_fw_name(dev, name, sizeof name), 2520 PCI_SLOT(d->devfn)); 2521 if (PCI_FUNC(d->devfn)) 2522 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2523 return g_strdup(path); 2524 } 2525 2526 static char *pcibus_get_dev_path(DeviceState *dev) 2527 { 2528 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2529 PCIDevice *t; 2530 int slot_depth; 2531 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2532 * 00 is added here to make this format compatible with 2533 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2534 * Slot.Function list specifies the slot and function numbers for all 2535 * devices on the path from root to the specific device. */ 2536 const char *root_bus_path; 2537 int root_bus_len; 2538 char slot[] = ":SS.F"; 2539 int slot_len = sizeof slot - 1 /* For '\0' */; 2540 int path_len; 2541 char *path, *p; 2542 int s; 2543 2544 root_bus_path = pci_root_bus_path(d); 2545 root_bus_len = strlen(root_bus_path); 2546 2547 /* Calculate # of slots on path between device and root. */; 2548 slot_depth = 0; 2549 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2550 ++slot_depth; 2551 } 2552 2553 path_len = root_bus_len + slot_len * slot_depth; 2554 2555 /* Allocate memory, fill in the terminating null byte. */ 2556 path = g_malloc(path_len + 1 /* For '\0' */); 2557 path[path_len] = '\0'; 2558 2559 memcpy(path, root_bus_path, root_bus_len); 2560 2561 /* Fill in slot numbers. We walk up from device to root, so need to print 2562 * them in the reverse order, last to first. */ 2563 p = path + path_len; 2564 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2565 p -= slot_len; 2566 s = snprintf(slot, sizeof slot, ":%02x.%x", 2567 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2568 assert(s == slot_len); 2569 memcpy(p, slot, slot_len); 2570 } 2571 2572 return path; 2573 } 2574 2575 static int pci_qdev_find_recursive(PCIBus *bus, 2576 const char *id, PCIDevice **pdev) 2577 { 2578 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2579 if (!qdev) { 2580 return -ENODEV; 2581 } 2582 2583 /* roughly check if given qdev is pci device */ 2584 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2585 *pdev = PCI_DEVICE(qdev); 2586 return 0; 2587 } 2588 return -EINVAL; 2589 } 2590 2591 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2592 { 2593 PCIHostState *host_bridge; 2594 int rc = -ENODEV; 2595 2596 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2597 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2598 if (!tmp) { 2599 rc = 0; 2600 break; 2601 } 2602 if (tmp != -ENODEV) { 2603 rc = tmp; 2604 } 2605 } 2606 2607 return rc; 2608 } 2609 2610 MemoryRegion *pci_address_space(PCIDevice *dev) 2611 { 2612 return pci_get_bus(dev)->address_space_mem; 2613 } 2614 2615 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2616 { 2617 return pci_get_bus(dev)->address_space_io; 2618 } 2619 2620 static void pci_device_class_init(ObjectClass *klass, void *data) 2621 { 2622 DeviceClass *k = DEVICE_CLASS(klass); 2623 2624 k->realize = pci_qdev_realize; 2625 k->unrealize = pci_qdev_unrealize; 2626 k->bus_type = TYPE_PCI_BUS; 2627 device_class_set_props(k, pci_props); 2628 } 2629 2630 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2631 { 2632 if (!object_class_is_abstract(klass)) { 2633 ObjectClass *conventional = 2634 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2635 ObjectClass *pcie = 2636 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2637 assert(conventional || pcie); 2638 } 2639 } 2640 2641 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2642 { 2643 PCIBus *bus = pci_get_bus(dev); 2644 PCIBus *iommu_bus = bus; 2645 uint8_t devfn = dev->devfn; 2646 2647 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2648 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2649 2650 /* 2651 * The requester ID of the provided device may be aliased, as seen from 2652 * the IOMMU, due to topology limitations. The IOMMU relies on a 2653 * requester ID to provide a unique AddressSpace for devices, but 2654 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2655 * to-PCI bridge creates and accepts transactions on behalf of down- 2656 * stream devices. When doing so, all downstream devices are masked 2657 * (aliased) behind a single requester ID. The requester ID used 2658 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2659 * bridges, with a PCIe capability indicating such, follow the 2660 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2661 * where the bridge uses the seconary bus as the bridge portion of the 2662 * requester ID and devfn of 00.0. For other bridges, typically those 2663 * found on the root complex such as the dmi-to-pci-bridge, we follow 2664 * the convention of typical bare-metal hardware, which uses the 2665 * requester ID of the bridge itself. There are device specific 2666 * exceptions to these rules, but these are the defaults that the 2667 * Linux kernel uses when determining DMA aliases itself and believed 2668 * to be true for the bare metal equivalents of the devices emulated 2669 * in QEMU. 2670 */ 2671 if (!pci_bus_is_express(iommu_bus)) { 2672 PCIDevice *parent = iommu_bus->parent_dev; 2673 2674 if (pci_is_express(parent) && 2675 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2676 devfn = PCI_DEVFN(0, 0); 2677 bus = iommu_bus; 2678 } else { 2679 devfn = parent->devfn; 2680 bus = parent_bus; 2681 } 2682 } 2683 2684 iommu_bus = parent_bus; 2685 } 2686 if (iommu_bus && iommu_bus->iommu_fn) { 2687 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2688 } 2689 return &address_space_memory; 2690 } 2691 2692 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2693 { 2694 bus->iommu_fn = fn; 2695 bus->iommu_opaque = opaque; 2696 } 2697 2698 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2699 { 2700 Range *range = opaque; 2701 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2702 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2703 int i; 2704 2705 if (!(cmd & PCI_COMMAND_MEMORY)) { 2706 return; 2707 } 2708 2709 if (pc->is_bridge) { 2710 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2711 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2712 2713 base = MAX(base, 0x1ULL << 32); 2714 2715 if (limit >= base) { 2716 Range pref_range; 2717 range_set_bounds(&pref_range, base, limit); 2718 range_extend(range, &pref_range); 2719 } 2720 } 2721 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2722 PCIIORegion *r = &dev->io_regions[i]; 2723 pcibus_t lob, upb; 2724 Range region_range; 2725 2726 if (!r->size || 2727 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2728 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2729 continue; 2730 } 2731 2732 lob = pci_bar_address(dev, i, r->type, r->size); 2733 upb = lob + r->size - 1; 2734 if (lob == PCI_BAR_UNMAPPED) { 2735 continue; 2736 } 2737 2738 lob = MAX(lob, 0x1ULL << 32); 2739 2740 if (upb >= lob) { 2741 range_set_bounds(®ion_range, lob, upb); 2742 range_extend(range, ®ion_range); 2743 } 2744 } 2745 } 2746 2747 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2748 { 2749 range_make_empty(range); 2750 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2751 } 2752 2753 static bool pcie_has_upstream_port(PCIDevice *dev) 2754 { 2755 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2756 2757 /* Device associated with an upstream port. 2758 * As there are several types of these, it's easier to check the 2759 * parent device: upstream ports are always connected to 2760 * root or downstream ports. 2761 */ 2762 return parent_dev && 2763 pci_is_express(parent_dev) && 2764 parent_dev->exp.exp_cap && 2765 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2766 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2767 } 2768 2769 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2770 { 2771 PCIBus *bus = pci_get_bus(pci_dev); 2772 2773 if(pcie_has_upstream_port(pci_dev)) { 2774 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2775 return bus->devices[0]; 2776 } else { 2777 /* Other bus types might support multiple devices at slots 0-31 */ 2778 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2779 } 2780 } 2781 2782 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2783 { 2784 MSIMessage msg; 2785 if (msix_enabled(dev)) { 2786 msg = msix_get_message(dev, vector); 2787 } else if (msi_enabled(dev)) { 2788 msg = msi_get_message(dev, vector); 2789 } else { 2790 /* Should never happen */ 2791 error_report("%s: unknown interrupt type", __func__); 2792 abort(); 2793 } 2794 return msg; 2795 } 2796 2797 static const TypeInfo pci_device_type_info = { 2798 .name = TYPE_PCI_DEVICE, 2799 .parent = TYPE_DEVICE, 2800 .instance_size = sizeof(PCIDevice), 2801 .abstract = true, 2802 .class_size = sizeof(PCIDeviceClass), 2803 .class_init = pci_device_class_init, 2804 .class_base_init = pci_device_class_base_init, 2805 }; 2806 2807 static void pci_register_types(void) 2808 { 2809 type_register_static(&pci_bus_info); 2810 type_register_static(&pcie_bus_info); 2811 type_register_static(&conventional_pci_interface_info); 2812 type_register_static(&pcie_interface_info); 2813 type_register_static(&pci_device_type_info); 2814 } 2815 2816 type_init(pci_register_types) 2817