xref: /qemu/hw/ppc/mac_newworld.c (revision 01b2ffce)
1 /*
2  * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3  *
4  * Copyright (c) 2004-2007 Fabrice Bellard
5  * Copyright (c) 2007 Jocelyn Mayer
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  *
25  * PCI bus layout on a real G5 (U3 based):
26  *
27  * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28  * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29  * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30  * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31  * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32  * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33  * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34  * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35  * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36  * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37  * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38  * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39  * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40  * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41  * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42  * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43  * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44  * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45  * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46  * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47  *
48  */
49 #include "qemu/osdep.h"
50 #include "qapi/error.h"
51 #include "hw/hw.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/ppc/mac.h"
54 #include "hw/input/adb.h"
55 #include "hw/ppc/mac_dbdma.h"
56 #include "hw/timer/m48t59.h"
57 #include "hw/pci/pci.h"
58 #include "net/net.h"
59 #include "sysemu/sysemu.h"
60 #include "hw/boards.h"
61 #include "hw/nvram/fw_cfg.h"
62 #include "hw/char/escc.h"
63 #include "hw/ppc/openpic.h"
64 #include "hw/ide.h"
65 #include "hw/loader.h"
66 #include "elf.h"
67 #include "qemu/error-report.h"
68 #include "sysemu/kvm.h"
69 #include "kvm_ppc.h"
70 #include "hw/usb.h"
71 #include "sysemu/block-backend.h"
72 #include "exec/address-spaces.h"
73 #include "hw/sysbus.h"
74 #include "qemu/cutils.h"
75 #include "trace.h"
76 
77 #define MAX_IDE_BUS 2
78 #define CFG_ADDR 0xf0000510
79 #define TBFREQ (100UL * 1000UL * 1000UL)
80 #define CLOCKFREQ (266UL * 1000UL * 1000UL)
81 #define BUSFREQ (100UL * 1000UL * 1000UL)
82 
83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
84 
85 /* UniN device */
86 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
87                        unsigned size)
88 {
89     trace_mac99_uninorth_write(addr, value);
90     if (addr == 0x0) {
91         *(int*)opaque = value;
92     }
93 }
94 
95 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
96 {
97     uint32_t value;
98 
99     value = 0;
100     switch (addr) {
101     case 0:
102         value = *(int*)opaque;
103     }
104 
105     trace_mac99_uninorth_read(addr, value);
106 
107     return value;
108 }
109 
110 static const MemoryRegionOps unin_ops = {
111     .read = unin_read,
112     .write = unin_write,
113     .endianness = DEVICE_NATIVE_ENDIAN,
114 };
115 
116 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
117                             Error **errp)
118 {
119     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
120 }
121 
122 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
123 {
124     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
125 }
126 
127 static hwaddr round_page(hwaddr addr)
128 {
129     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
130 }
131 
132 static void ppc_core99_reset(void *opaque)
133 {
134     PowerPCCPU *cpu = opaque;
135 
136     cpu_reset(CPU(cpu));
137     /* 970 CPUs want to get their initial IP as part of their boot protocol */
138     cpu->env.nip = PROM_ADDR + 0x100;
139 }
140 
141 /* PowerPC Mac99 hardware initialisation */
142 static void ppc_core99_init(MachineState *machine)
143 {
144     ram_addr_t ram_size = machine->ram_size;
145     const char *kernel_filename = machine->kernel_filename;
146     const char *kernel_cmdline = machine->kernel_cmdline;
147     const char *initrd_filename = machine->initrd_filename;
148     const char *boot_device = machine->boot_order;
149     PowerPCCPU *cpu = NULL;
150     CPUPPCState *env = NULL;
151     char *filename;
152     qemu_irq *pic, **openpic_irqs;
153     MemoryRegion *isa = g_new(MemoryRegion, 1);
154     MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
155     MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
156     int linux_boot, i, j, k;
157     MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
158     hwaddr kernel_base, initrd_base, cmdline_base = 0;
159     long kernel_size, initrd_size;
160     PCIBus *pci_bus;
161     PCIDevice *macio;
162     MACIOIDEState *macio_ide;
163     BusState *adb_bus;
164     MacIONVRAMState *nvr;
165     int bios_size, ndrv_size;
166     uint8_t *ndrv_file;
167     MemoryRegion *pic_mem, *escc_mem;
168     MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
169     int ppc_boot_device;
170     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
171     void *fw_cfg;
172     int machine_arch;
173     SysBusDevice *s;
174     DeviceState *dev;
175     int *token = g_new(int, 1);
176     hwaddr nvram_addr = 0xFFF04000;
177     uint64_t tbfreq;
178 
179     linux_boot = (kernel_filename != NULL);
180 
181     /* init CPUs */
182     if (machine->cpu_model == NULL) {
183 #ifdef TARGET_PPC64
184         machine->cpu_model = "970fx";
185 #else
186         machine->cpu_model = "G4";
187 #endif
188     }
189     for (i = 0; i < smp_cpus; i++) {
190         cpu = cpu_ppc_init(machine->cpu_model);
191         if (cpu == NULL) {
192             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
193             exit(1);
194         }
195         env = &cpu->env;
196 
197         /* Set time-base frequency to 100 Mhz */
198         cpu_ppc_tb_init(env, TBFREQ);
199         qemu_register_reset(ppc_core99_reset, cpu);
200     }
201 
202     /* allocate RAM */
203     memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
204     memory_region_add_subregion(get_system_memory(), 0, ram);
205 
206     /* allocate and load BIOS */
207     memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
208                            &error_fatal);
209     vmstate_register_ram_global(bios);
210 
211     if (bios_name == NULL)
212         bios_name = PROM_FILENAME;
213     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
214     memory_region_set_readonly(bios, true);
215     memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
216 
217     /* Load OpenBIOS (ELF) */
218     if (filename) {
219         bios_size = load_elf(filename, NULL, NULL, NULL,
220                              NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
221 
222         g_free(filename);
223     } else {
224         bios_size = -1;
225     }
226     if (bios_size < 0 || bios_size > BIOS_SIZE) {
227         error_report("could not load PowerPC bios '%s'", bios_name);
228         exit(1);
229     }
230 
231     if (linux_boot) {
232         uint64_t lowaddr = 0;
233         int bswap_needed;
234 
235 #ifdef BSWAP_NEEDED
236         bswap_needed = 1;
237 #else
238         bswap_needed = 0;
239 #endif
240         kernel_base = KERNEL_LOAD_ADDR;
241 
242         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
243                                NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
244                                0, 0);
245         if (kernel_size < 0)
246             kernel_size = load_aout(kernel_filename, kernel_base,
247                                     ram_size - kernel_base, bswap_needed,
248                                     TARGET_PAGE_SIZE);
249         if (kernel_size < 0)
250             kernel_size = load_image_targphys(kernel_filename,
251                                               kernel_base,
252                                               ram_size - kernel_base);
253         if (kernel_size < 0) {
254             error_report("could not load kernel '%s'", kernel_filename);
255             exit(1);
256         }
257         /* load initrd */
258         if (initrd_filename) {
259             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
260             initrd_size = load_image_targphys(initrd_filename, initrd_base,
261                                               ram_size - initrd_base);
262             if (initrd_size < 0) {
263                 error_report("could not load initial ram disk '%s'",
264                              initrd_filename);
265                 exit(1);
266             }
267             cmdline_base = round_page(initrd_base + initrd_size);
268         } else {
269             initrd_base = 0;
270             initrd_size = 0;
271             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
272         }
273         ppc_boot_device = 'm';
274     } else {
275         kernel_base = 0;
276         kernel_size = 0;
277         initrd_base = 0;
278         initrd_size = 0;
279         ppc_boot_device = '\0';
280         /* We consider that NewWorld PowerMac never have any floppy drive
281          * For now, OHW cannot boot from the network.
282          */
283         for (i = 0; boot_device[i] != '\0'; i++) {
284             if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
285                 ppc_boot_device = boot_device[i];
286                 break;
287             }
288         }
289         if (ppc_boot_device == '\0') {
290             fprintf(stderr, "No valid boot device for Mac99 machine\n");
291             exit(1);
292         }
293     }
294 
295     /* Register 8 MB of ISA IO space */
296     memory_region_init_alias(isa, NULL, "isa_mmio",
297                              get_system_io(), 0, 0x00800000);
298     memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
299 
300     /* UniN init: XXX should be a real device */
301     memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
302     memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
303 
304     memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
305     memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
306 
307     openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
308     openpic_irqs[0] =
309         g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
310     for (i = 0; i < smp_cpus; i++) {
311         /* Mac99 IRQ connection between OpenPIC outputs pins
312          * and PowerPC input pins
313          */
314         switch (PPC_INPUT(env)) {
315         case PPC_FLAGS_INPUT_6xx:
316             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
317             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
318                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
319             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
320                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
321             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
322                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
323             /* Not connected ? */
324             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
325             /* Check this */
326             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
327                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
328             break;
329 #if defined(TARGET_PPC64)
330         case PPC_FLAGS_INPUT_970:
331             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
332             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
333                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
334             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
335                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
336             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
337                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
338             /* Not connected ? */
339             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
340             /* Check this */
341             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
342                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
343             break;
344 #endif /* defined(TARGET_PPC64) */
345         default:
346             error_report("Bus model not supported on mac99 machine");
347             exit(1);
348         }
349     }
350 
351     pic = g_new0(qemu_irq, 64);
352 
353     dev = qdev_create(NULL, TYPE_OPENPIC);
354     qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
355     qdev_init_nofail(dev);
356     s = SYS_BUS_DEVICE(dev);
357     pic_mem = s->mmio[0].memory;
358     k = 0;
359     for (i = 0; i < smp_cpus; i++) {
360         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
361             sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
362         }
363     }
364 
365     for (i = 0; i < 64; i++) {
366         pic[i] = qdev_get_gpio_in(dev, i);
367     }
368 
369     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
370         /* 970 gets a U3 bus */
371         pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
372         machine_arch = ARCH_MAC99_U3;
373     } else {
374         pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
375         machine_arch = ARCH_MAC99;
376     }
377     object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort);
378 
379     machine->usb |= defaults_enabled() && !machine->usb_disabled;
380 
381     /* Timebase Frequency */
382     if (kvm_enabled()) {
383         tbfreq = kvmppc_get_tbfreq();
384     } else {
385         tbfreq = TBFREQ;
386     }
387 
388     /* init basic PC hardware */
389     escc_mem = escc_init(0, pic[0x25], pic[0x24],
390                          serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
391     memory_region_init_alias(escc_bar, NULL, "escc-bar",
392                              escc_mem, 0, memory_region_size(escc_mem));
393 
394     macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
395     dev = DEVICE(macio);
396     qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
397     qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
398     qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
399     qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
400     qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
401     qdev_prop_set_uint64(dev, "frequency", tbfreq);
402     macio_init(macio, pic_mem, escc_bar);
403 
404     /* We only emulate 2 out of 3 IDE controllers for now */
405     ide_drive_get(hd, ARRAY_SIZE(hd));
406 
407     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
408                                                         "ide[0]"));
409     macio_ide_init_drives(macio_ide, hd);
410 
411     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
412                                                         "ide[1]"));
413     macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
414 
415     dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
416     adb_bus = qdev_get_child_bus(dev, "adb.0");
417     dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
418     qdev_init_nofail(dev);
419     dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
420     qdev_init_nofail(dev);
421 
422     if (machine->usb) {
423         pci_create_simple(pci_bus, -1, "pci-ohci");
424 
425         /* U3 needs to use USB for input because Linux doesn't support via-cuda
426         on PPC64 */
427         if (machine_arch == ARCH_MAC99_U3) {
428             USBBus *usb_bus = usb_bus_find(-1);
429 
430             usb_create_simple(usb_bus, "usb-kbd");
431             usb_create_simple(usb_bus, "usb-mouse");
432         }
433     }
434 
435     pci_vga_init(pci_bus);
436 
437     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
438         graphic_depth = 15;
439     }
440 
441     for (i = 0; i < nb_nics; i++) {
442         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
443     }
444 
445     /* The NewWorld NVRAM is not located in the MacIO device */
446 #ifdef CONFIG_KVM
447     if (kvm_enabled() && getpagesize() > 4096) {
448         /* We can't combine read-write and read-only in a single page, so
449            move the NVRAM out of ROM again for KVM */
450         nvram_addr = 0xFFE00000;
451     }
452 #endif
453     dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
454     qdev_prop_set_uint32(dev, "size", 0x2000);
455     qdev_prop_set_uint32(dev, "it_shift", 1);
456     qdev_init_nofail(dev);
457     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
458     nvr = MACIO_NVRAM(dev);
459     pmac_format_nvram_partition(nvr, 0x2000);
460     /* No PCI init: the BIOS will do it */
461 
462     fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
463     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
464     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
465     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
466     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
467     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
468     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
469     if (kernel_cmdline) {
470         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
471         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
472     } else {
473         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
474     }
475     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
476     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
477     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
478 
479     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
480     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
481     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
482 
483     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
484     if (kvm_enabled()) {
485 #ifdef CONFIG_KVM
486         uint8_t *hypercall;
487 
488         hypercall = g_malloc(16);
489         kvmppc_get_hypercall(env, hypercall, 16);
490         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
491         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
492 #endif
493     }
494     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
495     /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
496     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
497     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
498     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
499 
500     /* MacOS NDRV VGA driver */
501     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
502     if (filename) {
503         ndrv_size = get_image_size(filename);
504         if (ndrv_size != -1) {
505             ndrv_file = g_malloc(ndrv_size);
506             ndrv_size = load_image(filename, ndrv_file);
507 
508             fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
509         }
510         g_free(filename);
511     }
512 
513     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
514 }
515 
516 static int core99_kvm_type(const char *arg)
517 {
518     /* Always force PR KVM */
519     return 2;
520 }
521 
522 static void core99_machine_class_init(ObjectClass *oc, void *data)
523 {
524     MachineClass *mc = MACHINE_CLASS(oc);
525 
526     mc->desc = "Mac99 based PowerMAC";
527     mc->init = ppc_core99_init;
528     mc->block_default_type = IF_IDE;
529     mc->max_cpus = MAX_CPUS;
530     mc->default_boot_order = "cd";
531     mc->kvm_type = core99_kvm_type;
532 }
533 
534 static const TypeInfo core99_machine_info = {
535     .name          = MACHINE_TYPE_NAME("mac99"),
536     .parent        = TYPE_MACHINE,
537     .class_init    = core99_machine_class_init,
538 };
539 
540 static void mac_machine_register_types(void)
541 {
542     type_register_static(&core99_machine_info);
543 }
544 
545 type_init(mac_machine_register_types)
546