1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/ppc/openpic.h" 64 #include "hw/ide.h" 65 #include "hw/loader.h" 66 #include "elf.h" 67 #include "qemu/error-report.h" 68 #include "sysemu/kvm.h" 69 #include "kvm_ppc.h" 70 #include "hw/usb.h" 71 #include "sysemu/block-backend.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 #include "qemu/cutils.h" 75 #include "trace.h" 76 77 #define MAX_IDE_BUS 2 78 #define CFG_ADDR 0xf0000510 79 #define TBFREQ (100UL * 1000UL * 1000UL) 80 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 81 #define BUSFREQ (100UL * 1000UL * 1000UL) 82 83 /* UniN device */ 84 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 85 unsigned size) 86 { 87 trace_mac99_uninorth_write(addr, value); 88 if (addr == 0x0) { 89 *(int*)opaque = value; 90 } 91 } 92 93 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 94 { 95 uint32_t value; 96 97 value = 0; 98 switch (addr) { 99 case 0: 100 value = *(int*)opaque; 101 } 102 103 trace_mac99_uninorth_read(addr, value); 104 105 return value; 106 } 107 108 static const MemoryRegionOps unin_ops = { 109 .read = unin_read, 110 .write = unin_write, 111 .endianness = DEVICE_NATIVE_ENDIAN, 112 }; 113 114 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 115 Error **errp) 116 { 117 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 118 } 119 120 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 121 { 122 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 123 } 124 125 static hwaddr round_page(hwaddr addr) 126 { 127 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 128 } 129 130 static void ppc_core99_reset(void *opaque) 131 { 132 PowerPCCPU *cpu = opaque; 133 134 cpu_reset(CPU(cpu)); 135 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 136 cpu->env.nip = PROM_ADDR + 0x100; 137 } 138 139 /* PowerPC Mac99 hardware initialisation */ 140 static void ppc_core99_init(MachineState *machine) 141 { 142 ram_addr_t ram_size = machine->ram_size; 143 const char *kernel_filename = machine->kernel_filename; 144 const char *kernel_cmdline = machine->kernel_cmdline; 145 const char *initrd_filename = machine->initrd_filename; 146 const char *boot_device = machine->boot_order; 147 PowerPCCPU *cpu = NULL; 148 CPUPPCState *env = NULL; 149 char *filename; 150 qemu_irq *pic, **openpic_irqs; 151 MemoryRegion *isa = g_new(MemoryRegion, 1); 152 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 153 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 154 int linux_boot, i, j, k; 155 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 156 hwaddr kernel_base, initrd_base, cmdline_base = 0; 157 long kernel_size, initrd_size; 158 PCIBus *pci_bus; 159 PCIDevice *macio; 160 MACIOIDEState *macio_ide; 161 BusState *adb_bus; 162 MacIONVRAMState *nvr; 163 int bios_size; 164 MemoryRegion *pic_mem, *escc_mem; 165 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 166 int ppc_boot_device; 167 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 168 void *fw_cfg; 169 int machine_arch; 170 SysBusDevice *s; 171 DeviceState *dev; 172 int *token = g_new(int, 1); 173 hwaddr nvram_addr = 0xFFF04000; 174 uint64_t tbfreq; 175 176 linux_boot = (kernel_filename != NULL); 177 178 /* init CPUs */ 179 if (machine->cpu_model == NULL) { 180 #ifdef TARGET_PPC64 181 machine->cpu_model = "970fx"; 182 #else 183 machine->cpu_model = "G4"; 184 #endif 185 } 186 for (i = 0; i < smp_cpus; i++) { 187 cpu = cpu_ppc_init(machine->cpu_model); 188 if (cpu == NULL) { 189 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 190 exit(1); 191 } 192 env = &cpu->env; 193 194 /* Set time-base frequency to 100 Mhz */ 195 cpu_ppc_tb_init(env, TBFREQ); 196 qemu_register_reset(ppc_core99_reset, cpu); 197 } 198 199 /* allocate RAM */ 200 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 201 memory_region_add_subregion(get_system_memory(), 0, ram); 202 203 /* allocate and load BIOS */ 204 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 205 &error_fatal); 206 vmstate_register_ram_global(bios); 207 208 if (bios_name == NULL) 209 bios_name = PROM_FILENAME; 210 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 211 memory_region_set_readonly(bios, true); 212 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 213 214 /* Load OpenBIOS (ELF) */ 215 if (filename) { 216 bios_size = load_elf(filename, NULL, NULL, NULL, 217 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 218 219 g_free(filename); 220 } else { 221 bios_size = -1; 222 } 223 if (bios_size < 0 || bios_size > BIOS_SIZE) { 224 error_report("could not load PowerPC bios '%s'", bios_name); 225 exit(1); 226 } 227 228 if (linux_boot) { 229 uint64_t lowaddr = 0; 230 int bswap_needed; 231 232 #ifdef BSWAP_NEEDED 233 bswap_needed = 1; 234 #else 235 bswap_needed = 0; 236 #endif 237 kernel_base = KERNEL_LOAD_ADDR; 238 239 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 240 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 241 0, 0); 242 if (kernel_size < 0) 243 kernel_size = load_aout(kernel_filename, kernel_base, 244 ram_size - kernel_base, bswap_needed, 245 TARGET_PAGE_SIZE); 246 if (kernel_size < 0) 247 kernel_size = load_image_targphys(kernel_filename, 248 kernel_base, 249 ram_size - kernel_base); 250 if (kernel_size < 0) { 251 error_report("could not load kernel '%s'", kernel_filename); 252 exit(1); 253 } 254 /* load initrd */ 255 if (initrd_filename) { 256 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 257 initrd_size = load_image_targphys(initrd_filename, initrd_base, 258 ram_size - initrd_base); 259 if (initrd_size < 0) { 260 error_report("could not load initial ram disk '%s'", 261 initrd_filename); 262 exit(1); 263 } 264 cmdline_base = round_page(initrd_base + initrd_size); 265 } else { 266 initrd_base = 0; 267 initrd_size = 0; 268 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 269 } 270 ppc_boot_device = 'm'; 271 } else { 272 kernel_base = 0; 273 kernel_size = 0; 274 initrd_base = 0; 275 initrd_size = 0; 276 ppc_boot_device = '\0'; 277 /* We consider that NewWorld PowerMac never have any floppy drive 278 * For now, OHW cannot boot from the network. 279 */ 280 for (i = 0; boot_device[i] != '\0'; i++) { 281 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 282 ppc_boot_device = boot_device[i]; 283 break; 284 } 285 } 286 if (ppc_boot_device == '\0') { 287 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 288 exit(1); 289 } 290 } 291 292 /* Register 8 MB of ISA IO space */ 293 memory_region_init_alias(isa, NULL, "isa_mmio", 294 get_system_io(), 0, 0x00800000); 295 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 296 297 /* UniN init: XXX should be a real device */ 298 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 299 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 300 301 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 302 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 303 304 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 305 openpic_irqs[0] = 306 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 307 for (i = 0; i < smp_cpus; i++) { 308 /* Mac99 IRQ connection between OpenPIC outputs pins 309 * and PowerPC input pins 310 */ 311 switch (PPC_INPUT(env)) { 312 case PPC_FLAGS_INPUT_6xx: 313 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 314 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 315 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 316 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 317 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 318 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 319 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 320 /* Not connected ? */ 321 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 322 /* Check this */ 323 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 324 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 325 break; 326 #if defined(TARGET_PPC64) 327 case PPC_FLAGS_INPUT_970: 328 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 329 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 330 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 331 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 332 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 333 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 334 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 335 /* Not connected ? */ 336 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 337 /* Check this */ 338 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 339 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 340 break; 341 #endif /* defined(TARGET_PPC64) */ 342 default: 343 error_report("Bus model not supported on mac99 machine"); 344 exit(1); 345 } 346 } 347 348 pic = g_new0(qemu_irq, 64); 349 350 dev = qdev_create(NULL, TYPE_OPENPIC); 351 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 352 qdev_init_nofail(dev); 353 s = SYS_BUS_DEVICE(dev); 354 pic_mem = s->mmio[0].memory; 355 k = 0; 356 for (i = 0; i < smp_cpus; i++) { 357 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 358 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 359 } 360 } 361 362 for (i = 0; i < 64; i++) { 363 pic[i] = qdev_get_gpio_in(dev, i); 364 } 365 366 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 367 /* 970 gets a U3 bus */ 368 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 369 machine_arch = ARCH_MAC99_U3; 370 } else { 371 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 372 machine_arch = ARCH_MAC99; 373 } 374 object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort); 375 376 machine->usb |= defaults_enabled() && !machine->usb_disabled; 377 378 /* Timebase Frequency */ 379 if (kvm_enabled()) { 380 tbfreq = kvmppc_get_tbfreq(); 381 } else { 382 tbfreq = TBFREQ; 383 } 384 385 /* init basic PC hardware */ 386 escc_mem = escc_init(0, pic[0x25], pic[0x24], 387 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 388 memory_region_init_alias(escc_bar, NULL, "escc-bar", 389 escc_mem, 0, memory_region_size(escc_mem)); 390 391 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 392 dev = DEVICE(macio); 393 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 394 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 395 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 396 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 397 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 398 qdev_prop_set_uint64(dev, "frequency", tbfreq); 399 macio_init(macio, pic_mem, escc_bar); 400 401 /* We only emulate 2 out of 3 IDE controllers for now */ 402 ide_drive_get(hd, ARRAY_SIZE(hd)); 403 404 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 405 "ide[0]")); 406 macio_ide_init_drives(macio_ide, hd); 407 408 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 409 "ide[1]")); 410 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 411 412 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 413 adb_bus = qdev_get_child_bus(dev, "adb.0"); 414 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 415 qdev_init_nofail(dev); 416 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 417 qdev_init_nofail(dev); 418 419 if (machine->usb) { 420 pci_create_simple(pci_bus, -1, "pci-ohci"); 421 422 /* U3 needs to use USB for input because Linux doesn't support via-cuda 423 on PPC64 */ 424 if (machine_arch == ARCH_MAC99_U3) { 425 USBBus *usb_bus = usb_bus_find(-1); 426 427 usb_create_simple(usb_bus, "usb-kbd"); 428 usb_create_simple(usb_bus, "usb-mouse"); 429 } 430 } 431 432 pci_vga_init(pci_bus); 433 434 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 435 graphic_depth = 15; 436 } 437 438 for (i = 0; i < nb_nics; i++) { 439 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 440 } 441 442 /* The NewWorld NVRAM is not located in the MacIO device */ 443 #ifdef CONFIG_KVM 444 if (kvm_enabled() && getpagesize() > 4096) { 445 /* We can't combine read-write and read-only in a single page, so 446 move the NVRAM out of ROM again for KVM */ 447 nvram_addr = 0xFFE00000; 448 } 449 #endif 450 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 451 qdev_prop_set_uint32(dev, "size", 0x2000); 452 qdev_prop_set_uint32(dev, "it_shift", 1); 453 qdev_init_nofail(dev); 454 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 455 nvr = MACIO_NVRAM(dev); 456 pmac_format_nvram_partition(nvr, 0x2000); 457 /* No PCI init: the BIOS will do it */ 458 459 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 460 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 461 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 462 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 463 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 464 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 465 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 466 if (kernel_cmdline) { 467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 468 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 469 } else { 470 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 471 } 472 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 473 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 474 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 475 476 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 477 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 478 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 479 480 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 481 if (kvm_enabled()) { 482 #ifdef CONFIG_KVM 483 uint8_t *hypercall; 484 485 hypercall = g_malloc(16); 486 kvmppc_get_hypercall(env, hypercall, 16); 487 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 488 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 489 #endif 490 } 491 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 492 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 493 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 495 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 496 497 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 498 } 499 500 static int core99_kvm_type(const char *arg) 501 { 502 /* Always force PR KVM */ 503 return 2; 504 } 505 506 static void core99_machine_class_init(ObjectClass *oc, void *data) 507 { 508 MachineClass *mc = MACHINE_CLASS(oc); 509 510 mc->desc = "Mac99 based PowerMAC"; 511 mc->init = ppc_core99_init; 512 mc->block_default_type = IF_IDE; 513 mc->max_cpus = MAX_CPUS; 514 mc->default_boot_order = "cd"; 515 mc->kvm_type = core99_kvm_type; 516 } 517 518 static const TypeInfo core99_machine_info = { 519 .name = MACHINE_TYPE_NAME("mac99"), 520 .parent = TYPE_MACHINE, 521 .class_init = core99_machine_class_init, 522 }; 523 524 static void mac_machine_register_types(void) 525 { 526 type_register_static(&core99_machine_info); 527 } 528 529 type_init(mac_machine_register_types) 530