1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu/datadir.h" 51 #include "qapi/error.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/qdev-properties.h" 54 #include "hw/ppc/mac.h" 55 #include "hw/input/adb.h" 56 #include "hw/ppc/mac_dbdma.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/nvram/fw_cfg.h" 61 #include "hw/char/escc.h" 62 #include "hw/misc/macio/macio.h" 63 #include "hw/ppc/openpic.h" 64 #include "hw/loader.h" 65 #include "hw/fw-path-provider.h" 66 #include "elf.h" 67 #include "qemu/error-report.h" 68 #include "sysemu/kvm.h" 69 #include "sysemu/reset.h" 70 #include "kvm_ppc.h" 71 #include "hw/usb.h" 72 #include "hw/sysbus.h" 73 #include "trace.h" 74 75 #define MAX_IDE_BUS 2 76 #define CFG_ADDR 0xf0000510 77 #define TBFREQ (100UL * 1000UL * 1000UL) 78 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 79 #define BUSFREQ (100UL * 1000UL * 1000UL) 80 81 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 82 83 #define PROM_BASE 0xfff00000 84 #define PROM_SIZE (1 * MiB) 85 86 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 87 Error **errp) 88 { 89 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 90 } 91 92 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 93 { 94 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 95 } 96 97 static void ppc_core99_reset(void *opaque) 98 { 99 PowerPCCPU *cpu = opaque; 100 101 cpu_reset(CPU(cpu)); 102 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 103 cpu->env.nip = PROM_BASE + 0x100; 104 } 105 106 /* PowerPC Mac99 hardware initialisation */ 107 static void ppc_core99_init(MachineState *machine) 108 { 109 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 110 PowerPCCPU *cpu = NULL; 111 CPUPPCState *env = NULL; 112 char *filename; 113 IrqLines *openpic_irqs; 114 int i, j, k, ppc_boot_device, machine_arch, bios_size; 115 const char *bios_name = machine->firmware ?: PROM_FILENAME; 116 MemoryRegion *bios = g_new(MemoryRegion, 1); 117 hwaddr kernel_base, initrd_base, cmdline_base = 0; 118 long kernel_size, initrd_size; 119 UNINHostState *uninorth_pci; 120 PCIBus *pci_bus; 121 PCIDevice *macio; 122 ESCCState *escc; 123 bool has_pmu, has_adb; 124 MACIOIDEState *macio_ide; 125 BusState *adb_bus; 126 MacIONVRAMState *nvr; 127 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 128 void *fw_cfg; 129 SysBusDevice *s; 130 DeviceState *dev, *pic_dev; 131 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; 132 hwaddr nvram_addr = 0xFFF04000; 133 uint64_t tbfreq; 134 135 /* init CPUs */ 136 for (i = 0; i < machine->smp.cpus; i++) { 137 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 138 env = &cpu->env; 139 140 /* Set time-base frequency to 100 Mhz */ 141 cpu_ppc_tb_init(env, TBFREQ); 142 qemu_register_reset(ppc_core99_reset, cpu); 143 } 144 145 /* allocate RAM */ 146 if (machine->ram_size > 2 * GiB) { 147 error_report("RAM size more than 2 GiB is not supported"); 148 exit(1); 149 } 150 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 151 152 /* allocate and load firmware ROM */ 153 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 154 &error_fatal); 155 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 156 157 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 158 if (filename) { 159 /* Load OpenBIOS (ELF) */ 160 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 161 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 162 163 if (bios_size <= 0) { 164 /* or load binary ROM image */ 165 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 166 } 167 g_free(filename); 168 } else { 169 bios_size = -1; 170 } 171 if (bios_size < 0 || bios_size > PROM_SIZE) { 172 error_report("could not load PowerPC bios '%s'", bios_name); 173 exit(1); 174 } 175 176 if (machine->kernel_filename) { 177 int bswap_needed; 178 179 #ifdef BSWAP_NEEDED 180 bswap_needed = 1; 181 #else 182 bswap_needed = 0; 183 #endif 184 kernel_base = KERNEL_LOAD_ADDR; 185 186 kernel_size = load_elf(machine->kernel_filename, NULL, 187 translate_kernel_address, NULL, NULL, NULL, 188 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 189 if (kernel_size < 0) 190 kernel_size = load_aout(machine->kernel_filename, kernel_base, 191 machine->ram_size - kernel_base, 192 bswap_needed, TARGET_PAGE_SIZE); 193 if (kernel_size < 0) 194 kernel_size = load_image_targphys(machine->kernel_filename, 195 kernel_base, 196 machine->ram_size - kernel_base); 197 if (kernel_size < 0) { 198 error_report("could not load kernel '%s'", 199 machine->kernel_filename); 200 exit(1); 201 } 202 /* load initrd */ 203 if (machine->initrd_filename) { 204 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 205 initrd_size = load_image_targphys(machine->initrd_filename, 206 initrd_base, 207 machine->ram_size - initrd_base); 208 if (initrd_size < 0) { 209 error_report("could not load initial ram disk '%s'", 210 machine->initrd_filename); 211 exit(1); 212 } 213 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 214 } else { 215 initrd_base = 0; 216 initrd_size = 0; 217 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 218 } 219 ppc_boot_device = 'm'; 220 } else { 221 kernel_base = 0; 222 kernel_size = 0; 223 initrd_base = 0; 224 initrd_size = 0; 225 ppc_boot_device = '\0'; 226 /* We consider that NewWorld PowerMac never have any floppy drive 227 * For now, OHW cannot boot from the network. 228 */ 229 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 230 if (machine->boot_config.order[i] >= 'c' && 231 machine->boot_config.order[i] <= 'f') { 232 ppc_boot_device = machine->boot_config.order[i]; 233 break; 234 } 235 } 236 if (ppc_boot_device == '\0') { 237 error_report("No valid boot device for Mac99 machine"); 238 exit(1); 239 } 240 } 241 242 /* UniN init */ 243 dev = qdev_new(TYPE_UNI_NORTH); 244 s = SYS_BUS_DEVICE(dev); 245 sysbus_realize_and_unref(s, &error_fatal); 246 memory_region_add_subregion(get_system_memory(), 0xf8000000, 247 sysbus_mmio_get_region(s, 0)); 248 249 openpic_irqs = g_new0(IrqLines, machine->smp.cpus); 250 for (i = 0; i < machine->smp.cpus; i++) { 251 /* Mac99 IRQ connection between OpenPIC outputs pins 252 * and PowerPC input pins 253 */ 254 switch (PPC_INPUT(env)) { 255 case PPC_FLAGS_INPUT_6xx: 256 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 257 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT); 258 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 259 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT); 260 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 261 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_MCP); 262 /* Not connected ? */ 263 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 264 /* Check this */ 265 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 266 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET); 267 break; 268 #if defined(TARGET_PPC64) 269 case PPC_FLAGS_INPUT_970: 270 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 271 qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT); 272 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 273 qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT); 274 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 275 qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_MCP); 276 /* Not connected ? */ 277 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 278 /* Check this */ 279 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 280 qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_HRESET); 281 break; 282 #endif /* defined(TARGET_PPC64) */ 283 default: 284 error_report("Bus model not supported on mac99 machine"); 285 exit(1); 286 } 287 } 288 289 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 290 /* 970 gets a U3 bus */ 291 /* Uninorth AGP bus */ 292 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 293 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 294 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 295 s = SYS_BUS_DEVICE(dev); 296 /* PCI hole */ 297 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 298 sysbus_mmio_get_region(s, 2)); 299 /* Register 8 MB of ISA IO space */ 300 memory_region_add_subregion(get_system_memory(), 0xf2000000, 301 sysbus_mmio_get_region(s, 3)); 302 sysbus_mmio_map(s, 0, 0xf0800000); 303 sysbus_mmio_map(s, 1, 0xf0c00000); 304 305 machine_arch = ARCH_MAC99_U3; 306 } else { 307 /* Use values found on a real PowerMac */ 308 /* Uninorth AGP bus */ 309 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 310 s = SYS_BUS_DEVICE(uninorth_agp_dev); 311 sysbus_realize_and_unref(s, &error_fatal); 312 sysbus_mmio_map(s, 0, 0xf0800000); 313 sysbus_mmio_map(s, 1, 0xf0c00000); 314 315 /* Uninorth internal bus */ 316 uninorth_internal_dev = qdev_new( 317 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 318 s = SYS_BUS_DEVICE(uninorth_internal_dev); 319 sysbus_realize_and_unref(s, &error_fatal); 320 sysbus_mmio_map(s, 0, 0xf4800000); 321 sysbus_mmio_map(s, 1, 0xf4c00000); 322 323 /* Uninorth main bus */ 324 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 325 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 326 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 327 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 328 s = SYS_BUS_DEVICE(dev); 329 /* PCI hole */ 330 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 331 sysbus_mmio_get_region(s, 2)); 332 /* Register 8 MB of ISA IO space */ 333 memory_region_add_subregion(get_system_memory(), 0xf2000000, 334 sysbus_mmio_get_region(s, 3)); 335 sysbus_mmio_map(s, 0, 0xf2800000); 336 sysbus_mmio_map(s, 1, 0xf2c00000); 337 338 machine_arch = ARCH_MAC99; 339 } 340 341 machine->usb |= defaults_enabled() && !machine->usb_disabled; 342 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 343 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 344 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 345 346 /* Timebase Frequency */ 347 if (kvm_enabled()) { 348 tbfreq = kvmppc_get_tbfreq(); 349 } else { 350 tbfreq = TBFREQ; 351 } 352 353 /* init basic PC hardware */ 354 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 355 356 /* MacIO */ 357 macio = pci_new(-1, TYPE_NEWWORLD_MACIO); 358 dev = DEVICE(macio); 359 qdev_prop_set_uint64(dev, "frequency", tbfreq); 360 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 361 qdev_prop_set_bit(dev, "has-adb", has_adb); 362 363 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 364 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 365 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 366 367 pci_realize_and_unref(macio, pci_bus, &error_fatal); 368 369 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic")); 370 for (i = 0; i < 4; i++) { 371 qdev_connect_gpio_out(DEVICE(uninorth_pci), i, 372 qdev_get_gpio_in(pic_dev, 0x1b + i)); 373 } 374 375 /* TODO: additional PCI buses only wired up for 32-bit machines */ 376 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { 377 /* Uninorth AGP bus */ 378 for (i = 0; i < 4; i++) { 379 qdev_connect_gpio_out(uninorth_agp_dev, i, 380 qdev_get_gpio_in(pic_dev, 0x1b + i)); 381 } 382 383 /* Uninorth internal bus */ 384 for (i = 0; i < 4; i++) { 385 qdev_connect_gpio_out(uninorth_internal_dev, i, 386 qdev_get_gpio_in(pic_dev, 0x1b + i)); 387 } 388 } 389 390 /* OpenPIC */ 391 s = SYS_BUS_DEVICE(pic_dev); 392 k = 0; 393 for (i = 0; i < machine->smp.cpus; i++) { 394 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 395 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 396 } 397 } 398 g_free(openpic_irqs); 399 400 /* We only emulate 2 out of 3 IDE controllers for now */ 401 ide_drive_get(hd, ARRAY_SIZE(hd)); 402 403 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 404 "ide[0]")); 405 macio_ide_init_drives(macio_ide, hd); 406 407 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 408 "ide[1]")); 409 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 410 411 if (has_adb) { 412 if (has_pmu) { 413 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu")); 414 } else { 415 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 416 } 417 418 adb_bus = qdev_get_child_bus(dev, "adb.0"); 419 dev = qdev_new(TYPE_ADB_KEYBOARD); 420 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 421 422 dev = qdev_new(TYPE_ADB_MOUSE); 423 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 424 } 425 426 if (machine->usb) { 427 pci_create_simple(pci_bus, -1, "pci-ohci"); 428 429 /* U3 needs to use USB for input because Linux doesn't support via-cuda 430 on PPC64 */ 431 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 432 USBBus *usb_bus = usb_bus_find(-1); 433 434 usb_create_simple(usb_bus, "usb-kbd"); 435 usb_create_simple(usb_bus, "usb-mouse"); 436 } 437 } 438 439 pci_vga_init(pci_bus); 440 441 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 442 graphic_depth = 15; 443 } 444 445 for (i = 0; i < nb_nics; i++) { 446 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL); 447 } 448 449 /* The NewWorld NVRAM is not located in the MacIO device */ 450 if (kvm_enabled() && qemu_real_host_page_size() > 4096) { 451 /* We can't combine read-write and read-only in a single page, so 452 move the NVRAM out of ROM again for KVM */ 453 nvram_addr = 0xFFE00000; 454 } 455 dev = qdev_new(TYPE_MACIO_NVRAM); 456 qdev_prop_set_uint32(dev, "size", 0x2000); 457 qdev_prop_set_uint32(dev, "it_shift", 1); 458 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 459 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 460 nvr = MACIO_NVRAM(dev); 461 pmac_format_nvram_partition(nvr, 0x2000); 462 /* No PCI init: the BIOS will do it */ 463 464 dev = qdev_new(TYPE_FW_CFG_MEM); 465 fw_cfg = FW_CFG(dev); 466 qdev_prop_set_uint32(dev, "data_width", 1); 467 qdev_prop_set_bit(dev, "dma_enabled", false); 468 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 469 OBJECT(fw_cfg)); 470 s = SYS_BUS_DEVICE(dev); 471 sysbus_realize_and_unref(s, &error_fatal); 472 sysbus_mmio_map(s, 0, CFG_ADDR); 473 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 474 475 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 476 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 477 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 478 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 479 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 480 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 481 if (machine->kernel_cmdline) { 482 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 483 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 484 machine->kernel_cmdline); 485 } else { 486 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 487 } 488 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 489 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 490 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 491 492 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 493 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 494 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 495 496 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 497 498 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 499 if (kvm_enabled()) { 500 uint8_t *hypercall; 501 502 hypercall = g_malloc(16); 503 kvmppc_get_hypercall(env, hypercall, 16); 504 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 505 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 506 } 507 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 508 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 509 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 510 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 511 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 512 513 /* MacOS NDRV VGA driver */ 514 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 515 if (filename) { 516 gchar *ndrv_file; 517 gsize ndrv_size; 518 519 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 520 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 521 } 522 g_free(filename); 523 } 524 525 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 526 } 527 528 /* 529 * Implementation of an interface to adjust firmware path 530 * for the bootindex property handling. 531 */ 532 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 533 DeviceState *dev) 534 { 535 PCIDevice *pci; 536 MACIOIDEState *macio_ide; 537 538 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 539 pci = PCI_DEVICE(dev); 540 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 541 } 542 543 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 544 macio_ide = MACIO_IDE(dev); 545 return g_strdup_printf("ata-3@%x", macio_ide->addr); 546 } 547 548 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 549 return g_strdup("disk"); 550 } 551 552 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 553 return g_strdup("cdrom"); 554 } 555 556 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 557 return g_strdup("disk"); 558 } 559 560 return NULL; 561 } 562 static int core99_kvm_type(MachineState *machine, const char *arg) 563 { 564 /* Always force PR KVM */ 565 return 2; 566 } 567 568 static void core99_machine_class_init(ObjectClass *oc, void *data) 569 { 570 MachineClass *mc = MACHINE_CLASS(oc); 571 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 572 573 mc->desc = "Mac99 based PowerMAC"; 574 mc->init = ppc_core99_init; 575 mc->block_default_type = IF_IDE; 576 /* SMP is not supported currently */ 577 mc->max_cpus = 1; 578 mc->default_boot_order = "cd"; 579 mc->default_display = "std"; 580 mc->kvm_type = core99_kvm_type; 581 #ifdef TARGET_PPC64 582 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 583 #else 584 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 585 #endif 586 mc->default_ram_id = "ppc_core99.ram"; 587 mc->ignore_boot_device_suffixes = true; 588 fwc->get_dev_path = core99_fw_dev_path; 589 } 590 591 static char *core99_get_via_config(Object *obj, Error **errp) 592 { 593 Core99MachineState *cms = CORE99_MACHINE(obj); 594 595 switch (cms->via_config) { 596 default: 597 case CORE99_VIA_CONFIG_CUDA: 598 return g_strdup("cuda"); 599 600 case CORE99_VIA_CONFIG_PMU: 601 return g_strdup("pmu"); 602 603 case CORE99_VIA_CONFIG_PMU_ADB: 604 return g_strdup("pmu-adb"); 605 } 606 } 607 608 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 609 { 610 Core99MachineState *cms = CORE99_MACHINE(obj); 611 612 if (!strcmp(value, "cuda")) { 613 cms->via_config = CORE99_VIA_CONFIG_CUDA; 614 } else if (!strcmp(value, "pmu")) { 615 cms->via_config = CORE99_VIA_CONFIG_PMU; 616 } else if (!strcmp(value, "pmu-adb")) { 617 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 618 } else { 619 error_setg(errp, "Invalid via value"); 620 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 621 } 622 } 623 624 static void core99_instance_init(Object *obj) 625 { 626 Core99MachineState *cms = CORE99_MACHINE(obj); 627 628 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 629 cms->via_config = CORE99_VIA_CONFIG_CUDA; 630 object_property_add_str(obj, "via", core99_get_via_config, 631 core99_set_via_config); 632 object_property_set_description(obj, "via", 633 "Set VIA configuration. " 634 "Valid values are cuda, pmu and pmu-adb"); 635 636 return; 637 } 638 639 static const TypeInfo core99_machine_info = { 640 .name = MACHINE_TYPE_NAME("mac99"), 641 .parent = TYPE_MACHINE, 642 .class_init = core99_machine_class_init, 643 .instance_init = core99_instance_init, 644 .instance_size = sizeof(Core99MachineState), 645 .interfaces = (InterfaceInfo[]) { 646 { TYPE_FW_PATH_PROVIDER }, 647 { } 648 }, 649 }; 650 651 static void mac_machine_register_types(void) 652 { 653 type_register_static(&core99_machine_info); 654 } 655 656 type_init(mac_machine_register_types) 657