1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/ppc/ppc.h" 29 #include "mac.h" 30 #include "hw/input/adb.h" 31 #include "hw/timer/m48t59.h" 32 #include "sysemu/sysemu.h" 33 #include "net/net.h" 34 #include "hw/isa/isa.h" 35 #include "hw/pci/pci.h" 36 #include "hw/boards.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/ide.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "qemu/error-report.h" 43 #include "sysemu/kvm.h" 44 #include "kvm_ppc.h" 45 #include "sysemu/block-backend.h" 46 #include "exec/address-spaces.h" 47 48 #define MAX_IDE_BUS 2 49 #define CFG_ADDR 0xf0000510 50 #define TBFREQ 16600000UL 51 #define CLOCKFREQ 266000000UL 52 #define BUSFREQ 66000000UL 53 54 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 55 Error **errp) 56 { 57 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 58 } 59 60 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 61 { 62 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 63 } 64 65 static hwaddr round_page(hwaddr addr) 66 { 67 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 68 } 69 70 static void ppc_heathrow_reset(void *opaque) 71 { 72 PowerPCCPU *cpu = opaque; 73 74 cpu_reset(CPU(cpu)); 75 } 76 77 static void ppc_heathrow_init(MachineState *machine) 78 { 79 ram_addr_t ram_size = machine->ram_size; 80 const char *kernel_filename = machine->kernel_filename; 81 const char *kernel_cmdline = machine->kernel_cmdline; 82 const char *initrd_filename = machine->initrd_filename; 83 const char *boot_device = machine->boot_order; 84 MemoryRegion *sysmem = get_system_memory(); 85 PowerPCCPU *cpu = NULL; 86 CPUPPCState *env = NULL; 87 char *filename; 88 qemu_irq *pic, **heathrow_irqs; 89 int linux_boot, i; 90 MemoryRegion *ram = g_new(MemoryRegion, 1); 91 MemoryRegion *bios = g_new(MemoryRegion, 1); 92 MemoryRegion *isa = g_new(MemoryRegion, 1); 93 uint32_t kernel_base, initrd_base, cmdline_base = 0; 94 int32_t kernel_size, initrd_size; 95 PCIBus *pci_bus; 96 PCIDevice *macio; 97 MACIOIDEState *macio_ide; 98 DeviceState *dev; 99 BusState *adb_bus; 100 int bios_size; 101 MemoryRegion *pic_mem; 102 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 103 uint16_t ppc_boot_device; 104 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 105 void *fw_cfg; 106 uint64_t tbfreq; 107 108 linux_boot = (kernel_filename != NULL); 109 110 /* init CPUs */ 111 if (machine->cpu_model == NULL) 112 machine->cpu_model = "G3"; 113 for (i = 0; i < smp_cpus; i++) { 114 cpu = cpu_ppc_init(machine->cpu_model); 115 if (cpu == NULL) { 116 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 117 exit(1); 118 } 119 env = &cpu->env; 120 121 /* Set time-base frequency to 16.6 Mhz */ 122 cpu_ppc_tb_init(env, TBFREQ); 123 qemu_register_reset(ppc_heathrow_reset, cpu); 124 } 125 126 /* allocate RAM */ 127 if (ram_size > (2047 << 20)) { 128 fprintf(stderr, 129 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 130 ((unsigned int)ram_size / (1 << 20))); 131 exit(1); 132 } 133 134 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 135 ram_size); 136 memory_region_add_subregion(sysmem, 0, ram); 137 138 /* allocate and load BIOS */ 139 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 140 &error_fatal); 141 vmstate_register_ram_global(bios); 142 143 if (bios_name == NULL) 144 bios_name = PROM_FILENAME; 145 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 146 memory_region_set_readonly(bios, true); 147 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 148 149 /* Load OpenBIOS (ELF) */ 150 if (filename) { 151 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 152 1, PPC_ELF_MACHINE, 0, 0); 153 g_free(filename); 154 } else { 155 bios_size = -1; 156 } 157 if (bios_size < 0 || bios_size > BIOS_SIZE) { 158 error_report("could not load PowerPC bios '%s'", bios_name); 159 exit(1); 160 } 161 162 if (linux_boot) { 163 uint64_t lowaddr = 0; 164 int bswap_needed; 165 166 #ifdef BSWAP_NEEDED 167 bswap_needed = 1; 168 #else 169 bswap_needed = 0; 170 #endif 171 kernel_base = KERNEL_LOAD_ADDR; 172 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 173 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 174 0, 0); 175 if (kernel_size < 0) 176 kernel_size = load_aout(kernel_filename, kernel_base, 177 ram_size - kernel_base, bswap_needed, 178 TARGET_PAGE_SIZE); 179 if (kernel_size < 0) 180 kernel_size = load_image_targphys(kernel_filename, 181 kernel_base, 182 ram_size - kernel_base); 183 if (kernel_size < 0) { 184 error_report("could not load kernel '%s'", kernel_filename); 185 exit(1); 186 } 187 /* load initrd */ 188 if (initrd_filename) { 189 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 190 initrd_size = load_image_targphys(initrd_filename, initrd_base, 191 ram_size - initrd_base); 192 if (initrd_size < 0) { 193 error_report("could not load initial ram disk '%s'", 194 initrd_filename); 195 exit(1); 196 } 197 cmdline_base = round_page(initrd_base + initrd_size); 198 } else { 199 initrd_base = 0; 200 initrd_size = 0; 201 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 202 } 203 ppc_boot_device = 'm'; 204 } else { 205 kernel_base = 0; 206 kernel_size = 0; 207 initrd_base = 0; 208 initrd_size = 0; 209 ppc_boot_device = '\0'; 210 for (i = 0; boot_device[i] != '\0'; i++) { 211 /* TOFIX: for now, the second IDE channel is not properly 212 * used by OHW. The Mac floppy disk are not emulated. 213 * For now, OHW cannot boot from the network. 214 */ 215 #if 0 216 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 217 ppc_boot_device = boot_device[i]; 218 break; 219 } 220 #else 221 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 222 ppc_boot_device = boot_device[i]; 223 break; 224 } 225 #endif 226 } 227 if (ppc_boot_device == '\0') { 228 fprintf(stderr, "No valid boot device for G3 Beige machine\n"); 229 exit(1); 230 } 231 } 232 233 /* Register 2 MB of ISA IO space */ 234 memory_region_init_alias(isa, NULL, "isa_mmio", 235 get_system_io(), 0, 0x00200000); 236 memory_region_add_subregion(sysmem, 0xfe000000, isa); 237 238 /* XXX: we register only 1 output pin for heathrow PIC */ 239 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 240 heathrow_irqs[0] = 241 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 242 /* Connect the heathrow PIC outputs to the 6xx bus */ 243 for (i = 0; i < smp_cpus; i++) { 244 switch (PPC_INPUT(env)) { 245 case PPC_FLAGS_INPUT_6xx: 246 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 247 heathrow_irqs[i][0] = 248 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 249 break; 250 default: 251 error_report("Bus model not supported on OldWorld Mac machine"); 252 exit(1); 253 } 254 } 255 256 /* Timebase Frequency */ 257 if (kvm_enabled()) { 258 tbfreq = kvmppc_get_tbfreq(); 259 } else { 260 tbfreq = TBFREQ; 261 } 262 263 /* init basic PC hardware */ 264 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 265 error_report("Only 6xx bus is supported on heathrow machine"); 266 exit(1); 267 } 268 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 269 pci_bus = pci_grackle_init(0xfec00000, pic, 270 get_system_memory(), 271 get_system_io()); 272 pci_vga_init(pci_bus); 273 274 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], 275 serial_hds[1], ESCC_CLOCK, 4); 276 memory_region_init_alias(escc_bar, NULL, "escc-bar", 277 escc_mem, 0, memory_region_size(escc_mem)); 278 279 for(i = 0; i < nb_nics; i++) 280 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 281 282 283 ide_drive_get(hd, ARRAY_SIZE(hd)); 284 285 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 286 dev = DEVICE(macio); 287 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 288 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 289 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 290 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 291 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 292 qdev_prop_set_uint64(dev, "frequency", tbfreq); 293 macio_init(macio, pic_mem, escc_bar); 294 295 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 296 "ide[0]")); 297 macio_ide_init_drives(macio_ide, hd); 298 299 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 300 "ide[1]")); 301 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 302 303 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 304 adb_bus = qdev_get_child_bus(dev, "adb.0"); 305 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 306 qdev_init_nofail(dev); 307 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 308 qdev_init_nofail(dev); 309 310 if (usb_enabled()) { 311 pci_create_simple(pci_bus, -1, "pci-ohci"); 312 } 313 314 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 315 graphic_depth = 15; 316 317 /* No PCI init: the BIOS will do it */ 318 319 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 320 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 321 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 322 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 323 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 324 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 325 if (kernel_cmdline) { 326 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 327 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 328 } else { 329 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 330 } 331 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 332 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 333 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 334 335 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 336 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 337 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 338 339 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 340 if (kvm_enabled()) { 341 #ifdef CONFIG_KVM 342 uint8_t *hypercall; 343 344 hypercall = g_malloc(16); 345 kvmppc_get_hypercall(env, hypercall, 16); 346 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 347 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 348 #endif 349 } 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 351 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 353 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 354 355 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 356 } 357 358 static int heathrow_kvm_type(const char *arg) 359 { 360 /* Always force PR KVM */ 361 return 2; 362 } 363 364 static void heathrow_machine_init(MachineClass *mc) 365 { 366 mc->desc = "Heathrow based PowerMAC"; 367 mc->init = ppc_heathrow_init; 368 mc->max_cpus = MAX_CPUS; 369 #ifndef TARGET_PPC64 370 mc->is_default = 1; 371 #endif 372 /* TOFIX "cad" when Mac floppy is implemented */ 373 mc->default_boot_order = "cd"; 374 mc->kvm_type = heathrow_kvm_type; 375 } 376 377 DEFINE_MACHINE("g3beige", heathrow_machine_init) 378