1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/ide.h" 45 #include "hw/loader.h" 46 #include "hw/fw-path-provider.h" 47 #include "elf.h" 48 #include "qemu/error-report.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/reset.h" 51 #include "kvm_ppc.h" 52 #include "exec/address-spaces.h" 53 54 #define MAX_IDE_BUS 2 55 #define CFG_ADDR 0xf0000510 56 #define TBFREQ 16600000UL 57 #define CLOCKFREQ 266000000UL 58 #define BUSFREQ 66000000UL 59 60 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 61 62 #define GRACKLE_BASE 0xfec00000 63 64 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 65 Error **errp) 66 { 67 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 68 } 69 70 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 71 { 72 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 73 } 74 75 static void ppc_heathrow_reset(void *opaque) 76 { 77 PowerPCCPU *cpu = opaque; 78 79 cpu_reset(CPU(cpu)); 80 } 81 82 static void ppc_heathrow_init(MachineState *machine) 83 { 84 ram_addr_t ram_size = machine->ram_size; 85 const char *kernel_filename = machine->kernel_filename; 86 const char *kernel_cmdline = machine->kernel_cmdline; 87 const char *initrd_filename = machine->initrd_filename; 88 const char *boot_device = machine->boot_order; 89 MemoryRegion *sysmem = get_system_memory(); 90 PowerPCCPU *cpu = NULL; 91 CPUPPCState *env = NULL; 92 char *filename; 93 int linux_boot, i; 94 MemoryRegion *bios = g_new(MemoryRegion, 1); 95 uint32_t kernel_base, initrd_base, cmdline_base = 0; 96 int32_t kernel_size, initrd_size; 97 PCIBus *pci_bus; 98 OldWorldMacIOState *macio; 99 MACIOIDEState *macio_ide; 100 SysBusDevice *s; 101 DeviceState *dev, *pic_dev; 102 BusState *adb_bus; 103 int bios_size; 104 unsigned int smp_cpus = machine->smp.cpus; 105 uint16_t ppc_boot_device; 106 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq; 109 110 linux_boot = (kernel_filename != NULL); 111 112 /* init CPUs */ 113 for (i = 0; i < smp_cpus; i++) { 114 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 115 env = &cpu->env; 116 117 /* Set time-base frequency to 16.6 Mhz */ 118 cpu_ppc_tb_init(env, TBFREQ); 119 qemu_register_reset(ppc_heathrow_reset, cpu); 120 } 121 122 /* allocate RAM */ 123 if (ram_size > 2047 * MiB) { 124 error_report("Too much memory for this machine: %" PRId64 " MB, " 125 "maximum 2047 MB", ram_size / MiB); 126 exit(1); 127 } 128 129 memory_region_add_subregion(sysmem, 0, machine->ram); 130 131 /* allocate and load BIOS */ 132 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 133 &error_fatal); 134 135 if (bios_name == NULL) 136 bios_name = PROM_FILENAME; 137 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 138 memory_region_set_readonly(bios, true); 139 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 140 141 /* Load OpenBIOS (ELF) */ 142 if (filename) { 143 bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL, 144 1, PPC_ELF_MACHINE, 0, 0); 145 g_free(filename); 146 } else { 147 bios_size = -1; 148 } 149 if (bios_size < 0 || bios_size > BIOS_SIZE) { 150 error_report("could not load PowerPC bios '%s'", bios_name); 151 exit(1); 152 } 153 154 if (linux_boot) { 155 uint64_t lowaddr = 0; 156 int bswap_needed; 157 158 #ifdef BSWAP_NEEDED 159 bswap_needed = 1; 160 #else 161 bswap_needed = 0; 162 #endif 163 kernel_base = KERNEL_LOAD_ADDR; 164 kernel_size = load_elf(kernel_filename, NULL, 165 translate_kernel_address, NULL, 166 NULL, &lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE, 167 0, 0); 168 if (kernel_size < 0) 169 kernel_size = load_aout(kernel_filename, kernel_base, 170 ram_size - kernel_base, bswap_needed, 171 TARGET_PAGE_SIZE); 172 if (kernel_size < 0) 173 kernel_size = load_image_targphys(kernel_filename, 174 kernel_base, 175 ram_size - kernel_base); 176 if (kernel_size < 0) { 177 error_report("could not load kernel '%s'", kernel_filename); 178 exit(1); 179 } 180 /* load initrd */ 181 if (initrd_filename) { 182 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 183 initrd_size = load_image_targphys(initrd_filename, initrd_base, 184 ram_size - initrd_base); 185 if (initrd_size < 0) { 186 error_report("could not load initial ram disk '%s'", 187 initrd_filename); 188 exit(1); 189 } 190 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 191 } else { 192 initrd_base = 0; 193 initrd_size = 0; 194 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 195 } 196 ppc_boot_device = 'm'; 197 } else { 198 kernel_base = 0; 199 kernel_size = 0; 200 initrd_base = 0; 201 initrd_size = 0; 202 ppc_boot_device = '\0'; 203 for (i = 0; boot_device[i] != '\0'; i++) { 204 /* TOFIX: for now, the second IDE channel is not properly 205 * used by OHW. The Mac floppy disk are not emulated. 206 * For now, OHW cannot boot from the network. 207 */ 208 #if 0 209 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 210 ppc_boot_device = boot_device[i]; 211 break; 212 } 213 #else 214 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 215 ppc_boot_device = boot_device[i]; 216 break; 217 } 218 #endif 219 } 220 if (ppc_boot_device == '\0') { 221 error_report("No valid boot device for G3 Beige machine"); 222 exit(1); 223 } 224 } 225 226 /* XXX: we register only 1 output pin for heathrow PIC */ 227 pic_dev = qdev_create(NULL, TYPE_HEATHROW); 228 qdev_init_nofail(pic_dev); 229 230 /* Connect the heathrow PIC outputs to the 6xx bus */ 231 for (i = 0; i < smp_cpus; i++) { 232 switch (PPC_INPUT(env)) { 233 case PPC_FLAGS_INPUT_6xx: 234 qdev_connect_gpio_out(pic_dev, 0, 235 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 236 break; 237 default: 238 error_report("Bus model not supported on OldWorld Mac machine"); 239 exit(1); 240 } 241 } 242 243 /* Timebase Frequency */ 244 if (kvm_enabled()) { 245 tbfreq = kvmppc_get_tbfreq(); 246 } else { 247 tbfreq = TBFREQ; 248 } 249 250 /* init basic PC hardware */ 251 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 252 error_report("Only 6xx bus is supported on heathrow machine"); 253 exit(1); 254 } 255 256 /* Grackle PCI host bridge */ 257 dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE); 258 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 259 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 260 &error_abort); 261 qdev_init_nofail(dev); 262 s = SYS_BUS_DEVICE(dev); 263 sysbus_mmio_map(s, 0, GRACKLE_BASE); 264 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 265 /* PCI hole */ 266 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 267 sysbus_mmio_get_region(s, 2)); 268 /* Register 2 MB of ISA IO space */ 269 memory_region_add_subregion(get_system_memory(), 0xfe000000, 270 sysbus_mmio_get_region(s, 3)); 271 272 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 273 274 pci_vga_init(pci_bus); 275 276 for (i = 0; i < nb_nics; i++) { 277 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 278 } 279 280 ide_drive_get(hd, ARRAY_SIZE(hd)); 281 282 /* MacIO */ 283 macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); 284 dev = DEVICE(macio); 285 qdev_prop_set_uint64(dev, "frequency", tbfreq); 286 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 287 &error_abort); 288 qdev_init_nofail(dev); 289 290 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 291 "ide[0]")); 292 macio_ide_init_drives(macio_ide, hd); 293 294 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 295 "ide[1]")); 296 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 297 298 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 299 adb_bus = qdev_get_child_bus(dev, "adb.0"); 300 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 301 qdev_init_nofail(dev); 302 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 303 qdev_init_nofail(dev); 304 305 if (machine_usb(machine)) { 306 pci_create_simple(pci_bus, -1, "pci-ohci"); 307 } 308 309 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 310 graphic_depth = 15; 311 312 /* No PCI init: the BIOS will do it */ 313 314 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 315 fw_cfg = FW_CFG(dev); 316 qdev_prop_set_uint32(dev, "data_width", 1); 317 qdev_prop_set_bit(dev, "dma_enabled", false); 318 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 319 OBJECT(fw_cfg), NULL); 320 qdev_init_nofail(dev); 321 s = SYS_BUS_DEVICE(dev); 322 sysbus_mmio_map(s, 0, CFG_ADDR); 323 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 324 325 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 326 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 327 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 328 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 329 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 331 if (kernel_cmdline) { 332 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 333 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 334 } else { 335 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 336 } 337 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 338 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 339 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 340 341 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 342 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 343 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 344 345 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 346 if (kvm_enabled()) { 347 uint8_t *hypercall; 348 349 hypercall = g_malloc(16); 350 kvmppc_get_hypercall(env, hypercall, 16); 351 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 353 } 354 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 355 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 356 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 357 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 358 359 /* MacOS NDRV VGA driver */ 360 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 361 if (filename) { 362 gchar *ndrv_file; 363 gsize ndrv_size; 364 365 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 366 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 367 } 368 g_free(filename); 369 } 370 371 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 372 } 373 374 /* 375 * Implementation of an interface to adjust firmware path 376 * for the bootindex property handling. 377 */ 378 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 379 DeviceState *dev) 380 { 381 PCIDevice *pci; 382 IDEBus *ide_bus; 383 IDEState *ide_s; 384 MACIOIDEState *macio_ide; 385 386 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 387 pci = PCI_DEVICE(dev); 388 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 389 } 390 391 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 392 macio_ide = MACIO_IDE(dev); 393 return g_strdup_printf("ata-3@%x", macio_ide->addr); 394 } 395 396 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 397 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 398 ide_s = idebus_active_if(ide_bus); 399 400 if (ide_s->drive_kind == IDE_CD) { 401 return g_strdup("cdrom"); 402 } 403 404 return g_strdup("disk"); 405 } 406 407 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 408 return g_strdup("disk"); 409 } 410 411 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 412 return g_strdup("cdrom"); 413 } 414 415 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 416 return g_strdup("disk"); 417 } 418 419 return NULL; 420 } 421 422 static int heathrow_kvm_type(MachineState *machine, const char *arg) 423 { 424 /* Always force PR KVM */ 425 return 2; 426 } 427 428 static void heathrow_class_init(ObjectClass *oc, void *data) 429 { 430 MachineClass *mc = MACHINE_CLASS(oc); 431 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 432 433 mc->desc = "Heathrow based PowerMAC"; 434 mc->init = ppc_heathrow_init; 435 mc->block_default_type = IF_IDE; 436 mc->max_cpus = MAX_CPUS; 437 #ifndef TARGET_PPC64 438 mc->is_default = true; 439 #endif 440 /* TOFIX "cad" when Mac floppy is implemented */ 441 mc->default_boot_order = "cd"; 442 mc->kvm_type = heathrow_kvm_type; 443 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 444 mc->default_display = "std"; 445 mc->ignore_boot_device_suffixes = true; 446 mc->default_ram_id = "ppc_heathrow.ram"; 447 fwc->get_dev_path = heathrow_fw_dev_path; 448 } 449 450 static const TypeInfo ppc_heathrow_machine_info = { 451 .name = MACHINE_TYPE_NAME("g3beige"), 452 .parent = TYPE_MACHINE, 453 .class_init = heathrow_class_init, 454 .interfaces = (InterfaceInfo[]) { 455 { TYPE_FW_PATH_PROVIDER }, 456 { } 457 }, 458 }; 459 460 static void ppc_heathrow_register_types(void) 461 { 462 type_register_static(&ppc_heathrow_machine_info); 463 } 464 465 type_init(ppc_heathrow_register_types); 466