1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "mac.h" 31 #include "hw/input/adb.h" 32 #include "hw/timer/m48t59.h" 33 #include "sysemu/sysemu.h" 34 #include "net/net.h" 35 #include "hw/isa/isa.h" 36 #include "hw/pci/pci.h" 37 #include "hw/boards.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/char/escc.h" 40 #include "hw/ide.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "qemu/error-report.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_ppc.h" 46 #include "sysemu/block-backend.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/cutils.h" 49 50 #define MAX_IDE_BUS 2 51 #define CFG_ADDR 0xf0000510 52 #define TBFREQ 16600000UL 53 #define CLOCKFREQ 266000000UL 54 #define BUSFREQ 66000000UL 55 56 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 57 58 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 59 Error **errp) 60 { 61 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 62 } 63 64 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 65 { 66 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 67 } 68 69 static void ppc_heathrow_reset(void *opaque) 70 { 71 PowerPCCPU *cpu = opaque; 72 73 cpu_reset(CPU(cpu)); 74 } 75 76 static void ppc_heathrow_init(MachineState *machine) 77 { 78 ram_addr_t ram_size = machine->ram_size; 79 const char *kernel_filename = machine->kernel_filename; 80 const char *kernel_cmdline = machine->kernel_cmdline; 81 const char *initrd_filename = machine->initrd_filename; 82 const char *boot_device = machine->boot_order; 83 MemoryRegion *sysmem = get_system_memory(); 84 PowerPCCPU *cpu = NULL; 85 CPUPPCState *env = NULL; 86 char *filename; 87 qemu_irq *pic, **heathrow_irqs; 88 int linux_boot, i; 89 MemoryRegion *ram = g_new(MemoryRegion, 1); 90 MemoryRegion *bios = g_new(MemoryRegion, 1); 91 MemoryRegion *isa = g_new(MemoryRegion, 1); 92 uint32_t kernel_base, initrd_base, cmdline_base = 0; 93 int32_t kernel_size, initrd_size; 94 PCIBus *pci_bus; 95 PCIDevice *macio; 96 MACIOIDEState *macio_ide; 97 DeviceState *dev; 98 BusState *adb_bus; 99 int bios_size, ndrv_size; 100 uint8_t *ndrv_file; 101 MemoryRegion *pic_mem; 102 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 103 uint16_t ppc_boot_device; 104 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 105 void *fw_cfg; 106 uint64_t tbfreq; 107 SysBusDevice *s; 108 109 linux_boot = (kernel_filename != NULL); 110 111 /* init CPUs */ 112 for (i = 0; i < smp_cpus; i++) { 113 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &cpu->env; 115 116 /* Set time-base frequency to 16.6 Mhz */ 117 cpu_ppc_tb_init(env, TBFREQ); 118 qemu_register_reset(ppc_heathrow_reset, cpu); 119 } 120 121 /* allocate RAM */ 122 if (ram_size > (2047 << 20)) { 123 fprintf(stderr, 124 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 125 ((unsigned int)ram_size / (1 << 20))); 126 exit(1); 127 } 128 129 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 130 ram_size); 131 memory_region_add_subregion(sysmem, 0, ram); 132 133 /* allocate and load BIOS */ 134 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 135 &error_fatal); 136 137 if (bios_name == NULL) 138 bios_name = PROM_FILENAME; 139 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 140 memory_region_set_readonly(bios, true); 141 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 142 143 /* Load OpenBIOS (ELF) */ 144 if (filename) { 145 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 146 1, PPC_ELF_MACHINE, 0, 0); 147 g_free(filename); 148 } else { 149 bios_size = -1; 150 } 151 if (bios_size < 0 || bios_size > BIOS_SIZE) { 152 error_report("could not load PowerPC bios '%s'", bios_name); 153 exit(1); 154 } 155 156 if (linux_boot) { 157 uint64_t lowaddr = 0; 158 int bswap_needed; 159 160 #ifdef BSWAP_NEEDED 161 bswap_needed = 1; 162 #else 163 bswap_needed = 0; 164 #endif 165 kernel_base = KERNEL_LOAD_ADDR; 166 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 167 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 168 0, 0); 169 if (kernel_size < 0) 170 kernel_size = load_aout(kernel_filename, kernel_base, 171 ram_size - kernel_base, bswap_needed, 172 TARGET_PAGE_SIZE); 173 if (kernel_size < 0) 174 kernel_size = load_image_targphys(kernel_filename, 175 kernel_base, 176 ram_size - kernel_base); 177 if (kernel_size < 0) { 178 error_report("could not load kernel '%s'", kernel_filename); 179 exit(1); 180 } 181 /* load initrd */ 182 if (initrd_filename) { 183 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 184 initrd_size = load_image_targphys(initrd_filename, initrd_base, 185 ram_size - initrd_base); 186 if (initrd_size < 0) { 187 error_report("could not load initial ram disk '%s'", 188 initrd_filename); 189 exit(1); 190 } 191 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 192 } else { 193 initrd_base = 0; 194 initrd_size = 0; 195 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 196 } 197 ppc_boot_device = 'm'; 198 } else { 199 kernel_base = 0; 200 kernel_size = 0; 201 initrd_base = 0; 202 initrd_size = 0; 203 ppc_boot_device = '\0'; 204 for (i = 0; boot_device[i] != '\0'; i++) { 205 /* TOFIX: for now, the second IDE channel is not properly 206 * used by OHW. The Mac floppy disk are not emulated. 207 * For now, OHW cannot boot from the network. 208 */ 209 #if 0 210 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 211 ppc_boot_device = boot_device[i]; 212 break; 213 } 214 #else 215 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 216 ppc_boot_device = boot_device[i]; 217 break; 218 } 219 #endif 220 } 221 if (ppc_boot_device == '\0') { 222 error_report("No valid boot device for G3 Beige machine"); 223 exit(1); 224 } 225 } 226 227 /* Register 2 MB of ISA IO space */ 228 memory_region_init_alias(isa, NULL, "isa_mmio", 229 get_system_io(), 0, 0x00200000); 230 memory_region_add_subregion(sysmem, 0xfe000000, isa); 231 232 /* XXX: we register only 1 output pin for heathrow PIC */ 233 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 234 heathrow_irqs[0] = 235 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 236 /* Connect the heathrow PIC outputs to the 6xx bus */ 237 for (i = 0; i < smp_cpus; i++) { 238 switch (PPC_INPUT(env)) { 239 case PPC_FLAGS_INPUT_6xx: 240 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 241 heathrow_irqs[i][0] = 242 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 243 break; 244 default: 245 error_report("Bus model not supported on OldWorld Mac machine"); 246 exit(1); 247 } 248 } 249 250 /* Timebase Frequency */ 251 if (kvm_enabled()) { 252 tbfreq = kvmppc_get_tbfreq(); 253 } else { 254 tbfreq = TBFREQ; 255 } 256 257 /* init basic PC hardware */ 258 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 259 error_report("Only 6xx bus is supported on heathrow machine"); 260 exit(1); 261 } 262 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 263 pci_bus = pci_grackle_init(0xfec00000, pic, 264 get_system_memory(), 265 get_system_io()); 266 pci_vga_init(pci_bus); 267 268 dev = qdev_create(NULL, TYPE_ESCC); 269 qdev_prop_set_uint32(dev, "disabled", 0); 270 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 271 qdev_prop_set_uint32(dev, "it_shift", 4); 272 qdev_prop_set_chr(dev, "chrA", serial_hds[0]); 273 qdev_prop_set_chr(dev, "chrB", serial_hds[1]); 274 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 275 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 276 qdev_init_nofail(dev); 277 278 s = SYS_BUS_DEVICE(dev); 279 sysbus_connect_irq(s, 0, pic[0x10]); 280 sysbus_connect_irq(s, 1, pic[0x0f]); 281 282 escc_mem = &ESCC(s)->mmio; 283 284 memory_region_init_alias(escc_bar, NULL, "escc-bar", 285 escc_mem, 0, memory_region_size(escc_mem)); 286 287 for(i = 0; i < nb_nics; i++) 288 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 289 290 291 ide_drive_get(hd, ARRAY_SIZE(hd)); 292 293 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 294 dev = DEVICE(macio); 295 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 296 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 297 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 298 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 299 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 300 qdev_prop_set_uint64(dev, "frequency", tbfreq); 301 macio_init(macio, pic_mem, escc_bar); 302 303 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 304 "ide[0]")); 305 macio_ide_init_drives(macio_ide, hd); 306 307 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 308 "ide[1]")); 309 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 310 311 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 312 adb_bus = qdev_get_child_bus(dev, "adb.0"); 313 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 314 qdev_init_nofail(dev); 315 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 316 qdev_init_nofail(dev); 317 318 if (machine_usb(machine)) { 319 pci_create_simple(pci_bus, -1, "pci-ohci"); 320 } 321 322 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 323 graphic_depth = 15; 324 325 /* No PCI init: the BIOS will do it */ 326 327 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 328 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 329 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 330 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 331 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 332 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 333 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 334 if (kernel_cmdline) { 335 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 336 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 337 } else { 338 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 339 } 340 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 341 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 342 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 343 344 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 345 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 346 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 347 348 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 349 if (kvm_enabled()) { 350 #ifdef CONFIG_KVM 351 uint8_t *hypercall; 352 353 hypercall = g_malloc(16); 354 kvmppc_get_hypercall(env, hypercall, 16); 355 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 356 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 357 #endif 358 } 359 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 360 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 361 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 362 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 363 364 /* MacOS NDRV VGA driver */ 365 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 366 if (filename) { 367 ndrv_size = get_image_size(filename); 368 if (ndrv_size != -1) { 369 ndrv_file = g_malloc(ndrv_size); 370 ndrv_size = load_image(filename, ndrv_file); 371 372 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 373 } 374 g_free(filename); 375 } 376 377 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 378 } 379 380 static int heathrow_kvm_type(const char *arg) 381 { 382 /* Always force PR KVM */ 383 return 2; 384 } 385 386 static void heathrow_class_init(ObjectClass *oc, void *data) 387 { 388 MachineClass *mc = MACHINE_CLASS(oc); 389 390 mc->desc = "Heathrow based PowerMAC"; 391 mc->init = ppc_heathrow_init; 392 mc->block_default_type = IF_IDE; 393 mc->max_cpus = MAX_CPUS; 394 #ifndef TARGET_PPC64 395 mc->is_default = 1; 396 #endif 397 /* TOFIX "cad" when Mac floppy is implemented */ 398 mc->default_boot_order = "cd"; 399 mc->kvm_type = heathrow_kvm_type; 400 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 401 } 402 403 static const TypeInfo ppc_heathrow_machine_info = { 404 .name = MACHINE_TYPE_NAME("g3beige"), 405 .parent = TYPE_MACHINE, 406 .class_init = heathrow_class_init 407 }; 408 409 static void ppc_heathrow_register_types(void) 410 { 411 type_register_static(&ppc_heathrow_machine_info); 412 } 413 414 type_init(ppc_heathrow_register_types); 415