1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/numa.h" 25 #include "sysemu/cpus.h" 26 #include "hw/hw.h" 27 #include "target/ppc/cpu.h" 28 #include "qemu/log.h" 29 #include "hw/ppc/fdt.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/loader.h" 34 #include "exec/address-spaces.h" 35 #include "qapi/visitor.h" 36 #include "monitor/monitor.h" 37 #include "hw/intc/intc.h" 38 #include "hw/ipmi/ipmi.h" 39 #include "target/ppc/mmu-hash64.h" 40 41 #include "hw/ppc/xics.h" 42 #include "hw/ppc/pnv_xscom.h" 43 44 #include "hw/isa/isa.h" 45 #include "hw/char/serial.h" 46 #include "hw/timer/mc146818rtc.h" 47 48 #include <libfdt.h> 49 50 #define FDT_MAX_SIZE 0x00100000 51 52 #define FW_FILE_NAME "skiboot.lid" 53 #define FW_LOAD_ADDR 0x0 54 #define FW_MAX_SIZE 0x00400000 55 56 #define KERNEL_LOAD_ADDR 0x20000000 57 #define INITRD_LOAD_ADDR 0x60000000 58 59 static const char *pnv_chip_core_typename(const PnvChip *o) 60 { 61 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 62 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 63 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 64 const char *core_type = object_class_get_name(object_class_by_name(s)); 65 g_free(s); 66 return core_type; 67 } 68 69 /* 70 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 71 * 4 * 4 sockets * 12 cores * 8 threads = 1536 72 * Let's make it 2^11 73 */ 74 #define MAX_CPUS 2048 75 76 /* 77 * Memory nodes are created by hostboot, one for each range of memory 78 * that has a different "affinity". In practice, it means one range 79 * per chip. 80 */ 81 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 82 { 83 char *mem_name; 84 uint64_t mem_reg_property[2]; 85 int off; 86 87 mem_reg_property[0] = cpu_to_be64(start); 88 mem_reg_property[1] = cpu_to_be64(size); 89 90 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 91 off = fdt_add_subnode(fdt, 0, mem_name); 92 g_free(mem_name); 93 94 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 95 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 96 sizeof(mem_reg_property)))); 97 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 98 } 99 100 static int get_cpus_node(void *fdt) 101 { 102 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 103 104 if (cpus_offset < 0) { 105 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 106 if (cpus_offset) { 107 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 108 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 109 } 110 } 111 _FDT(cpus_offset); 112 return cpus_offset; 113 } 114 115 /* 116 * The PowerNV cores (and threads) need to use real HW ids and not an 117 * incremental index like it has been done on other platforms. This HW 118 * id is stored in the CPU PIR, it is used to create cpu nodes in the 119 * device tree, used in XSCOM to address cores and in interrupt 120 * servers. 121 */ 122 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 123 { 124 PowerPCCPU *cpu = pc->threads[0]; 125 CPUState *cs = CPU(cpu); 126 DeviceClass *dc = DEVICE_GET_CLASS(cs); 127 int smt_threads = CPU_CORE(pc)->nr_threads; 128 CPUPPCState *env = &cpu->env; 129 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 130 uint32_t servers_prop[smt_threads]; 131 int i; 132 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 133 0xffffffff, 0xffffffff}; 134 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 135 uint32_t cpufreq = 1000000000; 136 uint32_t page_sizes_prop[64]; 137 size_t page_sizes_prop_size; 138 const uint8_t pa_features[] = { 24, 0, 139 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 140 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 141 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 142 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 143 int offset; 144 char *nodename; 145 int cpus_offset = get_cpus_node(fdt); 146 147 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 148 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 149 _FDT(offset); 150 g_free(nodename); 151 152 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 153 154 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 155 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 156 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 157 158 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 160 env->dcache_line_size))); 161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 162 env->dcache_line_size))); 163 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 164 env->icache_line_size))); 165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 166 env->icache_line_size))); 167 168 if (pcc->l1_dcache_size) { 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 170 pcc->l1_dcache_size))); 171 } else { 172 warn_report("Unknown L1 dcache size for cpu"); 173 } 174 if (pcc->l1_icache_size) { 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 176 pcc->l1_icache_size))); 177 } else { 178 warn_report("Unknown L1 icache size for cpu"); 179 } 180 181 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 182 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 183 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 184 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 185 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 186 187 if (env->spr_cb[SPR_PURR].oea_read) { 188 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 189 } 190 191 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 192 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 193 segs, sizeof(segs)))); 194 } 195 196 /* Advertise VMX/VSX (vector extensions) if available 197 * 0 / no property == no vector extensions 198 * 1 == VMX / Altivec available 199 * 2 == VSX available */ 200 if (env->insns_flags & PPC_ALTIVEC) { 201 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 202 203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 204 } 205 206 /* Advertise DFP (Decimal Floating Point) if available 207 * 0 / no property == no DFP 208 * 1 == DFP available */ 209 if (env->insns_flags2 & PPC2_DFP) { 210 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 211 } 212 213 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 214 sizeof(page_sizes_prop)); 215 if (page_sizes_prop_size) { 216 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 217 page_sizes_prop, page_sizes_prop_size))); 218 } 219 220 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 221 pa_features, sizeof(pa_features)))); 222 223 /* Build interrupt servers properties */ 224 for (i = 0; i < smt_threads; i++) { 225 servers_prop[i] = cpu_to_be32(pc->pir + i); 226 } 227 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 228 servers_prop, sizeof(servers_prop)))); 229 } 230 231 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 232 uint32_t nr_threads) 233 { 234 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 235 char *name; 236 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 237 uint32_t irange[2], i, rsize; 238 uint64_t *reg; 239 int offset; 240 241 irange[0] = cpu_to_be32(pir); 242 irange[1] = cpu_to_be32(nr_threads); 243 244 rsize = sizeof(uint64_t) * 2 * nr_threads; 245 reg = g_malloc(rsize); 246 for (i = 0; i < nr_threads; i++) { 247 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 248 reg[i * 2 + 1] = cpu_to_be64(0x1000); 249 } 250 251 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 252 offset = fdt_add_subnode(fdt, 0, name); 253 _FDT(offset); 254 g_free(name); 255 256 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 257 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 258 _FDT((fdt_setprop_string(fdt, offset, "device_type", 259 "PowerPC-External-Interrupt-Presentation"))); 260 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 261 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 262 irange, sizeof(irange)))); 263 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 264 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 265 g_free(reg); 266 } 267 268 static void pnv_dt_chip(PnvChip *chip, void *fdt) 269 { 270 const char *typename = pnv_chip_core_typename(chip); 271 size_t typesize = object_type_get_instance_size(typename); 272 int i; 273 274 pnv_dt_xscom(chip, fdt, 0); 275 276 for (i = 0; i < chip->nr_cores; i++) { 277 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 278 279 pnv_dt_core(chip, pnv_core, fdt); 280 281 /* Interrupt Control Presenters (ICP). One per core. */ 282 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 283 } 284 285 if (chip->ram_size) { 286 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 287 } 288 } 289 290 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 291 { 292 uint32_t io_base = d->ioport_id; 293 uint32_t io_regs[] = { 294 cpu_to_be32(1), 295 cpu_to_be32(io_base), 296 cpu_to_be32(2) 297 }; 298 char *name; 299 int node; 300 301 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 302 node = fdt_add_subnode(fdt, lpc_off, name); 303 _FDT(node); 304 g_free(name); 305 306 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 307 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 308 } 309 310 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 311 { 312 const char compatible[] = "ns16550\0pnpPNP,501"; 313 uint32_t io_base = d->ioport_id; 314 uint32_t io_regs[] = { 315 cpu_to_be32(1), 316 cpu_to_be32(io_base), 317 cpu_to_be32(8) 318 }; 319 char *name; 320 int node; 321 322 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 323 node = fdt_add_subnode(fdt, lpc_off, name); 324 _FDT(node); 325 g_free(name); 326 327 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 328 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 329 sizeof(compatible)))); 330 331 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 332 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 333 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 334 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 335 fdt_get_phandle(fdt, lpc_off)))); 336 337 /* This is needed by Linux */ 338 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 339 } 340 341 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 342 { 343 const char compatible[] = "bt\0ipmi-bt"; 344 uint32_t io_base; 345 uint32_t io_regs[] = { 346 cpu_to_be32(1), 347 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 348 cpu_to_be32(3) 349 }; 350 uint32_t irq; 351 char *name; 352 int node; 353 354 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 355 io_regs[1] = cpu_to_be32(io_base); 356 357 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 358 359 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 360 node = fdt_add_subnode(fdt, lpc_off, name); 361 _FDT(node); 362 g_free(name); 363 364 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 365 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 366 sizeof(compatible)))); 367 368 /* Mark it as reserved to avoid Linux trying to claim it */ 369 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 370 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 371 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 372 fdt_get_phandle(fdt, lpc_off)))); 373 } 374 375 typedef struct ForeachPopulateArgs { 376 void *fdt; 377 int offset; 378 } ForeachPopulateArgs; 379 380 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 381 { 382 ForeachPopulateArgs *args = opaque; 383 ISADevice *d = ISA_DEVICE(dev); 384 385 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 386 pnv_dt_rtc(d, args->fdt, args->offset); 387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 388 pnv_dt_serial(d, args->fdt, args->offset); 389 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 390 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 391 } else { 392 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 393 d->ioport_id); 394 } 395 396 return 0; 397 } 398 399 static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) 400 { 401 char *name; 402 int offset; 403 404 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 405 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); 406 offset = fdt_path_offset(fdt, name); 407 g_free(name); 408 return offset; 409 } 410 411 /* The default LPC bus of a multichip system is on chip 0. It's 412 * recognized by the firmware (skiboot) using a "primary" property. 413 */ 414 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 415 { 416 int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt); 417 ForeachPopulateArgs args = { 418 .fdt = fdt, 419 .offset = isa_offset, 420 }; 421 422 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 423 424 /* ISA devices are not necessarily parented to the ISA bus so we 425 * can not use object_child_foreach() */ 426 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 427 &args); 428 } 429 430 static void *pnv_dt_create(MachineState *machine) 431 { 432 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 433 PnvMachineState *pnv = PNV_MACHINE(machine); 434 void *fdt; 435 char *buf; 436 int off; 437 int i; 438 439 fdt = g_malloc0(FDT_MAX_SIZE); 440 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 441 442 /* Root node */ 443 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 444 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 445 _FDT((fdt_setprop_string(fdt, 0, "model", 446 "IBM PowerNV (emulated by qemu)"))); 447 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 448 sizeof(plat_compat)))); 449 450 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 451 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 452 if (qemu_uuid_set) { 453 _FDT((fdt_property_string(fdt, "system-id", buf))); 454 } 455 g_free(buf); 456 457 off = fdt_add_subnode(fdt, 0, "chosen"); 458 if (machine->kernel_cmdline) { 459 _FDT((fdt_setprop_string(fdt, off, "bootargs", 460 machine->kernel_cmdline))); 461 } 462 463 if (pnv->initrd_size) { 464 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 465 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 466 467 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 468 &start_prop, sizeof(start_prop)))); 469 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 470 &end_prop, sizeof(end_prop)))); 471 } 472 473 /* Populate device tree for each chip */ 474 for (i = 0; i < pnv->num_chips; i++) { 475 pnv_dt_chip(pnv->chips[i], fdt); 476 } 477 478 /* Populate ISA devices on chip 0 */ 479 pnv_dt_isa(pnv, fdt); 480 481 if (pnv->bmc) { 482 pnv_dt_bmc_sensors(pnv->bmc, fdt); 483 } 484 485 return fdt; 486 } 487 488 static void pnv_powerdown_notify(Notifier *n, void *opaque) 489 { 490 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 491 492 if (pnv->bmc) { 493 pnv_bmc_powerdown(pnv->bmc); 494 } 495 } 496 497 static void pnv_reset(void) 498 { 499 MachineState *machine = MACHINE(qdev_get_machine()); 500 PnvMachineState *pnv = PNV_MACHINE(machine); 501 void *fdt; 502 Object *obj; 503 504 qemu_devices_reset(); 505 506 /* OpenPOWER systems have a BMC, which can be defined on the 507 * command line with: 508 * 509 * -device ipmi-bmc-sim,id=bmc0 510 * 511 * This is the internal simulator but it could also be an external 512 * BMC. 513 */ 514 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 515 if (obj) { 516 pnv->bmc = IPMI_BMC(obj); 517 } 518 519 fdt = pnv_dt_create(machine); 520 521 /* Pack resulting tree */ 522 _FDT((fdt_pack(fdt))); 523 524 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 525 } 526 527 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 528 { 529 Pnv8Chip *chip8 = PNV8_CHIP(chip); 530 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 531 } 532 533 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 534 { 535 Pnv8Chip *chip8 = PNV8_CHIP(chip); 536 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 537 } 538 539 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 540 { 541 return NULL; 542 } 543 544 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 545 { 546 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 547 } 548 549 static void pnv_init(MachineState *machine) 550 { 551 PnvMachineState *pnv = PNV_MACHINE(machine); 552 MemoryRegion *ram; 553 char *fw_filename; 554 long fw_size; 555 int i; 556 char *chip_typename; 557 558 /* allocate RAM */ 559 if (machine->ram_size < (1 * GiB)) { 560 warn_report("skiboot may not work with < 1GB of RAM"); 561 } 562 563 ram = g_new(MemoryRegion, 1); 564 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 565 machine->ram_size); 566 memory_region_add_subregion(get_system_memory(), 0, ram); 567 568 /* load skiboot firmware */ 569 if (bios_name == NULL) { 570 bios_name = FW_FILE_NAME; 571 } 572 573 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 574 if (!fw_filename) { 575 error_report("Could not find OPAL firmware '%s'", bios_name); 576 exit(1); 577 } 578 579 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 580 if (fw_size < 0) { 581 error_report("Could not load OPAL firmware '%s'", fw_filename); 582 exit(1); 583 } 584 g_free(fw_filename); 585 586 /* load kernel */ 587 if (machine->kernel_filename) { 588 long kernel_size; 589 590 kernel_size = load_image_targphys(machine->kernel_filename, 591 KERNEL_LOAD_ADDR, 0x2000000); 592 if (kernel_size < 0) { 593 error_report("Could not load kernel '%s'", 594 machine->kernel_filename); 595 exit(1); 596 } 597 } 598 599 /* load initrd */ 600 if (machine->initrd_filename) { 601 pnv->initrd_base = INITRD_LOAD_ADDR; 602 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 603 pnv->initrd_base, 0x10000000); /* 128MB max */ 604 if (pnv->initrd_size < 0) { 605 error_report("Could not load initial ram disk '%s'", 606 machine->initrd_filename); 607 exit(1); 608 } 609 } 610 611 /* Create the processor chips */ 612 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 613 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 614 i, machine->cpu_type); 615 if (!object_class_by_name(chip_typename)) { 616 error_report("invalid CPU model '%.*s' for %s machine", 617 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 618 exit(1); 619 } 620 621 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 622 for (i = 0; i < pnv->num_chips; i++) { 623 char chip_name[32]; 624 Object *chip = object_new(chip_typename); 625 626 pnv->chips[i] = PNV_CHIP(chip); 627 628 /* TODO: put all the memory in one node on chip 0 until we find a 629 * way to specify different ranges for each chip 630 */ 631 if (i == 0) { 632 object_property_set_int(chip, machine->ram_size, "ram-size", 633 &error_fatal); 634 } 635 636 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 637 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 638 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 639 &error_fatal); 640 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 641 object_property_set_bool(chip, true, "realized", &error_fatal); 642 } 643 g_free(chip_typename); 644 645 /* Instantiate ISA bus on chip 0 */ 646 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 647 648 /* Create serial port */ 649 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 650 651 /* Create an RTC ISA device too */ 652 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 653 654 /* OpenPOWER systems use a IPMI SEL Event message to notify the 655 * host to powerdown */ 656 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 657 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 658 } 659 660 /* 661 * 0:21 Reserved - Read as zeros 662 * 22:24 Chip ID 663 * 25:28 Core number 664 * 29:31 Thread ID 665 */ 666 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 667 { 668 return (chip->chip_id << 7) | (core_id << 3); 669 } 670 671 static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child, 672 Error **errp) 673 { 674 return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 675 errp); 676 } 677 678 /* 679 * 0:48 Reserved - Read as zeroes 680 * 49:52 Node ID 681 * 53:55 Chip ID 682 * 56 Reserved - Read as zero 683 * 57:61 Core number 684 * 62:63 Thread ID 685 * 686 * We only care about the lower bits. uint32_t is fine for the moment. 687 */ 688 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 689 { 690 return (chip->chip_id << 8) | (core_id << 2); 691 } 692 693 static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, 694 Error **errp) 695 { 696 return NULL; 697 } 698 699 /* Allowed core identifiers on a POWER8 Processor Chip : 700 * 701 * <EX0 reserved> 702 * EX1 - Venice only 703 * EX2 - Venice only 704 * EX3 - Venice only 705 * EX4 706 * EX5 707 * EX6 708 * <EX7,8 reserved> <reserved> 709 * EX9 - Venice only 710 * EX10 - Venice only 711 * EX11 - Venice only 712 * EX12 713 * EX13 714 * EX14 715 * <EX15 reserved> 716 */ 717 #define POWER8E_CORE_MASK (0x7070ull) 718 #define POWER8_CORE_MASK (0x7e7eull) 719 720 /* 721 * POWER9 has 24 cores, ids starting at 0x0 722 */ 723 #define POWER9_CORE_MASK (0xffffffffffffffull) 724 725 static void pnv_chip_power8_instance_init(Object *obj) 726 { 727 Pnv8Chip *chip8 = PNV8_CHIP(obj); 728 729 object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI); 730 object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL); 731 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 732 OBJECT(qdev_get_machine()), &error_abort); 733 734 object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC); 735 object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL); 736 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 737 OBJECT(&chip8->psi), &error_abort); 738 739 object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC); 740 object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL); 741 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 742 OBJECT(&chip8->psi), &error_abort); 743 } 744 745 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 746 { 747 PnvChip *chip = PNV_CHIP(chip8); 748 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 749 const char *typename = pnv_chip_core_typename(chip); 750 size_t typesize = object_type_get_instance_size(typename); 751 int i, j; 752 char *name; 753 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 754 755 name = g_strdup_printf("icp-%x", chip->chip_id); 756 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 757 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 758 g_free(name); 759 760 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 761 762 /* Map the ICP registers for each thread */ 763 for (i = 0; i < chip->nr_cores; i++) { 764 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 765 int core_hwid = CPU_CORE(pnv_core)->core_id; 766 767 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 768 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 769 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 770 771 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 772 &icp->mmio); 773 } 774 } 775 } 776 777 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 778 { 779 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 780 PnvChip *chip = PNV_CHIP(dev); 781 Pnv8Chip *chip8 = PNV8_CHIP(dev); 782 Error *local_err = NULL; 783 784 pcc->parent_realize(dev, &local_err); 785 if (local_err) { 786 error_propagate(errp, local_err); 787 return; 788 } 789 790 /* Processor Service Interface (PSI) Host Bridge */ 791 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 792 "bar", &error_fatal); 793 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 794 if (local_err) { 795 error_propagate(errp, local_err); 796 return; 797 } 798 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs); 799 800 /* Create LPC controller */ 801 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 802 &error_fatal); 803 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 804 805 /* Interrupt Management Area. This is the memory region holding 806 * all the Interrupt Control Presenter (ICP) registers */ 807 pnv_chip_icp_realize(chip8, &local_err); 808 if (local_err) { 809 error_propagate(errp, local_err); 810 return; 811 } 812 813 /* Create the simplified OCC model */ 814 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 815 if (local_err) { 816 error_propagate(errp, local_err); 817 return; 818 } 819 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 820 } 821 822 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 823 { 824 DeviceClass *dc = DEVICE_CLASS(klass); 825 PnvChipClass *k = PNV_CHIP_CLASS(klass); 826 827 k->chip_type = PNV_CHIP_POWER8E; 828 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 829 k->cores_mask = POWER8E_CORE_MASK; 830 k->core_pir = pnv_chip_core_pir_p8; 831 k->intc_create = pnv_chip_power8_intc_create; 832 k->isa_create = pnv_chip_power8_isa_create; 833 k->xscom_base = 0x003fc0000000000ull; 834 dc->desc = "PowerNV Chip POWER8E"; 835 836 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 837 &k->parent_realize); 838 } 839 840 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 841 { 842 DeviceClass *dc = DEVICE_CLASS(klass); 843 PnvChipClass *k = PNV_CHIP_CLASS(klass); 844 845 k->chip_type = PNV_CHIP_POWER8; 846 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 847 k->cores_mask = POWER8_CORE_MASK; 848 k->core_pir = pnv_chip_core_pir_p8; 849 k->intc_create = pnv_chip_power8_intc_create; 850 k->isa_create = pnv_chip_power8_isa_create; 851 k->xscom_base = 0x003fc0000000000ull; 852 dc->desc = "PowerNV Chip POWER8"; 853 854 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 855 &k->parent_realize); 856 } 857 858 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 859 { 860 DeviceClass *dc = DEVICE_CLASS(klass); 861 PnvChipClass *k = PNV_CHIP_CLASS(klass); 862 863 k->chip_type = PNV_CHIP_POWER8NVL; 864 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 865 k->cores_mask = POWER8_CORE_MASK; 866 k->core_pir = pnv_chip_core_pir_p8; 867 k->intc_create = pnv_chip_power8_intc_create; 868 k->isa_create = pnv_chip_power8nvl_isa_create; 869 k->xscom_base = 0x003fc0000000000ull; 870 dc->desc = "PowerNV Chip POWER8NVL"; 871 872 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 873 &k->parent_realize); 874 } 875 876 static void pnv_chip_power9_instance_init(Object *obj) 877 { 878 } 879 880 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 881 { 882 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 883 Error *local_err = NULL; 884 885 pcc->parent_realize(dev, &local_err); 886 if (local_err) { 887 error_propagate(errp, local_err); 888 return; 889 } 890 } 891 892 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 893 { 894 DeviceClass *dc = DEVICE_CLASS(klass); 895 PnvChipClass *k = PNV_CHIP_CLASS(klass); 896 897 k->chip_type = PNV_CHIP_POWER9; 898 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 899 k->cores_mask = POWER9_CORE_MASK; 900 k->core_pir = pnv_chip_core_pir_p9; 901 k->intc_create = pnv_chip_power9_intc_create; 902 k->isa_create = pnv_chip_power9_isa_create; 903 k->xscom_base = 0x00603fc00000000ull; 904 dc->desc = "PowerNV Chip POWER9"; 905 906 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 907 &k->parent_realize); 908 } 909 910 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 911 { 912 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 913 int cores_max; 914 915 /* 916 * No custom mask for this chip, let's use the default one from * 917 * the chip class 918 */ 919 if (!chip->cores_mask) { 920 chip->cores_mask = pcc->cores_mask; 921 } 922 923 /* filter alien core ids ! some are reserved */ 924 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 925 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 926 chip->cores_mask); 927 return; 928 } 929 chip->cores_mask &= pcc->cores_mask; 930 931 /* now that we have a sane layout, let check the number of cores */ 932 cores_max = ctpop64(chip->cores_mask); 933 if (chip->nr_cores > cores_max) { 934 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 935 cores_max); 936 return; 937 } 938 } 939 940 static void pnv_chip_instance_init(Object *obj) 941 { 942 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base; 943 } 944 945 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 946 { 947 Error *error = NULL; 948 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 949 const char *typename = pnv_chip_core_typename(chip); 950 size_t typesize = object_type_get_instance_size(typename); 951 int i, core_hwid; 952 953 if (!object_class_by_name(typename)) { 954 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 955 return; 956 } 957 958 /* Cores */ 959 pnv_chip_core_sanitize(chip, &error); 960 if (error) { 961 error_propagate(errp, error); 962 return; 963 } 964 965 chip->cores = g_malloc0(typesize * chip->nr_cores); 966 967 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 968 && (i < chip->nr_cores); core_hwid++) { 969 char core_name[32]; 970 void *pnv_core = chip->cores + i * typesize; 971 uint64_t xscom_core_base; 972 973 if (!(chip->cores_mask & (1ull << core_hwid))) { 974 continue; 975 } 976 977 object_initialize(pnv_core, typesize, typename); 978 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 979 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 980 &error_fatal); 981 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 982 &error_fatal); 983 object_property_set_int(OBJECT(pnv_core), core_hwid, 984 CPU_CORE_PROP_CORE_ID, &error_fatal); 985 object_property_set_int(OBJECT(pnv_core), 986 pcc->core_pir(chip, core_hwid), 987 "pir", &error_fatal); 988 object_property_add_const_link(OBJECT(pnv_core), "chip", 989 OBJECT(chip), &error_fatal); 990 object_property_set_bool(OBJECT(pnv_core), true, "realized", 991 &error_fatal); 992 object_unref(OBJECT(pnv_core)); 993 994 /* Each core has an XSCOM MMIO region */ 995 if (!pnv_chip_is_power9(chip)) { 996 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 997 } else { 998 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid); 999 } 1000 1001 pnv_xscom_add_subregion(chip, xscom_core_base, 1002 &PNV_CORE(pnv_core)->xscom_regs); 1003 i++; 1004 } 1005 } 1006 1007 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1008 { 1009 PnvChip *chip = PNV_CHIP(dev); 1010 Error *error = NULL; 1011 1012 /* XSCOM bridge */ 1013 pnv_xscom_realize(chip, &error); 1014 if (error) { 1015 error_propagate(errp, error); 1016 return; 1017 } 1018 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1019 1020 /* Cores */ 1021 pnv_chip_core_realize(chip, &error); 1022 if (error) { 1023 error_propagate(errp, error); 1024 return; 1025 } 1026 } 1027 1028 static Property pnv_chip_properties[] = { 1029 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1030 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1031 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1032 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1033 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1034 DEFINE_PROP_END_OF_LIST(), 1035 }; 1036 1037 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1038 { 1039 DeviceClass *dc = DEVICE_CLASS(klass); 1040 1041 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1042 dc->realize = pnv_chip_realize; 1043 dc->props = pnv_chip_properties; 1044 dc->desc = "PowerNV Chip"; 1045 } 1046 1047 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1048 { 1049 PnvMachineState *pnv = PNV_MACHINE(xi); 1050 int i; 1051 1052 for (i = 0; i < pnv->num_chips; i++) { 1053 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1054 1055 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1056 return &chip8->psi.ics; 1057 } 1058 } 1059 return NULL; 1060 } 1061 1062 static void pnv_ics_resend(XICSFabric *xi) 1063 { 1064 PnvMachineState *pnv = PNV_MACHINE(xi); 1065 int i; 1066 1067 for (i = 0; i < pnv->num_chips; i++) { 1068 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1069 ics_resend(&chip8->psi.ics); 1070 } 1071 } 1072 1073 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1074 { 1075 CPUState *cs; 1076 1077 CPU_FOREACH(cs) { 1078 PowerPCCPU *cpu = POWERPC_CPU(cs); 1079 CPUPPCState *env = &cpu->env; 1080 1081 if (env->spr_cb[SPR_PIR].default_value == pir) { 1082 return cpu; 1083 } 1084 } 1085 1086 return NULL; 1087 } 1088 1089 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1090 { 1091 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1092 1093 return cpu ? ICP(cpu->intc) : NULL; 1094 } 1095 1096 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1097 Monitor *mon) 1098 { 1099 PnvMachineState *pnv = PNV_MACHINE(obj); 1100 int i; 1101 CPUState *cs; 1102 1103 CPU_FOREACH(cs) { 1104 PowerPCCPU *cpu = POWERPC_CPU(cs); 1105 1106 icp_pic_print_info(ICP(cpu->intc), mon); 1107 } 1108 1109 for (i = 0; i < pnv->num_chips; i++) { 1110 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1111 ics_pic_print_info(&chip8->psi.ics, mon); 1112 } 1113 } 1114 1115 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1116 void *opaque, Error **errp) 1117 { 1118 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1119 } 1120 1121 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1122 void *opaque, Error **errp) 1123 { 1124 PnvMachineState *pnv = PNV_MACHINE(obj); 1125 uint32_t num_chips; 1126 Error *local_err = NULL; 1127 1128 visit_type_uint32(v, name, &num_chips, &local_err); 1129 if (local_err) { 1130 error_propagate(errp, local_err); 1131 return; 1132 } 1133 1134 /* 1135 * TODO: should we decide on how many chips we can create based 1136 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1137 */ 1138 if (!is_power_of_2(num_chips) || num_chips > 4) { 1139 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1140 return; 1141 } 1142 1143 pnv->num_chips = num_chips; 1144 } 1145 1146 static void pnv_machine_instance_init(Object *obj) 1147 { 1148 PnvMachineState *pnv = PNV_MACHINE(obj); 1149 pnv->num_chips = 1; 1150 } 1151 1152 static void pnv_machine_class_props_init(ObjectClass *oc) 1153 { 1154 object_class_property_add(oc, "num-chips", "uint32", 1155 pnv_get_num_chips, pnv_set_num_chips, 1156 NULL, NULL, NULL); 1157 object_class_property_set_description(oc, "num-chips", 1158 "Specifies the number of processor chips", 1159 NULL); 1160 } 1161 1162 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1163 { 1164 MachineClass *mc = MACHINE_CLASS(oc); 1165 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1166 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1167 1168 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1169 mc->init = pnv_init; 1170 mc->reset = pnv_reset; 1171 mc->max_cpus = MAX_CPUS; 1172 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1173 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1174 * storage */ 1175 mc->no_parallel = 1; 1176 mc->default_boot_order = NULL; 1177 mc->default_ram_size = 1 * GiB; 1178 xic->icp_get = pnv_icp_get; 1179 xic->ics_get = pnv_ics_get; 1180 xic->ics_resend = pnv_ics_resend; 1181 ispc->print_info = pnv_pic_print_info; 1182 1183 pnv_machine_class_props_init(oc); 1184 } 1185 1186 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1187 { \ 1188 .name = type, \ 1189 .class_init = class_initfn, \ 1190 .parent = TYPE_PNV8_CHIP, \ 1191 } 1192 1193 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1194 { \ 1195 .name = type, \ 1196 .class_init = class_initfn, \ 1197 .parent = TYPE_PNV9_CHIP, \ 1198 } 1199 1200 static const TypeInfo types[] = { 1201 { 1202 .name = TYPE_PNV_MACHINE, 1203 .parent = TYPE_MACHINE, 1204 .instance_size = sizeof(PnvMachineState), 1205 .instance_init = pnv_machine_instance_init, 1206 .class_init = pnv_machine_class_init, 1207 .interfaces = (InterfaceInfo[]) { 1208 { TYPE_XICS_FABRIC }, 1209 { TYPE_INTERRUPT_STATS_PROVIDER }, 1210 { }, 1211 }, 1212 }, 1213 { 1214 .name = TYPE_PNV_CHIP, 1215 .parent = TYPE_SYS_BUS_DEVICE, 1216 .class_init = pnv_chip_class_init, 1217 .instance_init = pnv_chip_instance_init, 1218 .instance_size = sizeof(PnvChip), 1219 .class_size = sizeof(PnvChipClass), 1220 .abstract = true, 1221 }, 1222 1223 /* 1224 * P9 chip and variants 1225 */ 1226 { 1227 .name = TYPE_PNV9_CHIP, 1228 .parent = TYPE_PNV_CHIP, 1229 .instance_init = pnv_chip_power9_instance_init, 1230 .instance_size = sizeof(Pnv9Chip), 1231 }, 1232 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1233 1234 /* 1235 * P8 chip and variants 1236 */ 1237 { 1238 .name = TYPE_PNV8_CHIP, 1239 .parent = TYPE_PNV_CHIP, 1240 .instance_init = pnv_chip_power8_instance_init, 1241 .instance_size = sizeof(Pnv8Chip), 1242 }, 1243 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1244 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1245 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1246 pnv_chip_power8nvl_class_init), 1247 }; 1248 1249 DEFINE_TYPES(types) 1250