1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "sysemu/hw_accel.h" 31 #include "target/ppc/cpu.h" 32 #include "qemu/log.h" 33 #include "hw/ppc/fdt.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/ppc/pnv.h" 36 #include "hw/ppc/pnv_core.h" 37 #include "hw/loader.h" 38 #include "hw/nmi.h" 39 #include "exec/address-spaces.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/boards.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (256 * MiB) 67 #define INITRD_LOAD_ADDR 0x60000000 68 #define INITRD_MAX_SIZE (256 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (env->spr_cb[SPR_PURR].oea_read) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 warn_report("machine has no BMC device. Use '-device " 591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 592 "to define one"); 593 } else { 594 pnv_bmc_set_pnor(bmc, pnv->pnor); 595 pnv->bmc = bmc; 596 } 597 } 598 599 fdt = pnv_dt_create(machine); 600 601 /* Pack resulting tree */ 602 _FDT((fdt_pack(fdt))); 603 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 606 607 g_free(fdt); 608 } 609 610 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 611 { 612 Pnv8Chip *chip8 = PNV8_CHIP(chip); 613 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 614 } 615 616 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 620 } 621 622 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 623 { 624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 625 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 626 } 627 628 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 629 { 630 Pnv10Chip *chip10 = PNV10_CHIP(chip); 631 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 632 } 633 634 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 635 { 636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 637 } 638 639 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 int i; 643 644 ics_pic_print_info(&chip8->psi.ics, mon); 645 for (i = 0; i < chip->num_phbs; i++) { 646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 647 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 648 } 649 } 650 651 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 652 { 653 Pnv9Chip *chip9 = PNV9_CHIP(chip); 654 int i, j; 655 656 pnv_xive_pic_print_info(&chip9->xive, mon); 657 pnv_psi_pic_print_info(&chip9->psi, mon); 658 659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 660 PnvPhb4PecState *pec = &chip9->pecs[i]; 661 for (j = 0; j < pec->num_stacks; j++) { 662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 663 } 664 } 665 } 666 667 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 668 uint32_t core_id) 669 { 670 return PNV_XSCOM_EX_BASE(core_id); 671 } 672 673 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 674 uint32_t core_id) 675 { 676 return PNV9_XSCOM_EC_BASE(core_id); 677 } 678 679 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 680 uint32_t core_id) 681 { 682 return PNV10_XSCOM_EC_BASE(core_id); 683 } 684 685 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 686 { 687 PowerPCCPUClass *ppc_default = 688 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 689 PowerPCCPUClass *ppc = 690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 691 692 return ppc_default->pvr_match(ppc_default, ppc->pvr); 693 } 694 695 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 696 { 697 Object *obj; 698 699 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 700 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 701 object_property_set_int(obj, irq, "irq", &error_fatal); 702 object_property_set_bool(obj, true, "realized", &error_fatal); 703 } 704 705 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 706 { 707 Pnv10Chip *chip10 = PNV10_CHIP(chip); 708 709 pnv_psi_pic_print_info(&chip10->psi, mon); 710 } 711 712 static void pnv_init(MachineState *machine) 713 { 714 PnvMachineState *pnv = PNV_MACHINE(machine); 715 MachineClass *mc = MACHINE_GET_CLASS(machine); 716 char *fw_filename; 717 long fw_size; 718 int i; 719 char *chip_typename; 720 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 721 DeviceState *dev; 722 723 /* allocate RAM */ 724 if (machine->ram_size < (1 * GiB)) { 725 warn_report("skiboot may not work with < 1GB of RAM"); 726 } 727 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 728 729 /* 730 * Create our simple PNOR device 731 */ 732 dev = qdev_create(NULL, TYPE_PNV_PNOR); 733 if (pnor) { 734 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 735 &error_abort); 736 } 737 qdev_init_nofail(dev); 738 pnv->pnor = PNV_PNOR(dev); 739 740 /* load skiboot firmware */ 741 if (bios_name == NULL) { 742 bios_name = FW_FILE_NAME; 743 } 744 745 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 746 if (!fw_filename) { 747 error_report("Could not find OPAL firmware '%s'", bios_name); 748 exit(1); 749 } 750 751 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 752 if (fw_size < 0) { 753 error_report("Could not load OPAL firmware '%s'", fw_filename); 754 exit(1); 755 } 756 g_free(fw_filename); 757 758 /* load kernel */ 759 if (machine->kernel_filename) { 760 long kernel_size; 761 762 kernel_size = load_image_targphys(machine->kernel_filename, 763 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 764 if (kernel_size < 0) { 765 error_report("Could not load kernel '%s'", 766 machine->kernel_filename); 767 exit(1); 768 } 769 } 770 771 /* load initrd */ 772 if (machine->initrd_filename) { 773 pnv->initrd_base = INITRD_LOAD_ADDR; 774 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 775 pnv->initrd_base, INITRD_MAX_SIZE); 776 if (pnv->initrd_size < 0) { 777 error_report("Could not load initial ram disk '%s'", 778 machine->initrd_filename); 779 exit(1); 780 } 781 } 782 783 /* MSIs are supported on this platform */ 784 msi_nonbroken = true; 785 786 /* 787 * Check compatibility of the specified CPU with the machine 788 * default. 789 */ 790 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 791 error_report("invalid CPU model '%s' for %s machine", 792 machine->cpu_type, mc->name); 793 exit(1); 794 } 795 796 /* Create the processor chips */ 797 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 798 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 799 i, machine->cpu_type); 800 if (!object_class_by_name(chip_typename)) { 801 error_report("invalid chip model '%.*s' for %s machine", 802 i, machine->cpu_type, mc->name); 803 exit(1); 804 } 805 806 pnv->num_chips = 807 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 808 /* 809 * TODO: should we decide on how many chips we can create based 810 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 811 */ 812 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 813 error_report("invalid number of chips: '%d'", pnv->num_chips); 814 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 815 exit(1); 816 } 817 818 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 819 for (i = 0; i < pnv->num_chips; i++) { 820 char chip_name[32]; 821 Object *chip = object_new(chip_typename); 822 823 pnv->chips[i] = PNV_CHIP(chip); 824 825 /* 826 * TODO: put all the memory in one node on chip 0 until we find a 827 * way to specify different ranges for each chip 828 */ 829 if (i == 0) { 830 object_property_set_int(chip, machine->ram_size, "ram-size", 831 &error_fatal); 832 } 833 834 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 835 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 836 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 837 &error_fatal); 838 object_property_set_int(chip, machine->smp.cores, 839 "nr-cores", &error_fatal); 840 object_property_set_int(chip, machine->smp.threads, 841 "nr-threads", &error_fatal); 842 /* 843 * The POWER8 machine use the XICS interrupt interface. 844 * Propagate the XICS fabric to the chip and its controllers. 845 */ 846 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 847 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 848 } 849 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 850 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 851 &error_abort); 852 } 853 object_property_set_bool(chip, true, "realized", &error_fatal); 854 } 855 g_free(chip_typename); 856 857 /* Instantiate ISA bus on chip 0 */ 858 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 859 860 /* Create serial port */ 861 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 862 863 /* Create an RTC ISA device too */ 864 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 865 866 /* 867 * Create the machine BMC simulator and the IPMI BT device for 868 * communication with the BMC 869 */ 870 if (defaults_enabled()) { 871 pnv->bmc = pnv_bmc_create(pnv->pnor); 872 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 873 } 874 875 /* 876 * OpenPOWER systems use a IPMI SEL Event message to notify the 877 * host to powerdown 878 */ 879 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 880 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 881 } 882 883 /* 884 * 0:21 Reserved - Read as zeros 885 * 22:24 Chip ID 886 * 25:28 Core number 887 * 29:31 Thread ID 888 */ 889 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 890 { 891 return (chip->chip_id << 7) | (core_id << 3); 892 } 893 894 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 895 Error **errp) 896 { 897 Pnv8Chip *chip8 = PNV8_CHIP(chip); 898 Error *local_err = NULL; 899 Object *obj; 900 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 901 902 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 903 if (local_err) { 904 error_propagate(errp, local_err); 905 return; 906 } 907 908 pnv_cpu->intc = obj; 909 } 910 911 912 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 913 { 914 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 915 916 icp_reset(ICP(pnv_cpu->intc)); 917 } 918 919 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 920 { 921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 922 923 icp_destroy(ICP(pnv_cpu->intc)); 924 pnv_cpu->intc = NULL; 925 } 926 927 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 928 Monitor *mon) 929 { 930 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 931 } 932 933 /* 934 * 0:48 Reserved - Read as zeroes 935 * 49:52 Node ID 936 * 53:55 Chip ID 937 * 56 Reserved - Read as zero 938 * 57:61 Core number 939 * 62:63 Thread ID 940 * 941 * We only care about the lower bits. uint32_t is fine for the moment. 942 */ 943 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 944 { 945 return (chip->chip_id << 8) | (core_id << 2); 946 } 947 948 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 949 { 950 return (chip->chip_id << 8) | (core_id << 2); 951 } 952 953 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 954 Error **errp) 955 { 956 Pnv9Chip *chip9 = PNV9_CHIP(chip); 957 Error *local_err = NULL; 958 Object *obj; 959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 960 961 /* 962 * The core creates its interrupt presenter but the XIVE interrupt 963 * controller object is initialized afterwards. Hopefully, it's 964 * only used at runtime. 965 */ 966 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 967 &local_err); 968 if (local_err) { 969 error_propagate(errp, local_err); 970 return; 971 } 972 973 pnv_cpu->intc = obj; 974 } 975 976 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 977 { 978 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 979 980 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 981 } 982 983 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 984 { 985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 986 987 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 988 pnv_cpu->intc = NULL; 989 } 990 991 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 992 Monitor *mon) 993 { 994 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 995 } 996 997 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 998 Error **errp) 999 { 1000 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1001 1002 /* Will be defined when the interrupt controller is */ 1003 pnv_cpu->intc = NULL; 1004 } 1005 1006 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1007 { 1008 ; 1009 } 1010 1011 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1012 { 1013 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1014 1015 pnv_cpu->intc = NULL; 1016 } 1017 1018 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1019 Monitor *mon) 1020 { 1021 } 1022 1023 /* 1024 * Allowed core identifiers on a POWER8 Processor Chip : 1025 * 1026 * <EX0 reserved> 1027 * EX1 - Venice only 1028 * EX2 - Venice only 1029 * EX3 - Venice only 1030 * EX4 1031 * EX5 1032 * EX6 1033 * <EX7,8 reserved> <reserved> 1034 * EX9 - Venice only 1035 * EX10 - Venice only 1036 * EX11 - Venice only 1037 * EX12 1038 * EX13 1039 * EX14 1040 * <EX15 reserved> 1041 */ 1042 #define POWER8E_CORE_MASK (0x7070ull) 1043 #define POWER8_CORE_MASK (0x7e7eull) 1044 1045 /* 1046 * POWER9 has 24 cores, ids starting at 0x0 1047 */ 1048 #define POWER9_CORE_MASK (0xffffffffffffffull) 1049 1050 1051 #define POWER10_CORE_MASK (0xffffffffffffffull) 1052 1053 static void pnv_chip_power8_instance_init(Object *obj) 1054 { 1055 PnvChip *chip = PNV_CHIP(obj); 1056 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1057 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1058 int i; 1059 1060 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1061 (Object **)&chip8->xics, 1062 object_property_allow_set_link, 1063 OBJ_PROP_LINK_STRONG, 1064 &error_abort); 1065 1066 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1067 TYPE_PNV8_PSI, &error_abort, NULL); 1068 1069 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1070 TYPE_PNV8_LPC, &error_abort, NULL); 1071 1072 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1073 TYPE_PNV8_OCC, &error_abort, NULL); 1074 1075 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1076 TYPE_PNV8_HOMER, &error_abort, NULL); 1077 1078 for (i = 0; i < pcc->num_phbs; i++) { 1079 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1080 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1081 &error_abort, NULL); 1082 } 1083 1084 /* 1085 * Number of PHBs is the chip default 1086 */ 1087 chip->num_phbs = pcc->num_phbs; 1088 } 1089 1090 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1091 { 1092 PnvChip *chip = PNV_CHIP(chip8); 1093 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1094 int i, j; 1095 char *name; 1096 1097 name = g_strdup_printf("icp-%x", chip->chip_id); 1098 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1099 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1100 g_free(name); 1101 1102 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1103 1104 /* Map the ICP registers for each thread */ 1105 for (i = 0; i < chip->nr_cores; i++) { 1106 PnvCore *pnv_core = chip->cores[i]; 1107 int core_hwid = CPU_CORE(pnv_core)->core_id; 1108 1109 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1110 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1111 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1112 1113 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1114 &icp->mmio); 1115 } 1116 } 1117 } 1118 1119 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1120 { 1121 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1122 PnvChip *chip = PNV_CHIP(dev); 1123 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1124 Pnv8Psi *psi8 = &chip8->psi; 1125 Error *local_err = NULL; 1126 int i; 1127 1128 assert(chip8->xics); 1129 1130 /* XSCOM bridge is first */ 1131 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1132 if (local_err) { 1133 error_propagate(errp, local_err); 1134 return; 1135 } 1136 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1137 1138 pcc->parent_realize(dev, &local_err); 1139 if (local_err) { 1140 error_propagate(errp, local_err); 1141 return; 1142 } 1143 1144 /* Processor Service Interface (PSI) Host Bridge */ 1145 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1146 "bar", &error_fatal); 1147 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1148 ICS_PROP_XICS, &error_abort); 1149 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1150 if (local_err) { 1151 error_propagate(errp, local_err); 1152 return; 1153 } 1154 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1155 &PNV_PSI(psi8)->xscom_regs); 1156 1157 /* Create LPC controller */ 1158 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1159 &error_abort); 1160 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1161 &error_fatal); 1162 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1163 1164 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1165 (uint64_t) PNV_XSCOM_BASE(chip), 1166 PNV_XSCOM_LPC_BASE); 1167 1168 /* 1169 * Interrupt Management Area. This is the memory region holding 1170 * all the Interrupt Control Presenter (ICP) registers 1171 */ 1172 pnv_chip_icp_realize(chip8, &local_err); 1173 if (local_err) { 1174 error_propagate(errp, local_err); 1175 return; 1176 } 1177 1178 /* Create the simplified OCC model */ 1179 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1180 &error_abort); 1181 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1182 if (local_err) { 1183 error_propagate(errp, local_err); 1184 return; 1185 } 1186 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1187 1188 /* OCC SRAM model */ 1189 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1190 &chip8->occ.sram_regs); 1191 1192 /* HOMER */ 1193 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1194 &error_abort); 1195 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1196 &local_err); 1197 if (local_err) { 1198 error_propagate(errp, local_err); 1199 return; 1200 } 1201 /* Homer Xscom region */ 1202 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1203 1204 /* Homer mmio region */ 1205 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1206 &chip8->homer.regs); 1207 1208 /* PHB3 controllers */ 1209 for (i = 0; i < chip->num_phbs; i++) { 1210 PnvPHB3 *phb = &chip8->phbs[i]; 1211 PnvPBCQState *pbcq = &phb->pbcq; 1212 1213 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1214 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1215 &error_fatal); 1216 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1217 if (local_err) { 1218 error_propagate(errp, local_err); 1219 return; 1220 } 1221 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1222 1223 /* Populate the XSCOM address space. */ 1224 pnv_xscom_add_subregion(chip, 1225 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1226 &pbcq->xscom_nest_regs); 1227 pnv_xscom_add_subregion(chip, 1228 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1229 &pbcq->xscom_pci_regs); 1230 pnv_xscom_add_subregion(chip, 1231 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1232 &pbcq->xscom_spci_regs); 1233 } 1234 } 1235 1236 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1237 { 1238 addr &= (PNV_XSCOM_SIZE - 1); 1239 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1240 } 1241 1242 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1243 { 1244 DeviceClass *dc = DEVICE_CLASS(klass); 1245 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1246 1247 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1248 k->cores_mask = POWER8E_CORE_MASK; 1249 k->num_phbs = 3; 1250 k->core_pir = pnv_chip_core_pir_p8; 1251 k->intc_create = pnv_chip_power8_intc_create; 1252 k->intc_reset = pnv_chip_power8_intc_reset; 1253 k->intc_destroy = pnv_chip_power8_intc_destroy; 1254 k->intc_print_info = pnv_chip_power8_intc_print_info; 1255 k->isa_create = pnv_chip_power8_isa_create; 1256 k->dt_populate = pnv_chip_power8_dt_populate; 1257 k->pic_print_info = pnv_chip_power8_pic_print_info; 1258 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1259 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1260 dc->desc = "PowerNV Chip POWER8E"; 1261 1262 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1263 &k->parent_realize); 1264 } 1265 1266 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1267 { 1268 DeviceClass *dc = DEVICE_CLASS(klass); 1269 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1270 1271 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1272 k->cores_mask = POWER8_CORE_MASK; 1273 k->num_phbs = 3; 1274 k->core_pir = pnv_chip_core_pir_p8; 1275 k->intc_create = pnv_chip_power8_intc_create; 1276 k->intc_reset = pnv_chip_power8_intc_reset; 1277 k->intc_destroy = pnv_chip_power8_intc_destroy; 1278 k->intc_print_info = pnv_chip_power8_intc_print_info; 1279 k->isa_create = pnv_chip_power8_isa_create; 1280 k->dt_populate = pnv_chip_power8_dt_populate; 1281 k->pic_print_info = pnv_chip_power8_pic_print_info; 1282 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1283 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1284 dc->desc = "PowerNV Chip POWER8"; 1285 1286 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1287 &k->parent_realize); 1288 } 1289 1290 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1291 { 1292 DeviceClass *dc = DEVICE_CLASS(klass); 1293 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1294 1295 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1296 k->cores_mask = POWER8_CORE_MASK; 1297 k->num_phbs = 3; 1298 k->core_pir = pnv_chip_core_pir_p8; 1299 k->intc_create = pnv_chip_power8_intc_create; 1300 k->intc_reset = pnv_chip_power8_intc_reset; 1301 k->intc_destroy = pnv_chip_power8_intc_destroy; 1302 k->intc_print_info = pnv_chip_power8_intc_print_info; 1303 k->isa_create = pnv_chip_power8nvl_isa_create; 1304 k->dt_populate = pnv_chip_power8_dt_populate; 1305 k->pic_print_info = pnv_chip_power8_pic_print_info; 1306 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1307 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1308 dc->desc = "PowerNV Chip POWER8NVL"; 1309 1310 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1311 &k->parent_realize); 1312 } 1313 1314 static void pnv_chip_power9_instance_init(Object *obj) 1315 { 1316 PnvChip *chip = PNV_CHIP(obj); 1317 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1318 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1319 int i; 1320 1321 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1322 TYPE_PNV_XIVE, &error_abort, NULL); 1323 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1324 "xive-fabric", &error_abort); 1325 1326 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1327 TYPE_PNV9_PSI, &error_abort, NULL); 1328 1329 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1330 TYPE_PNV9_LPC, &error_abort, NULL); 1331 1332 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1333 TYPE_PNV9_OCC, &error_abort, NULL); 1334 1335 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1336 TYPE_PNV9_HOMER, &error_abort, NULL); 1337 1338 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1339 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1340 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1341 &error_abort, NULL); 1342 } 1343 1344 /* 1345 * Number of PHBs is the chip default 1346 */ 1347 chip->num_phbs = pcc->num_phbs; 1348 } 1349 1350 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1351 { 1352 PnvChip *chip = PNV_CHIP(chip9); 1353 int i; 1354 1355 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1356 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1357 1358 for (i = 0; i < chip9->nr_quads; i++) { 1359 char eq_name[32]; 1360 PnvQuad *eq = &chip9->quads[i]; 1361 PnvCore *pnv_core = chip->cores[i * 4]; 1362 int core_id = CPU_CORE(pnv_core)->core_id; 1363 1364 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1365 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1366 TYPE_PNV_QUAD, &error_fatal, NULL); 1367 1368 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1369 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1370 1371 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1372 &eq->xscom_regs); 1373 } 1374 } 1375 1376 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1377 { 1378 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1379 Error *local_err = NULL; 1380 int i, j; 1381 int phb_id = 0; 1382 1383 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1384 PnvPhb4PecState *pec = &chip9->pecs[i]; 1385 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1386 uint32_t pec_nest_base; 1387 uint32_t pec_pci_base; 1388 1389 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1390 /* 1391 * PEC0 -> 1 stack 1392 * PEC1 -> 2 stacks 1393 * PEC2 -> 3 stacks 1394 */ 1395 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1396 &error_fatal); 1397 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1398 &error_fatal); 1399 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1400 "system-memory", &error_abort); 1401 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1402 if (local_err) { 1403 error_propagate(errp, local_err); 1404 return; 1405 } 1406 1407 pec_nest_base = pecc->xscom_nest_base(pec); 1408 pec_pci_base = pecc->xscom_pci_base(pec); 1409 1410 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1411 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1412 1413 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1414 j++, phb_id++) { 1415 PnvPhb4PecStack *stack = &pec->stacks[j]; 1416 Object *obj = OBJECT(&stack->phb); 1417 1418 object_property_set_int(obj, phb_id, "index", &error_fatal); 1419 object_property_set_int(obj, chip->chip_id, "chip-id", 1420 &error_fatal); 1421 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1422 &error_fatal); 1423 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1424 &error_fatal); 1425 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1426 object_property_set_bool(obj, true, "realized", &local_err); 1427 if (local_err) { 1428 error_propagate(errp, local_err); 1429 return; 1430 } 1431 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1432 1433 /* Populate the XSCOM address space. */ 1434 pnv_xscom_add_subregion(chip, 1435 pec_nest_base + 0x40 * (stack->stack_no + 1), 1436 &stack->nest_regs_mr); 1437 pnv_xscom_add_subregion(chip, 1438 pec_pci_base + 0x40 * (stack->stack_no + 1), 1439 &stack->pci_regs_mr); 1440 pnv_xscom_add_subregion(chip, 1441 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1442 0x40 * stack->stack_no, 1443 &stack->phb_regs_mr); 1444 } 1445 } 1446 } 1447 1448 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1449 { 1450 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1451 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1452 PnvChip *chip = PNV_CHIP(dev); 1453 Pnv9Psi *psi9 = &chip9->psi; 1454 Error *local_err = NULL; 1455 1456 /* XSCOM bridge is first */ 1457 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1458 if (local_err) { 1459 error_propagate(errp, local_err); 1460 return; 1461 } 1462 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1463 1464 pcc->parent_realize(dev, &local_err); 1465 if (local_err) { 1466 error_propagate(errp, local_err); 1467 return; 1468 } 1469 1470 pnv_chip_quad_realize(chip9, &local_err); 1471 if (local_err) { 1472 error_propagate(errp, local_err); 1473 return; 1474 } 1475 1476 /* XIVE interrupt controller (POWER9) */ 1477 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1478 "ic-bar", &error_fatal); 1479 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1480 "vc-bar", &error_fatal); 1481 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1482 "pc-bar", &error_fatal); 1483 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1484 "tm-bar", &error_fatal); 1485 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1486 &error_abort); 1487 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1488 &local_err); 1489 if (local_err) { 1490 error_propagate(errp, local_err); 1491 return; 1492 } 1493 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1494 &chip9->xive.xscom_regs); 1495 1496 /* Processor Service Interface (PSI) Host Bridge */ 1497 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1498 "bar", &error_fatal); 1499 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1500 if (local_err) { 1501 error_propagate(errp, local_err); 1502 return; 1503 } 1504 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1505 &PNV_PSI(psi9)->xscom_regs); 1506 1507 /* LPC */ 1508 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1509 &error_abort); 1510 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1511 if (local_err) { 1512 error_propagate(errp, local_err); 1513 return; 1514 } 1515 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1516 &chip9->lpc.xscom_regs); 1517 1518 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1519 (uint64_t) PNV9_LPCM_BASE(chip)); 1520 1521 /* Create the simplified OCC model */ 1522 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1523 &error_abort); 1524 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1525 if (local_err) { 1526 error_propagate(errp, local_err); 1527 return; 1528 } 1529 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1530 1531 /* OCC SRAM model */ 1532 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1533 &chip9->occ.sram_regs); 1534 1535 /* HOMER */ 1536 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1537 &error_abort); 1538 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1539 &local_err); 1540 if (local_err) { 1541 error_propagate(errp, local_err); 1542 return; 1543 } 1544 /* Homer Xscom region */ 1545 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1546 1547 /* Homer mmio region */ 1548 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1549 &chip9->homer.regs); 1550 1551 /* PHBs */ 1552 pnv_chip_power9_phb_realize(chip, &local_err); 1553 if (local_err) { 1554 error_propagate(errp, local_err); 1555 return; 1556 } 1557 } 1558 1559 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1560 { 1561 addr &= (PNV9_XSCOM_SIZE - 1); 1562 return addr >> 3; 1563 } 1564 1565 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1566 { 1567 DeviceClass *dc = DEVICE_CLASS(klass); 1568 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1569 1570 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1571 k->cores_mask = POWER9_CORE_MASK; 1572 k->core_pir = pnv_chip_core_pir_p9; 1573 k->intc_create = pnv_chip_power9_intc_create; 1574 k->intc_reset = pnv_chip_power9_intc_reset; 1575 k->intc_destroy = pnv_chip_power9_intc_destroy; 1576 k->intc_print_info = pnv_chip_power9_intc_print_info; 1577 k->isa_create = pnv_chip_power9_isa_create; 1578 k->dt_populate = pnv_chip_power9_dt_populate; 1579 k->pic_print_info = pnv_chip_power9_pic_print_info; 1580 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1581 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1582 dc->desc = "PowerNV Chip POWER9"; 1583 k->num_phbs = 6; 1584 1585 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1586 &k->parent_realize); 1587 } 1588 1589 static void pnv_chip_power10_instance_init(Object *obj) 1590 { 1591 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1592 1593 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1594 TYPE_PNV10_PSI, &error_abort, NULL); 1595 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1596 TYPE_PNV10_LPC, &error_abort, NULL); 1597 } 1598 1599 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1600 { 1601 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1602 PnvChip *chip = PNV_CHIP(dev); 1603 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1604 Error *local_err = NULL; 1605 1606 /* XSCOM bridge is first */ 1607 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1608 if (local_err) { 1609 error_propagate(errp, local_err); 1610 return; 1611 } 1612 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1613 1614 pcc->parent_realize(dev, &local_err); 1615 if (local_err) { 1616 error_propagate(errp, local_err); 1617 return; 1618 } 1619 1620 /* Processor Service Interface (PSI) Host Bridge */ 1621 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1622 "bar", &error_fatal); 1623 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1624 &local_err); 1625 if (local_err) { 1626 error_propagate(errp, local_err); 1627 return; 1628 } 1629 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1630 &PNV_PSI(&chip10->psi)->xscom_regs); 1631 1632 /* LPC */ 1633 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1634 &error_abort); 1635 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1636 &local_err); 1637 if (local_err) { 1638 error_propagate(errp, local_err); 1639 return; 1640 } 1641 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1642 &chip10->lpc.xscom_regs); 1643 1644 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1645 (uint64_t) PNV10_LPCM_BASE(chip)); 1646 } 1647 1648 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1649 { 1650 addr &= (PNV10_XSCOM_SIZE - 1); 1651 return addr >> 3; 1652 } 1653 1654 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1655 { 1656 DeviceClass *dc = DEVICE_CLASS(klass); 1657 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1658 1659 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1660 k->cores_mask = POWER10_CORE_MASK; 1661 k->core_pir = pnv_chip_core_pir_p10; 1662 k->intc_create = pnv_chip_power10_intc_create; 1663 k->intc_reset = pnv_chip_power10_intc_reset; 1664 k->intc_destroy = pnv_chip_power10_intc_destroy; 1665 k->intc_print_info = pnv_chip_power10_intc_print_info; 1666 k->isa_create = pnv_chip_power10_isa_create; 1667 k->dt_populate = pnv_chip_power10_dt_populate; 1668 k->pic_print_info = pnv_chip_power10_pic_print_info; 1669 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1670 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1671 dc->desc = "PowerNV Chip POWER10"; 1672 1673 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1674 &k->parent_realize); 1675 } 1676 1677 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1678 { 1679 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1680 int cores_max; 1681 1682 /* 1683 * No custom mask for this chip, let's use the default one from * 1684 * the chip class 1685 */ 1686 if (!chip->cores_mask) { 1687 chip->cores_mask = pcc->cores_mask; 1688 } 1689 1690 /* filter alien core ids ! some are reserved */ 1691 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1692 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1693 chip->cores_mask); 1694 return; 1695 } 1696 chip->cores_mask &= pcc->cores_mask; 1697 1698 /* now that we have a sane layout, let check the number of cores */ 1699 cores_max = ctpop64(chip->cores_mask); 1700 if (chip->nr_cores > cores_max) { 1701 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1702 cores_max); 1703 return; 1704 } 1705 } 1706 1707 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1708 { 1709 Error *error = NULL; 1710 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1711 const char *typename = pnv_chip_core_typename(chip); 1712 int i, core_hwid; 1713 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1714 1715 if (!object_class_by_name(typename)) { 1716 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1717 return; 1718 } 1719 1720 /* Cores */ 1721 pnv_chip_core_sanitize(chip, &error); 1722 if (error) { 1723 error_propagate(errp, error); 1724 return; 1725 } 1726 1727 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1728 1729 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1730 && (i < chip->nr_cores); core_hwid++) { 1731 char core_name[32]; 1732 PnvCore *pnv_core; 1733 uint64_t xscom_core_base; 1734 1735 if (!(chip->cores_mask & (1ull << core_hwid))) { 1736 continue; 1737 } 1738 1739 pnv_core = PNV_CORE(object_new(typename)); 1740 1741 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1742 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1743 &error_abort); 1744 chip->cores[i] = pnv_core; 1745 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1746 "nr-threads", &error_fatal); 1747 object_property_set_int(OBJECT(pnv_core), core_hwid, 1748 CPU_CORE_PROP_CORE_ID, &error_fatal); 1749 object_property_set_int(OBJECT(pnv_core), 1750 pcc->core_pir(chip, core_hwid), 1751 "pir", &error_fatal); 1752 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1753 "hrmor", &error_fatal); 1754 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1755 &error_abort); 1756 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1757 &error_fatal); 1758 1759 /* Each core has an XSCOM MMIO region */ 1760 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1761 1762 pnv_xscom_add_subregion(chip, xscom_core_base, 1763 &pnv_core->xscom_regs); 1764 i++; 1765 } 1766 } 1767 1768 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1769 { 1770 PnvChip *chip = PNV_CHIP(dev); 1771 Error *error = NULL; 1772 1773 /* Cores */ 1774 pnv_chip_core_realize(chip, &error); 1775 if (error) { 1776 error_propagate(errp, error); 1777 return; 1778 } 1779 } 1780 1781 static Property pnv_chip_properties[] = { 1782 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1783 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1784 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1785 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1786 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1787 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1788 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1789 DEFINE_PROP_END_OF_LIST(), 1790 }; 1791 1792 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1793 { 1794 DeviceClass *dc = DEVICE_CLASS(klass); 1795 1796 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1797 dc->realize = pnv_chip_realize; 1798 device_class_set_props(dc, pnv_chip_properties); 1799 dc->desc = "PowerNV Chip"; 1800 } 1801 1802 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1803 { 1804 int i, j; 1805 1806 for (i = 0; i < chip->nr_cores; i++) { 1807 PnvCore *pc = chip->cores[i]; 1808 CPUCore *cc = CPU_CORE(pc); 1809 1810 for (j = 0; j < cc->nr_threads; j++) { 1811 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1812 return pc->threads[j]; 1813 } 1814 } 1815 } 1816 return NULL; 1817 } 1818 1819 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1820 { 1821 PnvMachineState *pnv = PNV_MACHINE(xi); 1822 int i, j; 1823 1824 for (i = 0; i < pnv->num_chips; i++) { 1825 PnvChip *chip = pnv->chips[i]; 1826 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1827 1828 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1829 return &chip8->psi.ics; 1830 } 1831 for (j = 0; j < chip->num_phbs; j++) { 1832 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1833 return &chip8->phbs[j].lsis; 1834 } 1835 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1836 return ICS(&chip8->phbs[j].msis); 1837 } 1838 } 1839 } 1840 return NULL; 1841 } 1842 1843 static void pnv_ics_resend(XICSFabric *xi) 1844 { 1845 PnvMachineState *pnv = PNV_MACHINE(xi); 1846 int i, j; 1847 1848 for (i = 0; i < pnv->num_chips; i++) { 1849 PnvChip *chip = pnv->chips[i]; 1850 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1851 1852 ics_resend(&chip8->psi.ics); 1853 for (j = 0; j < chip->num_phbs; j++) { 1854 ics_resend(&chip8->phbs[j].lsis); 1855 ics_resend(ICS(&chip8->phbs[j].msis)); 1856 } 1857 } 1858 } 1859 1860 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1861 { 1862 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1863 1864 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1865 } 1866 1867 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1868 Monitor *mon) 1869 { 1870 PnvMachineState *pnv = PNV_MACHINE(obj); 1871 int i; 1872 CPUState *cs; 1873 1874 CPU_FOREACH(cs) { 1875 PowerPCCPU *cpu = POWERPC_CPU(cs); 1876 1877 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1878 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1879 mon); 1880 } 1881 1882 for (i = 0; i < pnv->num_chips; i++) { 1883 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1884 } 1885 } 1886 1887 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1888 uint8_t nvt_blk, uint32_t nvt_idx, 1889 bool cam_ignore, uint8_t priority, 1890 uint32_t logic_serv, 1891 XiveTCTXMatch *match) 1892 { 1893 PnvMachineState *pnv = PNV_MACHINE(xfb); 1894 int total_count = 0; 1895 int i; 1896 1897 for (i = 0; i < pnv->num_chips; i++) { 1898 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1899 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1900 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1901 int count; 1902 1903 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1904 priority, logic_serv, match); 1905 1906 if (count < 0) { 1907 return count; 1908 } 1909 1910 total_count += count; 1911 } 1912 1913 return total_count; 1914 } 1915 1916 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1917 { 1918 MachineClass *mc = MACHINE_CLASS(oc); 1919 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1920 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1921 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1922 1923 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1924 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1925 1926 xic->icp_get = pnv_icp_get; 1927 xic->ics_get = pnv_ics_get; 1928 xic->ics_resend = pnv_ics_resend; 1929 1930 pmc->compat = compat; 1931 pmc->compat_size = sizeof(compat); 1932 } 1933 1934 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1935 { 1936 MachineClass *mc = MACHINE_CLASS(oc); 1937 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1938 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1939 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1940 1941 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1942 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1943 xfc->match_nvt = pnv_match_nvt; 1944 1945 mc->alias = "powernv"; 1946 1947 pmc->compat = compat; 1948 pmc->compat_size = sizeof(compat); 1949 pmc->dt_power_mgt = pnv_dt_power_mgt; 1950 } 1951 1952 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1953 { 1954 MachineClass *mc = MACHINE_CLASS(oc); 1955 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1956 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1957 1958 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1959 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1960 1961 pmc->compat = compat; 1962 pmc->compat_size = sizeof(compat); 1963 pmc->dt_power_mgt = pnv_dt_power_mgt; 1964 } 1965 1966 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1967 { 1968 PnvMachineState *pnv = PNV_MACHINE(obj); 1969 1970 return !!pnv->fw_load_addr; 1971 } 1972 1973 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1974 { 1975 PnvMachineState *pnv = PNV_MACHINE(obj); 1976 1977 if (value) { 1978 pnv->fw_load_addr = 0x8000000; 1979 } 1980 } 1981 1982 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1983 { 1984 PowerPCCPU *cpu = POWERPC_CPU(cs); 1985 CPUPPCState *env = &cpu->env; 1986 1987 cpu_synchronize_state(cs); 1988 ppc_cpu_do_system_reset(cs); 1989 /* 1990 * SRR1[42:45] is set to 0100 which the ISA defines as implementation 1991 * dependent. POWER processors use this for xscom triggered interrupts, 1992 * which come from the BMC or NMI IPIs. 1993 */ 1994 env->spr[SPR_SRR1] |= PPC_BIT(43); 1995 } 1996 1997 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1998 { 1999 CPUState *cs; 2000 2001 CPU_FOREACH(cs) { 2002 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2003 } 2004 } 2005 2006 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2007 { 2008 MachineClass *mc = MACHINE_CLASS(oc); 2009 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2010 NMIClass *nc = NMI_CLASS(oc); 2011 2012 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2013 mc->init = pnv_init; 2014 mc->reset = pnv_reset; 2015 mc->max_cpus = MAX_CPUS; 2016 /* Pnv provides a AHCI device for storage */ 2017 mc->block_default_type = IF_IDE; 2018 mc->no_parallel = 1; 2019 mc->default_boot_order = NULL; 2020 /* 2021 * RAM defaults to less than 2048 for 32-bit hosts, and large 2022 * enough to fit the maximum initrd size at it's load address 2023 */ 2024 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 2025 mc->default_ram_id = "pnv.ram"; 2026 ispc->print_info = pnv_pic_print_info; 2027 nc->nmi_monitor_handler = pnv_nmi; 2028 2029 object_class_property_add_bool(oc, "hb-mode", 2030 pnv_machine_get_hb, pnv_machine_set_hb, 2031 &error_abort); 2032 object_class_property_set_description(oc, "hb-mode", 2033 "Use a hostboot like boot loader", 2034 NULL); 2035 } 2036 2037 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2038 { \ 2039 .name = type, \ 2040 .class_init = class_initfn, \ 2041 .parent = TYPE_PNV8_CHIP, \ 2042 } 2043 2044 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2045 { \ 2046 .name = type, \ 2047 .class_init = class_initfn, \ 2048 .parent = TYPE_PNV9_CHIP, \ 2049 } 2050 2051 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2052 { \ 2053 .name = type, \ 2054 .class_init = class_initfn, \ 2055 .parent = TYPE_PNV10_CHIP, \ 2056 } 2057 2058 static const TypeInfo types[] = { 2059 { 2060 .name = MACHINE_TYPE_NAME("powernv10"), 2061 .parent = TYPE_PNV_MACHINE, 2062 .class_init = pnv_machine_power10_class_init, 2063 }, 2064 { 2065 .name = MACHINE_TYPE_NAME("powernv9"), 2066 .parent = TYPE_PNV_MACHINE, 2067 .class_init = pnv_machine_power9_class_init, 2068 .interfaces = (InterfaceInfo[]) { 2069 { TYPE_XIVE_FABRIC }, 2070 { }, 2071 }, 2072 }, 2073 { 2074 .name = MACHINE_TYPE_NAME("powernv8"), 2075 .parent = TYPE_PNV_MACHINE, 2076 .class_init = pnv_machine_power8_class_init, 2077 .interfaces = (InterfaceInfo[]) { 2078 { TYPE_XICS_FABRIC }, 2079 { }, 2080 }, 2081 }, 2082 { 2083 .name = TYPE_PNV_MACHINE, 2084 .parent = TYPE_MACHINE, 2085 .abstract = true, 2086 .instance_size = sizeof(PnvMachineState), 2087 .class_init = pnv_machine_class_init, 2088 .class_size = sizeof(PnvMachineClass), 2089 .interfaces = (InterfaceInfo[]) { 2090 { TYPE_INTERRUPT_STATS_PROVIDER }, 2091 { TYPE_NMI }, 2092 { }, 2093 }, 2094 }, 2095 { 2096 .name = TYPE_PNV_CHIP, 2097 .parent = TYPE_SYS_BUS_DEVICE, 2098 .class_init = pnv_chip_class_init, 2099 .instance_size = sizeof(PnvChip), 2100 .class_size = sizeof(PnvChipClass), 2101 .abstract = true, 2102 }, 2103 2104 /* 2105 * P10 chip and variants 2106 */ 2107 { 2108 .name = TYPE_PNV10_CHIP, 2109 .parent = TYPE_PNV_CHIP, 2110 .instance_init = pnv_chip_power10_instance_init, 2111 .instance_size = sizeof(Pnv10Chip), 2112 }, 2113 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2114 2115 /* 2116 * P9 chip and variants 2117 */ 2118 { 2119 .name = TYPE_PNV9_CHIP, 2120 .parent = TYPE_PNV_CHIP, 2121 .instance_init = pnv_chip_power9_instance_init, 2122 .instance_size = sizeof(Pnv9Chip), 2123 }, 2124 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2125 2126 /* 2127 * P8 chip and variants 2128 */ 2129 { 2130 .name = TYPE_PNV8_CHIP, 2131 .parent = TYPE_PNV_CHIP, 2132 .instance_init = pnv_chip_power8_instance_init, 2133 .instance_size = sizeof(Pnv8Chip), 2134 }, 2135 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2136 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2137 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2138 pnv_chip_power8nvl_class_init), 2139 }; 2140 2141 DEFINE_TYPES(types) 2142