1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/sysemu.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_core.h" 29 #include "hw/ppc/pnv_xscom.h" 30 #include "hw/ppc/xics.h" 31 32 static const char *pnv_core_cpu_typename(PnvCore *pc) 33 { 34 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 35 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 36 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 37 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 38 g_free(s); 39 return cpu_type; 40 } 41 42 static void pnv_cpu_reset(void *opaque) 43 { 44 PowerPCCPU *cpu = opaque; 45 CPUState *cs = CPU(cpu); 46 CPUPPCState *env = &cpu->env; 47 48 cpu_reset(cs); 49 50 /* 51 * the skiboot firmware elects a primary thread to initialize the 52 * system and it can be any. 53 */ 54 env->gpr[3] = PNV_FDT_ADDR; 55 env->nip = 0x10; 56 env->msr |= MSR_HVB; /* Hypervisor mode */ 57 } 58 59 /* 60 * These values are read by the PowerNV HW monitors under Linux 61 */ 62 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 63 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 64 65 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 66 unsigned int width) 67 { 68 uint32_t offset = addr >> 3; 69 uint64_t val = 0; 70 71 /* The result should be 38 C */ 72 switch (offset) { 73 case PNV_XSCOM_EX_DTS_RESULT0: 74 val = 0x26f024f023f0000ull; 75 break; 76 case PNV_XSCOM_EX_DTS_RESULT1: 77 val = 0x24f000000000000ull; 78 break; 79 default: 80 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 81 addr); 82 } 83 84 return val; 85 } 86 87 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 88 unsigned int width) 89 { 90 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 91 addr); 92 } 93 94 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 95 .read = pnv_core_power8_xscom_read, 96 .write = pnv_core_power8_xscom_write, 97 .valid.min_access_size = 8, 98 .valid.max_access_size = 8, 99 .impl.min_access_size = 8, 100 .impl.max_access_size = 8, 101 .endianness = DEVICE_BIG_ENDIAN, 102 }; 103 104 105 /* 106 * POWER9 core controls 107 */ 108 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 109 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 110 111 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 112 unsigned int width) 113 { 114 uint32_t offset = addr >> 3; 115 uint64_t val = 0; 116 117 /* The result should be 38 C */ 118 switch (offset) { 119 case PNV_XSCOM_EX_DTS_RESULT0: 120 val = 0x26f024f023f0000ull; 121 break; 122 case PNV_XSCOM_EX_DTS_RESULT1: 123 val = 0x24f000000000000ull; 124 break; 125 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 126 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 127 val = 0x0; 128 break; 129 default: 130 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 131 addr); 132 } 133 134 return val; 135 } 136 137 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 138 unsigned int width) 139 { 140 uint32_t offset = addr >> 3; 141 142 switch (offset) { 143 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 144 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 145 break; 146 default: 147 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 148 addr); 149 } 150 } 151 152 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 153 .read = pnv_core_power9_xscom_read, 154 .write = pnv_core_power9_xscom_write, 155 .valid.min_access_size = 8, 156 .valid.max_access_size = 8, 157 .impl.min_access_size = 8, 158 .impl.max_access_size = 8, 159 .endianness = DEVICE_BIG_ENDIAN, 160 }; 161 162 static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) 163 { 164 CPUPPCState *env = &cpu->env; 165 int core_pir; 166 int thread_index = 0; /* TODO: TCG supports only one thread */ 167 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 168 Error *local_err = NULL; 169 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 170 171 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 172 if (local_err) { 173 error_propagate(errp, local_err); 174 return; 175 } 176 177 pcc->intc_create(chip, cpu, &local_err); 178 if (local_err) { 179 error_propagate(errp, local_err); 180 return; 181 } 182 183 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); 184 185 /* 186 * The PIR of a thread is the core PIR + the thread index. We will 187 * need to find a way to get the thread index when TCG supports 188 * more than 1. We could use the object name ? 189 */ 190 pir->default_value = core_pir + thread_index; 191 192 /* Set time-base frequency to 512 MHz */ 193 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 194 195 qemu_register_reset(pnv_cpu_reset, cpu); 196 } 197 198 static void pnv_core_realize(DeviceState *dev, Error **errp) 199 { 200 PnvCore *pc = PNV_CORE(OBJECT(dev)); 201 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 202 CPUCore *cc = CPU_CORE(OBJECT(dev)); 203 const char *typename = pnv_core_cpu_typename(pc); 204 Error *local_err = NULL; 205 void *obj; 206 int i, j; 207 char name[32]; 208 Object *chip; 209 210 chip = object_property_get_link(OBJECT(dev), "chip", &local_err); 211 if (!chip) { 212 error_propagate_prepend(errp, local_err, 213 "required link 'chip' not found: "); 214 return; 215 } 216 217 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 218 for (i = 0; i < cc->nr_threads; i++) { 219 PowerPCCPU *cpu; 220 221 obj = object_new(typename); 222 cpu = POWERPC_CPU(obj); 223 224 pc->threads[i] = POWERPC_CPU(obj); 225 226 snprintf(name, sizeof(name), "thread[%d]", i); 227 object_property_add_child(OBJECT(pc), name, obj, &error_abort); 228 object_property_add_alias(obj, "core-pir", OBJECT(pc), 229 "pir", &error_abort); 230 231 cpu->machine_data = g_new0(PnvCPUState, 1); 232 233 object_unref(obj); 234 } 235 236 for (j = 0; j < cc->nr_threads; j++) { 237 pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err); 238 if (local_err) { 239 goto err; 240 } 241 } 242 243 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 244 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 245 pc, name, PNV_XSCOM_EX_SIZE); 246 return; 247 248 err: 249 while (--i >= 0) { 250 obj = OBJECT(pc->threads[i]); 251 object_unparent(obj); 252 } 253 g_free(pc->threads); 254 error_propagate(errp, local_err); 255 } 256 257 static void pnv_unrealize_vcpu(PowerPCCPU *cpu) 258 { 259 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 260 261 qemu_unregister_reset(pnv_cpu_reset, cpu); 262 object_unparent(OBJECT(pnv_cpu_state(cpu)->intc)); 263 cpu_remove_sync(CPU(cpu)); 264 cpu->machine_data = NULL; 265 g_free(pnv_cpu); 266 object_unparent(OBJECT(cpu)); 267 } 268 269 static void pnv_core_unrealize(DeviceState *dev, Error **errp) 270 { 271 PnvCore *pc = PNV_CORE(dev); 272 CPUCore *cc = CPU_CORE(dev); 273 int i; 274 275 for (i = 0; i < cc->nr_threads; i++) { 276 pnv_unrealize_vcpu(pc->threads[i]); 277 } 278 g_free(pc->threads); 279 } 280 281 static Property pnv_core_properties[] = { 282 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 283 DEFINE_PROP_END_OF_LIST(), 284 }; 285 286 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 287 { 288 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 289 290 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 291 } 292 293 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 294 { 295 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 296 297 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 298 } 299 300 static void pnv_core_class_init(ObjectClass *oc, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(oc); 303 304 dc->realize = pnv_core_realize; 305 dc->unrealize = pnv_core_unrealize; 306 dc->props = pnv_core_properties; 307 } 308 309 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 310 { \ 311 .parent = TYPE_PNV_CORE, \ 312 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 313 .class_init = pnv_core_##family##_class_init, \ 314 } 315 316 static const TypeInfo pnv_core_infos[] = { 317 { 318 .name = TYPE_PNV_CORE, 319 .parent = TYPE_CPU_CORE, 320 .instance_size = sizeof(PnvCore), 321 .class_size = sizeof(PnvCoreClass), 322 .class_init = pnv_core_class_init, 323 .abstract = true, 324 }, 325 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 326 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 327 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 328 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), 329 }; 330 331 DEFINE_TYPES(pnv_core_infos) 332 333 /* 334 * POWER9 Quads 335 */ 336 337 #define P9X_EX_NCU_SPEC_BAR 0x11010 338 339 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, 340 unsigned int width) 341 { 342 uint32_t offset = addr >> 3; 343 uint64_t val = -1; 344 345 switch (offset) { 346 case P9X_EX_NCU_SPEC_BAR: 347 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 348 val = 0; 349 break; 350 default: 351 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 352 offset); 353 } 354 355 return val; 356 } 357 358 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, 359 unsigned int width) 360 { 361 uint32_t offset = addr >> 3; 362 363 switch (offset) { 364 case P9X_EX_NCU_SPEC_BAR: 365 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 366 break; 367 default: 368 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 369 offset); 370 } 371 } 372 373 static const MemoryRegionOps pnv_quad_xscom_ops = { 374 .read = pnv_quad_xscom_read, 375 .write = pnv_quad_xscom_write, 376 .valid.min_access_size = 8, 377 .valid.max_access_size = 8, 378 .impl.min_access_size = 8, 379 .impl.max_access_size = 8, 380 .endianness = DEVICE_BIG_ENDIAN, 381 }; 382 383 static void pnv_quad_realize(DeviceState *dev, Error **errp) 384 { 385 PnvQuad *eq = PNV_QUAD(dev); 386 char name[32]; 387 388 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); 389 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, 390 eq, name, PNV9_XSCOM_EQ_SIZE); 391 } 392 393 static Property pnv_quad_properties[] = { 394 DEFINE_PROP_UINT32("id", PnvQuad, id, 0), 395 DEFINE_PROP_END_OF_LIST(), 396 }; 397 398 static void pnv_quad_class_init(ObjectClass *oc, void *data) 399 { 400 DeviceClass *dc = DEVICE_CLASS(oc); 401 402 dc->realize = pnv_quad_realize; 403 dc->props = pnv_quad_properties; 404 } 405 406 static const TypeInfo pnv_quad_info = { 407 .name = TYPE_PNV_QUAD, 408 .parent = TYPE_DEVICE, 409 .instance_size = sizeof(PnvQuad), 410 .class_init = pnv_quad_class_init, 411 }; 412 413 static void pnv_core_register_types(void) 414 { 415 type_register_static(&pnv_quad_info); 416 } 417 418 type_init(pnv_core_register_types) 419