xref: /qemu/hw/ppc/pnv_pnor.c (revision bdf200a5) 
1 /*
2  * QEMU PowerNV PNOR simple model
3  *
4  * Copyright (c) 2015-2019, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "qemu/error-report.h"
13 #include "qemu/log.h"
14 #include "sysemu/block-backend.h"
15 #include "sysemu/blockdev.h"
16 #include "hw/loader.h"
17 #include "hw/ppc/pnv_pnor.h"
18 #include "hw/qdev-properties.h"
19 
20 static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size)
21 {
22     PnvPnor *s = PNV_PNOR(opaque);
23     uint64_t ret = 0;
24     int i;
25 
26     for (i = 0; i < size; i++) {
27         ret |= (uint64_t) s->storage[addr + i] << (8 * (size - i - 1));
28     }
29 
30     return ret;
31 }
32 
33 static void pnv_pnor_update(PnvPnor *s, int offset, int size)
34 {
35     int offset_end;
36 
37     if (s->blk) {
38         return;
39     }
40 
41     offset_end = offset + size;
42     offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
43     offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
44 
45     blk_pwrite(s->blk, offset, s->storage + offset,
46                offset_end - offset, 0);
47 }
48 
49 static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data,
50                            unsigned size)
51 {
52     PnvPnor *s = PNV_PNOR(opaque);
53     int i;
54 
55     for (i = 0; i < size; i++) {
56         s->storage[addr + i] = (data >> (8 * (size - i - 1))) & 0xFF;
57     }
58     pnv_pnor_update(s, addr, size);
59 }
60 
61 /*
62  * TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash
63  * is BIG.
64  */
65 static const MemoryRegionOps pnv_pnor_ops = {
66     .read = pnv_pnor_read,
67     .write = pnv_pnor_write,
68     .endianness = DEVICE_BIG_ENDIAN,
69     .valid = {
70         .min_access_size = 1,
71         .max_access_size = 4,
72     },
73 };
74 
75 static void pnv_pnor_realize(DeviceState *dev, Error **errp)
76 {
77     PnvPnor *s = PNV_PNOR(dev);
78     int ret;
79 
80     if (s->blk) {
81         uint64_t perm = BLK_PERM_CONSISTENT_READ |
82                         (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
83         ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
84         if (ret < 0) {
85             return;
86         }
87 
88         s->size = blk_getlength(s->blk);
89         if (s->size <= 0) {
90             error_setg(errp, "failed to get flash size");
91             return;
92         }
93 
94         s->storage = blk_blockalign(s->blk, s->size);
95 
96         if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
97             error_setg(errp, "failed to read the initial flash content");
98             return;
99         }
100     } else {
101         s->storage = blk_blockalign(NULL, s->size);
102         memset(s->storage, 0xFF, s->size);
103     }
104 
105     memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
106                           TYPE_PNV_PNOR, s->size);
107 }
108 
109 static Property pnv_pnor_properties[] = {
110     DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20),
111     DEFINE_PROP_DRIVE("drive", PnvPnor, blk),
112     DEFINE_PROP_END_OF_LIST(),
113 };
114 
115 static void pnv_pnor_class_init(ObjectClass *klass, void *data)
116 {
117     DeviceClass *dc = DEVICE_CLASS(klass);
118 
119     dc->realize = pnv_pnor_realize;
120     dc->props = pnv_pnor_properties;
121 }
122 
123 static const TypeInfo pnv_pnor_info = {
124     .name          = TYPE_PNV_PNOR,
125     .parent        = TYPE_SYS_BUS_DEVICE,
126     .instance_size = sizeof(PnvPnor),
127     .class_init    = pnv_pnor_class_init,
128 };
129 
130 static void pnv_pnor_register_types(void)
131 {
132     type_register_static(&pnv_pnor_info);
133 }
134 
135 type_init(pnv_pnor_register_types)
136