153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * QEMU generic PowerPC hardware System Emulator 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2003-2007 Jocelyn Mayer 553018216SPaolo Bonzini * 653018216SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 753018216SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 853018216SPaolo Bonzini * in the Software without restriction, including without limitation the rights 953018216SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1053018216SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1153018216SPaolo Bonzini * furnished to do so, subject to the following conditions: 1253018216SPaolo Bonzini * 1353018216SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1453018216SPaolo Bonzini * all copies or substantial portions of the Software. 1553018216SPaolo Bonzini * 1653018216SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1753018216SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1853018216SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1953018216SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2053018216SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2153018216SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2253018216SPaolo Bonzini * THE SOFTWARE. 2353018216SPaolo Bonzini */ 2464552b6bSMarkus Armbruster 250d75590dSPeter Maydell #include "qemu/osdep.h" 264771d756SPaolo Bonzini #include "cpu.h" 2764552b6bSMarkus Armbruster #include "hw/irq.h" 280d09e41aSPaolo Bonzini #include "hw/ppc/ppc.h" 292b927571SAndreas Färber #include "hw/ppc/ppc_e500.h" 3053018216SPaolo Bonzini #include "qemu/timer.h" 310ce470cdSAlexey Kardashevskiy #include "sysemu/cpus.h" 3253018216SPaolo Bonzini #include "qemu/log.h" 33db725815SMarkus Armbruster #include "qemu/main-loop.h" 3498a8b524SAlexey Kardashevskiy #include "qemu/error-report.h" 3553018216SPaolo Bonzini #include "sysemu/kvm.h" 3654d31236SMarkus Armbruster #include "sysemu/runstate.h" 3753018216SPaolo Bonzini #include "kvm_ppc.h" 38d6454270SMarkus Armbruster #include "migration/vmstate.h" 3998a8b524SAlexey Kardashevskiy #include "trace.h" 4053018216SPaolo Bonzini 4153018216SPaolo Bonzini //#define PPC_DEBUG_IRQ 4253018216SPaolo Bonzini //#define PPC_DEBUG_TB 4353018216SPaolo Bonzini 4453018216SPaolo Bonzini #ifdef PPC_DEBUG_IRQ 4553018216SPaolo Bonzini # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 4653018216SPaolo Bonzini #else 4753018216SPaolo Bonzini # define LOG_IRQ(...) do { } while (0) 4853018216SPaolo Bonzini #endif 4953018216SPaolo Bonzini 5053018216SPaolo Bonzini 5153018216SPaolo Bonzini #ifdef PPC_DEBUG_TB 5253018216SPaolo Bonzini # define LOG_TB(...) qemu_log(__VA_ARGS__) 5353018216SPaolo Bonzini #else 5453018216SPaolo Bonzini # define LOG_TB(...) do { } while (0) 5553018216SPaolo Bonzini #endif 5653018216SPaolo Bonzini 5753018216SPaolo Bonzini static void cpu_ppc_tb_stop (CPUPPCState *env); 5853018216SPaolo Bonzini static void cpu_ppc_tb_start (CPUPPCState *env); 5953018216SPaolo Bonzini 6053018216SPaolo Bonzini void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 6153018216SPaolo Bonzini { 62d8ed887bSAndreas Färber CPUState *cs = CPU(cpu); 6353018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 648d04fb55SJan Kiszka unsigned int old_pending; 658d04fb55SJan Kiszka bool locked = false; 668d04fb55SJan Kiszka 678d04fb55SJan Kiszka /* We may already have the BQL if coming from the reset path */ 688d04fb55SJan Kiszka if (!qemu_mutex_iothread_locked()) { 698d04fb55SJan Kiszka locked = true; 708d04fb55SJan Kiszka qemu_mutex_lock_iothread(); 718d04fb55SJan Kiszka } 728d04fb55SJan Kiszka 738d04fb55SJan Kiszka old_pending = env->pending_interrupts; 7453018216SPaolo Bonzini 7553018216SPaolo Bonzini if (level) { 7653018216SPaolo Bonzini env->pending_interrupts |= 1 << n_IRQ; 77c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_HARD); 7853018216SPaolo Bonzini } else { 7953018216SPaolo Bonzini env->pending_interrupts &= ~(1 << n_IRQ); 80d8ed887bSAndreas Färber if (env->pending_interrupts == 0) { 81d8ed887bSAndreas Färber cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 82d8ed887bSAndreas Färber } 8353018216SPaolo Bonzini } 8453018216SPaolo Bonzini 8553018216SPaolo Bonzini if (old_pending != env->pending_interrupts) { 8653018216SPaolo Bonzini kvmppc_set_interrupt(cpu, n_IRQ, level); 8753018216SPaolo Bonzini } 8853018216SPaolo Bonzini 898d04fb55SJan Kiszka 9053018216SPaolo Bonzini LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 9153018216SPaolo Bonzini "req %08x\n", __func__, env, n_IRQ, level, 92259186a7SAndreas Färber env->pending_interrupts, CPU(cpu)->interrupt_request); 938d04fb55SJan Kiszka 948d04fb55SJan Kiszka if (locked) { 958d04fb55SJan Kiszka qemu_mutex_unlock_iothread(); 968d04fb55SJan Kiszka } 9753018216SPaolo Bonzini } 9853018216SPaolo Bonzini 9953018216SPaolo Bonzini /* PowerPC 6xx / 7xx internal IRQ controller */ 10053018216SPaolo Bonzini static void ppc6xx_set_irq(void *opaque, int pin, int level) 10153018216SPaolo Bonzini { 10253018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 10353018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 10453018216SPaolo Bonzini int cur_level; 10553018216SPaolo Bonzini 10653018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 10753018216SPaolo Bonzini env, pin, level); 10853018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 10953018216SPaolo Bonzini /* Don't generate spurious events */ 11053018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 111259186a7SAndreas Färber CPUState *cs = CPU(cpu); 112259186a7SAndreas Färber 11353018216SPaolo Bonzini switch (pin) { 11453018216SPaolo Bonzini case PPC6xx_INPUT_TBEN: 11553018216SPaolo Bonzini /* Level sensitive - active high */ 11653018216SPaolo Bonzini LOG_IRQ("%s: %s the time base\n", 11753018216SPaolo Bonzini __func__, level ? "start" : "stop"); 11853018216SPaolo Bonzini if (level) { 11953018216SPaolo Bonzini cpu_ppc_tb_start(env); 12053018216SPaolo Bonzini } else { 12153018216SPaolo Bonzini cpu_ppc_tb_stop(env); 12253018216SPaolo Bonzini } 12353018216SPaolo Bonzini case PPC6xx_INPUT_INT: 12453018216SPaolo Bonzini /* Level sensitive - active high */ 12553018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 12653018216SPaolo Bonzini __func__, level); 12753018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 12853018216SPaolo Bonzini break; 12953018216SPaolo Bonzini case PPC6xx_INPUT_SMI: 13053018216SPaolo Bonzini /* Level sensitive - active high */ 13153018216SPaolo Bonzini LOG_IRQ("%s: set the SMI IRQ state to %d\n", 13253018216SPaolo Bonzini __func__, level); 13353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 13453018216SPaolo Bonzini break; 13553018216SPaolo Bonzini case PPC6xx_INPUT_MCP: 13653018216SPaolo Bonzini /* Negative edge sensitive */ 13753018216SPaolo Bonzini /* XXX: TODO: actual reaction may depends on HID0 status 13853018216SPaolo Bonzini * 603/604/740/750: check HID0[EMCP] 13953018216SPaolo Bonzini */ 14053018216SPaolo Bonzini if (cur_level == 1 && level == 0) { 14153018216SPaolo Bonzini LOG_IRQ("%s: raise machine check state\n", 14253018216SPaolo Bonzini __func__); 14353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 14453018216SPaolo Bonzini } 14553018216SPaolo Bonzini break; 14653018216SPaolo Bonzini case PPC6xx_INPUT_CKSTP_IN: 14753018216SPaolo Bonzini /* Level sensitive - active low */ 14853018216SPaolo Bonzini /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 14953018216SPaolo Bonzini /* XXX: Note that the only way to restart the CPU is to reset it */ 15053018216SPaolo Bonzini if (level) { 15153018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 152259186a7SAndreas Färber cs->halted = 1; 15353018216SPaolo Bonzini } 15453018216SPaolo Bonzini break; 15553018216SPaolo Bonzini case PPC6xx_INPUT_HRESET: 15653018216SPaolo Bonzini /* Level sensitive - active low */ 15753018216SPaolo Bonzini if (level) { 15853018216SPaolo Bonzini LOG_IRQ("%s: reset the CPU\n", __func__); 159c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_RESET); 16053018216SPaolo Bonzini } 16153018216SPaolo Bonzini break; 16253018216SPaolo Bonzini case PPC6xx_INPUT_SRESET: 16353018216SPaolo Bonzini LOG_IRQ("%s: set the RESET IRQ state to %d\n", 16453018216SPaolo Bonzini __func__, level); 16553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 16653018216SPaolo Bonzini break; 16753018216SPaolo Bonzini default: 16853018216SPaolo Bonzini /* Unknown pin - do nothing */ 16953018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 17053018216SPaolo Bonzini return; 17153018216SPaolo Bonzini } 17253018216SPaolo Bonzini if (level) 17353018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 17453018216SPaolo Bonzini else 17553018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 17653018216SPaolo Bonzini } 17753018216SPaolo Bonzini } 17853018216SPaolo Bonzini 179aa5a9e24SPaolo Bonzini void ppc6xx_irq_init(PowerPCCPU *cpu) 18053018216SPaolo Bonzini { 181aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 18253018216SPaolo Bonzini 18353018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 18453018216SPaolo Bonzini PPC6xx_INPUT_NB); 18553018216SPaolo Bonzini } 18653018216SPaolo Bonzini 18753018216SPaolo Bonzini #if defined(TARGET_PPC64) 18853018216SPaolo Bonzini /* PowerPC 970 internal IRQ controller */ 18953018216SPaolo Bonzini static void ppc970_set_irq(void *opaque, int pin, int level) 19053018216SPaolo Bonzini { 19153018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 19253018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 19353018216SPaolo Bonzini int cur_level; 19453018216SPaolo Bonzini 19553018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 19653018216SPaolo Bonzini env, pin, level); 19753018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 19853018216SPaolo Bonzini /* Don't generate spurious events */ 19953018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 200259186a7SAndreas Färber CPUState *cs = CPU(cpu); 201259186a7SAndreas Färber 20253018216SPaolo Bonzini switch (pin) { 20353018216SPaolo Bonzini case PPC970_INPUT_INT: 20453018216SPaolo Bonzini /* Level sensitive - active high */ 20553018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 20653018216SPaolo Bonzini __func__, level); 20753018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 20853018216SPaolo Bonzini break; 20953018216SPaolo Bonzini case PPC970_INPUT_THINT: 21053018216SPaolo Bonzini /* Level sensitive - active high */ 21153018216SPaolo Bonzini LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 21253018216SPaolo Bonzini level); 21353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 21453018216SPaolo Bonzini break; 21553018216SPaolo Bonzini case PPC970_INPUT_MCP: 21653018216SPaolo Bonzini /* Negative edge sensitive */ 21753018216SPaolo Bonzini /* XXX: TODO: actual reaction may depends on HID0 status 21853018216SPaolo Bonzini * 603/604/740/750: check HID0[EMCP] 21953018216SPaolo Bonzini */ 22053018216SPaolo Bonzini if (cur_level == 1 && level == 0) { 22153018216SPaolo Bonzini LOG_IRQ("%s: raise machine check state\n", 22253018216SPaolo Bonzini __func__); 22353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 22453018216SPaolo Bonzini } 22553018216SPaolo Bonzini break; 22653018216SPaolo Bonzini case PPC970_INPUT_CKSTP: 22753018216SPaolo Bonzini /* Level sensitive - active low */ 22853018216SPaolo Bonzini /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 22953018216SPaolo Bonzini if (level) { 23053018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 231259186a7SAndreas Färber cs->halted = 1; 23253018216SPaolo Bonzini } else { 23353018216SPaolo Bonzini LOG_IRQ("%s: restart the CPU\n", __func__); 234259186a7SAndreas Färber cs->halted = 0; 235259186a7SAndreas Färber qemu_cpu_kick(cs); 23653018216SPaolo Bonzini } 23753018216SPaolo Bonzini break; 23853018216SPaolo Bonzini case PPC970_INPUT_HRESET: 23953018216SPaolo Bonzini /* Level sensitive - active low */ 24053018216SPaolo Bonzini if (level) { 241c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_RESET); 24253018216SPaolo Bonzini } 24353018216SPaolo Bonzini break; 24453018216SPaolo Bonzini case PPC970_INPUT_SRESET: 24553018216SPaolo Bonzini LOG_IRQ("%s: set the RESET IRQ state to %d\n", 24653018216SPaolo Bonzini __func__, level); 24753018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 24853018216SPaolo Bonzini break; 24953018216SPaolo Bonzini case PPC970_INPUT_TBEN: 25053018216SPaolo Bonzini LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 25153018216SPaolo Bonzini level); 25253018216SPaolo Bonzini /* XXX: TODO */ 25353018216SPaolo Bonzini break; 25453018216SPaolo Bonzini default: 25553018216SPaolo Bonzini /* Unknown pin - do nothing */ 25653018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 25753018216SPaolo Bonzini return; 25853018216SPaolo Bonzini } 25953018216SPaolo Bonzini if (level) 26053018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 26153018216SPaolo Bonzini else 26253018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 26353018216SPaolo Bonzini } 26453018216SPaolo Bonzini } 26553018216SPaolo Bonzini 266aa5a9e24SPaolo Bonzini void ppc970_irq_init(PowerPCCPU *cpu) 26753018216SPaolo Bonzini { 268aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 26953018216SPaolo Bonzini 27053018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 27153018216SPaolo Bonzini PPC970_INPUT_NB); 27253018216SPaolo Bonzini } 27353018216SPaolo Bonzini 27453018216SPaolo Bonzini /* POWER7 internal IRQ controller */ 27553018216SPaolo Bonzini static void power7_set_irq(void *opaque, int pin, int level) 27653018216SPaolo Bonzini { 27753018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 27853018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 27953018216SPaolo Bonzini 28053018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 28153018216SPaolo Bonzini env, pin, level); 28253018216SPaolo Bonzini 28353018216SPaolo Bonzini switch (pin) { 28453018216SPaolo Bonzini case POWER7_INPUT_INT: 28553018216SPaolo Bonzini /* Level sensitive - active high */ 28653018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 28753018216SPaolo Bonzini __func__, level); 28853018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 28953018216SPaolo Bonzini break; 29053018216SPaolo Bonzini default: 29153018216SPaolo Bonzini /* Unknown pin - do nothing */ 29253018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 29353018216SPaolo Bonzini return; 29453018216SPaolo Bonzini } 29553018216SPaolo Bonzini if (level) { 29653018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 29753018216SPaolo Bonzini } else { 29853018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 29953018216SPaolo Bonzini } 30053018216SPaolo Bonzini } 30153018216SPaolo Bonzini 302aa5a9e24SPaolo Bonzini void ppcPOWER7_irq_init(PowerPCCPU *cpu) 30353018216SPaolo Bonzini { 304aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 30553018216SPaolo Bonzini 30653018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 30753018216SPaolo Bonzini POWER7_INPUT_NB); 30853018216SPaolo Bonzini } 30967afe775SBenjamin Herrenschmidt 31067afe775SBenjamin Herrenschmidt /* POWER9 internal IRQ controller */ 31167afe775SBenjamin Herrenschmidt static void power9_set_irq(void *opaque, int pin, int level) 31267afe775SBenjamin Herrenschmidt { 31367afe775SBenjamin Herrenschmidt PowerPCCPU *cpu = opaque; 31467afe775SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 31567afe775SBenjamin Herrenschmidt 31667afe775SBenjamin Herrenschmidt LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 31767afe775SBenjamin Herrenschmidt env, pin, level); 31867afe775SBenjamin Herrenschmidt 31967afe775SBenjamin Herrenschmidt switch (pin) { 32067afe775SBenjamin Herrenschmidt case POWER9_INPUT_INT: 32167afe775SBenjamin Herrenschmidt /* Level sensitive - active high */ 32267afe775SBenjamin Herrenschmidt LOG_IRQ("%s: set the external IRQ state to %d\n", 32367afe775SBenjamin Herrenschmidt __func__, level); 32467afe775SBenjamin Herrenschmidt ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 32567afe775SBenjamin Herrenschmidt break; 32667afe775SBenjamin Herrenschmidt case POWER9_INPUT_HINT: 32767afe775SBenjamin Herrenschmidt /* Level sensitive - active high */ 32867afe775SBenjamin Herrenschmidt LOG_IRQ("%s: set the external IRQ state to %d\n", 32967afe775SBenjamin Herrenschmidt __func__, level); 33067afe775SBenjamin Herrenschmidt ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 33167afe775SBenjamin Herrenschmidt break; 33267afe775SBenjamin Herrenschmidt default: 33367afe775SBenjamin Herrenschmidt /* Unknown pin - do nothing */ 33467afe775SBenjamin Herrenschmidt LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 33567afe775SBenjamin Herrenschmidt return; 33667afe775SBenjamin Herrenschmidt } 33767afe775SBenjamin Herrenschmidt if (level) { 33867afe775SBenjamin Herrenschmidt env->irq_input_state |= 1 << pin; 33967afe775SBenjamin Herrenschmidt } else { 34067afe775SBenjamin Herrenschmidt env->irq_input_state &= ~(1 << pin); 34167afe775SBenjamin Herrenschmidt } 34267afe775SBenjamin Herrenschmidt } 34367afe775SBenjamin Herrenschmidt 34467afe775SBenjamin Herrenschmidt void ppcPOWER9_irq_init(PowerPCCPU *cpu) 34567afe775SBenjamin Herrenschmidt { 34667afe775SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 34767afe775SBenjamin Herrenschmidt 34867afe775SBenjamin Herrenschmidt env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, 34967afe775SBenjamin Herrenschmidt POWER9_INPUT_NB); 35067afe775SBenjamin Herrenschmidt } 35153018216SPaolo Bonzini #endif /* defined(TARGET_PPC64) */ 35253018216SPaolo Bonzini 35352144b69SThomas Huth void ppc40x_core_reset(PowerPCCPU *cpu) 35452144b69SThomas Huth { 35552144b69SThomas Huth CPUPPCState *env = &cpu->env; 35652144b69SThomas Huth target_ulong dbsr; 35752144b69SThomas Huth 35852144b69SThomas Huth qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 35952144b69SThomas Huth cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 36052144b69SThomas Huth dbsr = env->spr[SPR_40x_DBSR]; 36152144b69SThomas Huth dbsr &= ~0x00000300; 36252144b69SThomas Huth dbsr |= 0x00000100; 36352144b69SThomas Huth env->spr[SPR_40x_DBSR] = dbsr; 36452144b69SThomas Huth } 36552144b69SThomas Huth 36652144b69SThomas Huth void ppc40x_chip_reset(PowerPCCPU *cpu) 36752144b69SThomas Huth { 36852144b69SThomas Huth CPUPPCState *env = &cpu->env; 36952144b69SThomas Huth target_ulong dbsr; 37052144b69SThomas Huth 37152144b69SThomas Huth qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 37252144b69SThomas Huth cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 37352144b69SThomas Huth /* XXX: TODO reset all internal peripherals */ 37452144b69SThomas Huth dbsr = env->spr[SPR_40x_DBSR]; 37552144b69SThomas Huth dbsr &= ~0x00000300; 37652144b69SThomas Huth dbsr |= 0x00000200; 37752144b69SThomas Huth env->spr[SPR_40x_DBSR] = dbsr; 37852144b69SThomas Huth } 37952144b69SThomas Huth 38052144b69SThomas Huth void ppc40x_system_reset(PowerPCCPU *cpu) 38152144b69SThomas Huth { 38252144b69SThomas Huth qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 38352144b69SThomas Huth qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 38452144b69SThomas Huth } 38552144b69SThomas Huth 38652144b69SThomas Huth void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 38752144b69SThomas Huth { 388db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 38952144b69SThomas Huth 39052144b69SThomas Huth switch ((val >> 28) & 0x3) { 39152144b69SThomas Huth case 0x0: 39252144b69SThomas Huth /* No action */ 39352144b69SThomas Huth break; 39452144b69SThomas Huth case 0x1: 39552144b69SThomas Huth /* Core reset */ 39652144b69SThomas Huth ppc40x_core_reset(cpu); 39752144b69SThomas Huth break; 39852144b69SThomas Huth case 0x2: 39952144b69SThomas Huth /* Chip reset */ 40052144b69SThomas Huth ppc40x_chip_reset(cpu); 40152144b69SThomas Huth break; 40252144b69SThomas Huth case 0x3: 40352144b69SThomas Huth /* System reset */ 40452144b69SThomas Huth ppc40x_system_reset(cpu); 40552144b69SThomas Huth break; 40652144b69SThomas Huth } 40752144b69SThomas Huth } 40852144b69SThomas Huth 40953018216SPaolo Bonzini /* PowerPC 40x internal IRQ controller */ 41053018216SPaolo Bonzini static void ppc40x_set_irq(void *opaque, int pin, int level) 41153018216SPaolo Bonzini { 41253018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 41353018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 41453018216SPaolo Bonzini int cur_level; 41553018216SPaolo Bonzini 41653018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 41753018216SPaolo Bonzini env, pin, level); 41853018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 41953018216SPaolo Bonzini /* Don't generate spurious events */ 42053018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 421259186a7SAndreas Färber CPUState *cs = CPU(cpu); 422259186a7SAndreas Färber 42353018216SPaolo Bonzini switch (pin) { 42453018216SPaolo Bonzini case PPC40x_INPUT_RESET_SYS: 42553018216SPaolo Bonzini if (level) { 42653018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC system\n", 42753018216SPaolo Bonzini __func__); 42853018216SPaolo Bonzini ppc40x_system_reset(cpu); 42953018216SPaolo Bonzini } 43053018216SPaolo Bonzini break; 43153018216SPaolo Bonzini case PPC40x_INPUT_RESET_CHIP: 43253018216SPaolo Bonzini if (level) { 43353018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 43453018216SPaolo Bonzini ppc40x_chip_reset(cpu); 43553018216SPaolo Bonzini } 43653018216SPaolo Bonzini break; 43753018216SPaolo Bonzini case PPC40x_INPUT_RESET_CORE: 43853018216SPaolo Bonzini /* XXX: TODO: update DBSR[MRR] */ 43953018216SPaolo Bonzini if (level) { 44053018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC core\n", __func__); 44153018216SPaolo Bonzini ppc40x_core_reset(cpu); 44253018216SPaolo Bonzini } 44353018216SPaolo Bonzini break; 44453018216SPaolo Bonzini case PPC40x_INPUT_CINT: 44553018216SPaolo Bonzini /* Level sensitive - active high */ 44653018216SPaolo Bonzini LOG_IRQ("%s: set the critical IRQ state to %d\n", 44753018216SPaolo Bonzini __func__, level); 44853018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 44953018216SPaolo Bonzini break; 45053018216SPaolo Bonzini case PPC40x_INPUT_INT: 45153018216SPaolo Bonzini /* Level sensitive - active high */ 45253018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 45353018216SPaolo Bonzini __func__, level); 45453018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 45553018216SPaolo Bonzini break; 45653018216SPaolo Bonzini case PPC40x_INPUT_HALT: 45753018216SPaolo Bonzini /* Level sensitive - active low */ 45853018216SPaolo Bonzini if (level) { 45953018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 460259186a7SAndreas Färber cs->halted = 1; 46153018216SPaolo Bonzini } else { 46253018216SPaolo Bonzini LOG_IRQ("%s: restart the CPU\n", __func__); 463259186a7SAndreas Färber cs->halted = 0; 464259186a7SAndreas Färber qemu_cpu_kick(cs); 46553018216SPaolo Bonzini } 46653018216SPaolo Bonzini break; 46753018216SPaolo Bonzini case PPC40x_INPUT_DEBUG: 46853018216SPaolo Bonzini /* Level sensitive - active high */ 46953018216SPaolo Bonzini LOG_IRQ("%s: set the debug pin state to %d\n", 47053018216SPaolo Bonzini __func__, level); 47153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 47253018216SPaolo Bonzini break; 47353018216SPaolo Bonzini default: 47453018216SPaolo Bonzini /* Unknown pin - do nothing */ 47553018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 47653018216SPaolo Bonzini return; 47753018216SPaolo Bonzini } 47853018216SPaolo Bonzini if (level) 47953018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 48053018216SPaolo Bonzini else 48153018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 48253018216SPaolo Bonzini } 48353018216SPaolo Bonzini } 48453018216SPaolo Bonzini 485aa5a9e24SPaolo Bonzini void ppc40x_irq_init(PowerPCCPU *cpu) 48653018216SPaolo Bonzini { 487aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 48853018216SPaolo Bonzini 48953018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 49053018216SPaolo Bonzini cpu, PPC40x_INPUT_NB); 49153018216SPaolo Bonzini } 49253018216SPaolo Bonzini 49353018216SPaolo Bonzini /* PowerPC E500 internal IRQ controller */ 49453018216SPaolo Bonzini static void ppce500_set_irq(void *opaque, int pin, int level) 49553018216SPaolo Bonzini { 49653018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 49753018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 49853018216SPaolo Bonzini int cur_level; 49953018216SPaolo Bonzini 50053018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 50153018216SPaolo Bonzini env, pin, level); 50253018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 50353018216SPaolo Bonzini /* Don't generate spurious events */ 50453018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 50553018216SPaolo Bonzini switch (pin) { 50653018216SPaolo Bonzini case PPCE500_INPUT_MCK: 50753018216SPaolo Bonzini if (level) { 50853018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC system\n", 50953018216SPaolo Bonzini __func__); 510cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 51153018216SPaolo Bonzini } 51253018216SPaolo Bonzini break; 51353018216SPaolo Bonzini case PPCE500_INPUT_RESET_CORE: 51453018216SPaolo Bonzini if (level) { 51553018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC core\n", __func__); 51653018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 51753018216SPaolo Bonzini } 51853018216SPaolo Bonzini break; 51953018216SPaolo Bonzini case PPCE500_INPUT_CINT: 52053018216SPaolo Bonzini /* Level sensitive - active high */ 52153018216SPaolo Bonzini LOG_IRQ("%s: set the critical IRQ state to %d\n", 52253018216SPaolo Bonzini __func__, level); 52353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 52453018216SPaolo Bonzini break; 52553018216SPaolo Bonzini case PPCE500_INPUT_INT: 52653018216SPaolo Bonzini /* Level sensitive - active high */ 52753018216SPaolo Bonzini LOG_IRQ("%s: set the core IRQ state to %d\n", 52853018216SPaolo Bonzini __func__, level); 52953018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 53053018216SPaolo Bonzini break; 53153018216SPaolo Bonzini case PPCE500_INPUT_DEBUG: 53253018216SPaolo Bonzini /* Level sensitive - active high */ 53353018216SPaolo Bonzini LOG_IRQ("%s: set the debug pin state to %d\n", 53453018216SPaolo Bonzini __func__, level); 53553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 53653018216SPaolo Bonzini break; 53753018216SPaolo Bonzini default: 53853018216SPaolo Bonzini /* Unknown pin - do nothing */ 53953018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 54053018216SPaolo Bonzini return; 54153018216SPaolo Bonzini } 54253018216SPaolo Bonzini if (level) 54353018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 54453018216SPaolo Bonzini else 54553018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 54653018216SPaolo Bonzini } 54753018216SPaolo Bonzini } 54853018216SPaolo Bonzini 549aa5a9e24SPaolo Bonzini void ppce500_irq_init(PowerPCCPU *cpu) 55053018216SPaolo Bonzini { 551aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 55253018216SPaolo Bonzini 55353018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 55453018216SPaolo Bonzini cpu, PPCE500_INPUT_NB); 55553018216SPaolo Bonzini } 55653018216SPaolo Bonzini 55753018216SPaolo Bonzini /* Enable or Disable the E500 EPR capability */ 55853018216SPaolo Bonzini void ppce500_set_mpic_proxy(bool enabled) 55953018216SPaolo Bonzini { 560182735efSAndreas Färber CPUState *cs; 56153018216SPaolo Bonzini 562bdc44640SAndreas Färber CPU_FOREACH(cs) { 563182735efSAndreas Färber PowerPCCPU *cpu = POWERPC_CPU(cs); 56453018216SPaolo Bonzini 565182735efSAndreas Färber cpu->env.mpic_proxy = enabled; 56653018216SPaolo Bonzini if (kvm_enabled()) { 567182735efSAndreas Färber kvmppc_set_mpic_proxy(cpu, enabled); 56853018216SPaolo Bonzini } 56953018216SPaolo Bonzini } 57053018216SPaolo Bonzini } 57153018216SPaolo Bonzini 57253018216SPaolo Bonzini /*****************************************************************************/ 57353018216SPaolo Bonzini /* PowerPC time base and decrementer emulation */ 57453018216SPaolo Bonzini 57553018216SPaolo Bonzini uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 57653018216SPaolo Bonzini { 57753018216SPaolo Bonzini /* TB time in tb periods */ 57873bcb24dSRutuja Shah return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 57953018216SPaolo Bonzini } 58053018216SPaolo Bonzini 58153018216SPaolo Bonzini uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 58253018216SPaolo Bonzini { 58353018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 58453018216SPaolo Bonzini uint64_t tb; 58553018216SPaolo Bonzini 58653018216SPaolo Bonzini if (kvm_enabled()) { 58753018216SPaolo Bonzini return env->spr[SPR_TBL]; 58853018216SPaolo Bonzini } 58953018216SPaolo Bonzini 590bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 59153018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 59253018216SPaolo Bonzini 59353018216SPaolo Bonzini return tb; 59453018216SPaolo Bonzini } 59553018216SPaolo Bonzini 59653018216SPaolo Bonzini static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 59753018216SPaolo Bonzini { 59853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 59953018216SPaolo Bonzini uint64_t tb; 60053018216SPaolo Bonzini 601bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 60253018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 60353018216SPaolo Bonzini 60453018216SPaolo Bonzini return tb >> 32; 60553018216SPaolo Bonzini } 60653018216SPaolo Bonzini 60753018216SPaolo Bonzini uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 60853018216SPaolo Bonzini { 60953018216SPaolo Bonzini if (kvm_enabled()) { 61053018216SPaolo Bonzini return env->spr[SPR_TBU]; 61153018216SPaolo Bonzini } 61253018216SPaolo Bonzini 61353018216SPaolo Bonzini return _cpu_ppc_load_tbu(env); 61453018216SPaolo Bonzini } 61553018216SPaolo Bonzini 61653018216SPaolo Bonzini static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 61753018216SPaolo Bonzini int64_t *tb_offsetp, uint64_t value) 61853018216SPaolo Bonzini { 61973bcb24dSRutuja Shah *tb_offsetp = value - 62073bcb24dSRutuja Shah muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 62173bcb24dSRutuja Shah 62253018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 62353018216SPaolo Bonzini __func__, value, *tb_offsetp); 62453018216SPaolo Bonzini } 62553018216SPaolo Bonzini 62653018216SPaolo Bonzini void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 62753018216SPaolo Bonzini { 62853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 62953018216SPaolo Bonzini uint64_t tb; 63053018216SPaolo Bonzini 631bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 63253018216SPaolo Bonzini tb &= 0xFFFFFFFF00000000ULL; 633bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 63453018216SPaolo Bonzini &tb_env->tb_offset, tb | (uint64_t)value); 63553018216SPaolo Bonzini } 63653018216SPaolo Bonzini 63753018216SPaolo Bonzini static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 63853018216SPaolo Bonzini { 63953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 64053018216SPaolo Bonzini uint64_t tb; 64153018216SPaolo Bonzini 642bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 64353018216SPaolo Bonzini tb &= 0x00000000FFFFFFFFULL; 644bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 64553018216SPaolo Bonzini &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 64653018216SPaolo Bonzini } 64753018216SPaolo Bonzini 64853018216SPaolo Bonzini void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 64953018216SPaolo Bonzini { 65053018216SPaolo Bonzini _cpu_ppc_store_tbu(env, value); 65153018216SPaolo Bonzini } 65253018216SPaolo Bonzini 65353018216SPaolo Bonzini uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 65453018216SPaolo Bonzini { 65553018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 65653018216SPaolo Bonzini uint64_t tb; 65753018216SPaolo Bonzini 658bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 65953018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 66053018216SPaolo Bonzini 66153018216SPaolo Bonzini return tb; 66253018216SPaolo Bonzini } 66353018216SPaolo Bonzini 66453018216SPaolo Bonzini uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 66553018216SPaolo Bonzini { 66653018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 66753018216SPaolo Bonzini uint64_t tb; 66853018216SPaolo Bonzini 669bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 67053018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 67153018216SPaolo Bonzini 67253018216SPaolo Bonzini return tb >> 32; 67353018216SPaolo Bonzini } 67453018216SPaolo Bonzini 67553018216SPaolo Bonzini void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 67653018216SPaolo Bonzini { 67753018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 67853018216SPaolo Bonzini uint64_t tb; 67953018216SPaolo Bonzini 680bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 68153018216SPaolo Bonzini tb &= 0xFFFFFFFF00000000ULL; 682bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 68353018216SPaolo Bonzini &tb_env->atb_offset, tb | (uint64_t)value); 68453018216SPaolo Bonzini } 68553018216SPaolo Bonzini 68653018216SPaolo Bonzini void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 68753018216SPaolo Bonzini { 68853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 68953018216SPaolo Bonzini uint64_t tb; 69053018216SPaolo Bonzini 691bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 69253018216SPaolo Bonzini tb &= 0x00000000FFFFFFFFULL; 693bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 69453018216SPaolo Bonzini &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 69553018216SPaolo Bonzini } 69653018216SPaolo Bonzini 69753018216SPaolo Bonzini static void cpu_ppc_tb_stop (CPUPPCState *env) 69853018216SPaolo Bonzini { 69953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 70053018216SPaolo Bonzini uint64_t tb, atb, vmclk; 70153018216SPaolo Bonzini 70253018216SPaolo Bonzini /* If the time base is already frozen, do nothing */ 70353018216SPaolo Bonzini if (tb_env->tb_freq != 0) { 704bc72ad67SAlex Bligh vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 70553018216SPaolo Bonzini /* Get the time base */ 70653018216SPaolo Bonzini tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 70753018216SPaolo Bonzini /* Get the alternate time base */ 70853018216SPaolo Bonzini atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 70953018216SPaolo Bonzini /* Store the time base value (ie compute the current offset) */ 71053018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 71153018216SPaolo Bonzini /* Store the alternate time base value (compute the current offset) */ 71253018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 71353018216SPaolo Bonzini /* Set the time base frequency to zero */ 71453018216SPaolo Bonzini tb_env->tb_freq = 0; 71553018216SPaolo Bonzini /* Now, the time bases are frozen to tb_offset / atb_offset value */ 71653018216SPaolo Bonzini } 71753018216SPaolo Bonzini } 71853018216SPaolo Bonzini 71953018216SPaolo Bonzini static void cpu_ppc_tb_start (CPUPPCState *env) 72053018216SPaolo Bonzini { 72153018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 72253018216SPaolo Bonzini uint64_t tb, atb, vmclk; 72353018216SPaolo Bonzini 72453018216SPaolo Bonzini /* If the time base is not frozen, do nothing */ 72553018216SPaolo Bonzini if (tb_env->tb_freq == 0) { 726bc72ad67SAlex Bligh vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 72753018216SPaolo Bonzini /* Get the time base from tb_offset */ 72853018216SPaolo Bonzini tb = tb_env->tb_offset; 72953018216SPaolo Bonzini /* Get the alternate time base from atb_offset */ 73053018216SPaolo Bonzini atb = tb_env->atb_offset; 73153018216SPaolo Bonzini /* Restore the tb frequency from the decrementer frequency */ 73253018216SPaolo Bonzini tb_env->tb_freq = tb_env->decr_freq; 73353018216SPaolo Bonzini /* Store the time base value */ 73453018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 73553018216SPaolo Bonzini /* Store the alternate time base value */ 73653018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 73753018216SPaolo Bonzini } 73853018216SPaolo Bonzini } 73953018216SPaolo Bonzini 740e81a982aSAlexander Graf bool ppc_decr_clear_on_delivery(CPUPPCState *env) 741e81a982aSAlexander Graf { 742e81a982aSAlexander Graf ppc_tb_t *tb_env = env->tb_env; 743e81a982aSAlexander Graf int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 744e81a982aSAlexander Graf return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 745e81a982aSAlexander Graf } 746e81a982aSAlexander Graf 747a8dafa52SSuraj Jitindar Singh static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 74853018216SPaolo Bonzini { 74953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 750a8dafa52SSuraj Jitindar Singh int64_t decr, diff; 75153018216SPaolo Bonzini 752bc72ad67SAlex Bligh diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 75353018216SPaolo Bonzini if (diff >= 0) { 75473bcb24dSRutuja Shah decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 75553018216SPaolo Bonzini } else if (tb_env->flags & PPC_TIMER_BOOKE) { 75653018216SPaolo Bonzini decr = 0; 75753018216SPaolo Bonzini } else { 75873bcb24dSRutuja Shah decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 75953018216SPaolo Bonzini } 760a8dafa52SSuraj Jitindar Singh LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); 76153018216SPaolo Bonzini 76253018216SPaolo Bonzini return decr; 76353018216SPaolo Bonzini } 76453018216SPaolo Bonzini 765a8dafa52SSuraj Jitindar Singh target_ulong cpu_ppc_load_decr(CPUPPCState *env) 76653018216SPaolo Bonzini { 76753018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 768a8dafa52SSuraj Jitindar Singh uint64_t decr; 76953018216SPaolo Bonzini 77053018216SPaolo Bonzini if (kvm_enabled()) { 77153018216SPaolo Bonzini return env->spr[SPR_DECR]; 77253018216SPaolo Bonzini } 77353018216SPaolo Bonzini 774a8dafa52SSuraj Jitindar Singh decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 775a8dafa52SSuraj Jitindar Singh 776a8dafa52SSuraj Jitindar Singh /* 777a8dafa52SSuraj Jitindar Singh * If large decrementer is enabled then the decrementer is signed extened 778a8dafa52SSuraj Jitindar Singh * to 64 bits, otherwise it is a 32 bit value. 779a8dafa52SSuraj Jitindar Singh */ 780a8dafa52SSuraj Jitindar Singh if (env->spr[SPR_LPCR] & LPCR_LD) { 781a8dafa52SSuraj Jitindar Singh return decr; 782a8dafa52SSuraj Jitindar Singh } 783a8dafa52SSuraj Jitindar Singh return (uint32_t) decr; 78453018216SPaolo Bonzini } 78553018216SPaolo Bonzini 786a8dafa52SSuraj Jitindar Singh target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 78753018216SPaolo Bonzini { 788db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 789a8dafa52SSuraj Jitindar Singh PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 79053018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 791a8dafa52SSuraj Jitindar Singh uint64_t hdecr; 79253018216SPaolo Bonzini 793a8dafa52SSuraj Jitindar Singh hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 794a8dafa52SSuraj Jitindar Singh 795a8dafa52SSuraj Jitindar Singh /* 796a8dafa52SSuraj Jitindar Singh * If we have a large decrementer (POWER9 or later) then hdecr is sign 797a8dafa52SSuraj Jitindar Singh * extended to 64 bits, otherwise it is 32 bits. 798a8dafa52SSuraj Jitindar Singh */ 799a8dafa52SSuraj Jitindar Singh if (pcc->lrg_decr_bits > 32) { 800a8dafa52SSuraj Jitindar Singh return hdecr; 801a8dafa52SSuraj Jitindar Singh } 802a8dafa52SSuraj Jitindar Singh return (uint32_t) hdecr; 80353018216SPaolo Bonzini } 80453018216SPaolo Bonzini 80553018216SPaolo Bonzini uint64_t cpu_ppc_load_purr (CPUPPCState *env) 80653018216SPaolo Bonzini { 80753018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 80853018216SPaolo Bonzini uint64_t diff; 80953018216SPaolo Bonzini 810bc72ad67SAlex Bligh diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; 81153018216SPaolo Bonzini 81273bcb24dSRutuja Shah return tb_env->purr_load + 81373bcb24dSRutuja Shah muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 81453018216SPaolo Bonzini } 81553018216SPaolo Bonzini 81653018216SPaolo Bonzini /* When decrementer expires, 81753018216SPaolo Bonzini * all we need to do is generate or queue a CPU exception 81853018216SPaolo Bonzini */ 81953018216SPaolo Bonzini static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 82053018216SPaolo Bonzini { 82153018216SPaolo Bonzini /* Raise it */ 82253018216SPaolo Bonzini LOG_TB("raise decrementer exception\n"); 82353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 82453018216SPaolo Bonzini } 82553018216SPaolo Bonzini 826e81a982aSAlexander Graf static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 827e81a982aSAlexander Graf { 828e81a982aSAlexander Graf ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 829e81a982aSAlexander Graf } 830e81a982aSAlexander Graf 83153018216SPaolo Bonzini static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 83253018216SPaolo Bonzini { 8334b236b62SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 8344b236b62SBenjamin Herrenschmidt 83553018216SPaolo Bonzini /* Raise it */ 8364b236b62SBenjamin Herrenschmidt LOG_TB("raise hv decrementer exception\n"); 8374b236b62SBenjamin Herrenschmidt 8384b236b62SBenjamin Herrenschmidt /* The architecture specifies that we don't deliver HDEC 8394b236b62SBenjamin Herrenschmidt * interrupts in a PM state. Not only they don't cause a 8404b236b62SBenjamin Herrenschmidt * wakeup but they also get effectively discarded. 8414b236b62SBenjamin Herrenschmidt */ 8421e7fd61dSBenjamin Herrenschmidt if (!env->resume_as_sreset) { 84353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 84453018216SPaolo Bonzini } 8454b236b62SBenjamin Herrenschmidt } 84653018216SPaolo Bonzini 847e81a982aSAlexander Graf static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 848e81a982aSAlexander Graf { 849e81a982aSAlexander Graf ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 850e81a982aSAlexander Graf } 851e81a982aSAlexander Graf 85253018216SPaolo Bonzini static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 8531246b259SStefan Weil QEMUTimer *timer, 854e81a982aSAlexander Graf void (*raise_excp)(void *), 855e81a982aSAlexander Graf void (*lower_excp)(PowerPCCPU *), 856a8dafa52SSuraj Jitindar Singh target_ulong decr, target_ulong value, 857a8dafa52SSuraj Jitindar Singh int nr_bits) 85853018216SPaolo Bonzini { 85953018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 86053018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 86153018216SPaolo Bonzini uint64_t now, next; 862a8dafa52SSuraj Jitindar Singh bool negative; 86353018216SPaolo Bonzini 864a8dafa52SSuraj Jitindar Singh /* Truncate value to decr_width and sign extend for simplicity */ 865a8dafa52SSuraj Jitindar Singh value &= ((1ULL << nr_bits) - 1); 866a8dafa52SSuraj Jitindar Singh negative = !!(value & (1ULL << (nr_bits - 1))); 867a8dafa52SSuraj Jitindar Singh if (negative) { 868a8dafa52SSuraj Jitindar Singh value |= (0xFFFFFFFFULL << nr_bits); 869a8dafa52SSuraj Jitindar Singh } 870a8dafa52SSuraj Jitindar Singh 871a8dafa52SSuraj Jitindar Singh LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, 87253018216SPaolo Bonzini decr, value); 87353018216SPaolo Bonzini 87453018216SPaolo Bonzini if (kvm_enabled()) { 87553018216SPaolo Bonzini /* KVM handles decrementer exceptions, we don't need our own timer */ 87653018216SPaolo Bonzini return; 87753018216SPaolo Bonzini } 87853018216SPaolo Bonzini 879e81a982aSAlexander Graf /* 880e81a982aSAlexander Graf * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 881e81a982aSAlexander Graf * interrupt. 882e81a982aSAlexander Graf * 883e81a982aSAlexander Graf * If we get a really small DEC value, we can assume that by the time we 884e81a982aSAlexander Graf * handled it we should inject an interrupt already. 885e81a982aSAlexander Graf * 886e81a982aSAlexander Graf * On MSB level based DEC implementations the MSB always means the interrupt 887e81a982aSAlexander Graf * is pending, so raise it on those. 888e81a982aSAlexander Graf * 889e81a982aSAlexander Graf * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 890e81a982aSAlexander Graf * an edge interrupt, so raise it here too. 891e81a982aSAlexander Graf */ 892e81a982aSAlexander Graf if ((value < 3) || 893a8dafa52SSuraj Jitindar Singh ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || 894a8dafa52SSuraj Jitindar Singh ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative 895a8dafa52SSuraj Jitindar Singh && !(decr & (1ULL << (nr_bits - 1))))) { 896e81a982aSAlexander Graf (*raise_excp)(cpu); 897e81a982aSAlexander Graf return; 898e81a982aSAlexander Graf } 899e81a982aSAlexander Graf 900e81a982aSAlexander Graf /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 901a8dafa52SSuraj Jitindar Singh if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 902e81a982aSAlexander Graf (*lower_excp)(cpu); 903e81a982aSAlexander Graf } 904e81a982aSAlexander Graf 905e81a982aSAlexander Graf /* Calculate the next timer event */ 906bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 90773bcb24dSRutuja Shah next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 90853018216SPaolo Bonzini *nextp = next; 909e81a982aSAlexander Graf 91053018216SPaolo Bonzini /* Adjust timer */ 911bc72ad67SAlex Bligh timer_mod(timer, next); 91253018216SPaolo Bonzini } 91353018216SPaolo Bonzini 914a8dafa52SSuraj Jitindar Singh static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 915a8dafa52SSuraj Jitindar Singh target_ulong value, int nr_bits) 91653018216SPaolo Bonzini { 91753018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 91853018216SPaolo Bonzini 91953018216SPaolo Bonzini __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 920e81a982aSAlexander Graf tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 921a8dafa52SSuraj Jitindar Singh value, nr_bits); 92253018216SPaolo Bonzini } 92353018216SPaolo Bonzini 924a8dafa52SSuraj Jitindar Singh void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 92553018216SPaolo Bonzini { 926db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 927a8dafa52SSuraj Jitindar Singh PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 928a8dafa52SSuraj Jitindar Singh int nr_bits = 32; 92953018216SPaolo Bonzini 930a8dafa52SSuraj Jitindar Singh if (env->spr[SPR_LPCR] & LPCR_LD) { 931a8dafa52SSuraj Jitindar Singh nr_bits = pcc->lrg_decr_bits; 932a8dafa52SSuraj Jitindar Singh } 933a8dafa52SSuraj Jitindar Singh 934a8dafa52SSuraj Jitindar Singh _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 93553018216SPaolo Bonzini } 93653018216SPaolo Bonzini 93753018216SPaolo Bonzini static void cpu_ppc_decr_cb(void *opaque) 93853018216SPaolo Bonzini { 93953018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 94053018216SPaolo Bonzini 941e81a982aSAlexander Graf cpu_ppc_decr_excp(cpu); 94253018216SPaolo Bonzini } 94353018216SPaolo Bonzini 944a8dafa52SSuraj Jitindar Singh static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 945a8dafa52SSuraj Jitindar Singh target_ulong value, int nr_bits) 94653018216SPaolo Bonzini { 94753018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 94853018216SPaolo Bonzini 94953018216SPaolo Bonzini if (tb_env->hdecr_timer != NULL) { 95053018216SPaolo Bonzini __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 951e81a982aSAlexander Graf tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 952a8dafa52SSuraj Jitindar Singh hdecr, value, nr_bits); 95353018216SPaolo Bonzini } 95453018216SPaolo Bonzini } 95553018216SPaolo Bonzini 956a8dafa52SSuraj Jitindar Singh void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 95753018216SPaolo Bonzini { 958db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 959a8dafa52SSuraj Jitindar Singh PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 96053018216SPaolo Bonzini 961a8dafa52SSuraj Jitindar Singh _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 962a8dafa52SSuraj Jitindar Singh pcc->lrg_decr_bits); 96353018216SPaolo Bonzini } 96453018216SPaolo Bonzini 96553018216SPaolo Bonzini static void cpu_ppc_hdecr_cb(void *opaque) 96653018216SPaolo Bonzini { 96753018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 96853018216SPaolo Bonzini 969e81a982aSAlexander Graf cpu_ppc_hdecr_excp(cpu); 97053018216SPaolo Bonzini } 97153018216SPaolo Bonzini 97253018216SPaolo Bonzini static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) 97353018216SPaolo Bonzini { 97453018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 97553018216SPaolo Bonzini 97653018216SPaolo Bonzini tb_env->purr_load = value; 977bc72ad67SAlex Bligh tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 97853018216SPaolo Bonzini } 97953018216SPaolo Bonzini 98053018216SPaolo Bonzini static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 98153018216SPaolo Bonzini { 98253018216SPaolo Bonzini CPUPPCState *env = opaque; 983db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 98453018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 98553018216SPaolo Bonzini 98653018216SPaolo Bonzini tb_env->tb_freq = freq; 98753018216SPaolo Bonzini tb_env->decr_freq = freq; 98853018216SPaolo Bonzini /* There is a bug in Linux 2.4 kernels: 98953018216SPaolo Bonzini * if a decrementer exception is pending when it enables msr_ee at startup, 99053018216SPaolo Bonzini * it's not ready to handle it... 99153018216SPaolo Bonzini */ 992a8dafa52SSuraj Jitindar Singh _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 993a8dafa52SSuraj Jitindar Singh _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 99453018216SPaolo Bonzini cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); 99553018216SPaolo Bonzini } 99653018216SPaolo Bonzini 99742043e4fSLaurent Vivier static void timebase_save(PPCTimebase *tb) 99898a8b524SAlexey Kardashevskiy { 9994a7428c5SChristopher Covington uint64_t ticks = cpu_get_host_ticks(); 100098a8b524SAlexey Kardashevskiy PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 100198a8b524SAlexey Kardashevskiy 100298a8b524SAlexey Kardashevskiy if (!first_ppc_cpu->env.tb_env) { 100398a8b524SAlexey Kardashevskiy error_report("No timebase object"); 100498a8b524SAlexey Kardashevskiy return; 100598a8b524SAlexey Kardashevskiy } 100698a8b524SAlexey Kardashevskiy 100742043e4fSLaurent Vivier /* not used anymore, we keep it for compatibility */ 100877bad151SPaolo Bonzini tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 100998a8b524SAlexey Kardashevskiy /* 101042043e4fSLaurent Vivier * tb_offset is only expected to be changed by QEMU so 101198a8b524SAlexey Kardashevskiy * there is no need to update it from KVM here 101298a8b524SAlexey Kardashevskiy */ 101398a8b524SAlexey Kardashevskiy tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 1014d14f3397SMaxiwell S. Garcia 1015d14f3397SMaxiwell S. Garcia tb->runstate_paused = runstate_check(RUN_STATE_PAUSED); 101698a8b524SAlexey Kardashevskiy } 101798a8b524SAlexey Kardashevskiy 101842043e4fSLaurent Vivier static void timebase_load(PPCTimebase *tb) 101998a8b524SAlexey Kardashevskiy { 102098a8b524SAlexey Kardashevskiy CPUState *cpu; 102198a8b524SAlexey Kardashevskiy PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 102242043e4fSLaurent Vivier int64_t tb_off_adj, tb_off; 102398a8b524SAlexey Kardashevskiy unsigned long freq; 102498a8b524SAlexey Kardashevskiy 102598a8b524SAlexey Kardashevskiy if (!first_ppc_cpu->env.tb_env) { 102698a8b524SAlexey Kardashevskiy error_report("No timebase object"); 102742043e4fSLaurent Vivier return; 102898a8b524SAlexey Kardashevskiy } 102998a8b524SAlexey Kardashevskiy 103098a8b524SAlexey Kardashevskiy freq = first_ppc_cpu->env.tb_env->tb_freq; 103198a8b524SAlexey Kardashevskiy 103242043e4fSLaurent Vivier tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 103398a8b524SAlexey Kardashevskiy 103498a8b524SAlexey Kardashevskiy tb_off = first_ppc_cpu->env.tb_env->tb_offset; 103598a8b524SAlexey Kardashevskiy trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 103698a8b524SAlexey Kardashevskiy (tb_off_adj - tb_off) / freq); 103798a8b524SAlexey Kardashevskiy 103898a8b524SAlexey Kardashevskiy /* Set new offset to all CPUs */ 103998a8b524SAlexey Kardashevskiy CPU_FOREACH(cpu) { 104098a8b524SAlexey Kardashevskiy PowerPCCPU *pcpu = POWERPC_CPU(cpu); 104198a8b524SAlexey Kardashevskiy pcpu->env.tb_env->tb_offset = tb_off_adj; 10429723295aSGreg Kurz kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); 104342043e4fSLaurent Vivier } 104498a8b524SAlexey Kardashevskiy } 104598a8b524SAlexey Kardashevskiy 104642043e4fSLaurent Vivier void cpu_ppc_clock_vm_state_change(void *opaque, int running, 104742043e4fSLaurent Vivier RunState state) 104842043e4fSLaurent Vivier { 104942043e4fSLaurent Vivier PPCTimebase *tb = opaque; 105042043e4fSLaurent Vivier 105142043e4fSLaurent Vivier if (running) { 105242043e4fSLaurent Vivier timebase_load(tb); 105342043e4fSLaurent Vivier } else { 105442043e4fSLaurent Vivier timebase_save(tb); 105542043e4fSLaurent Vivier } 105642043e4fSLaurent Vivier } 105742043e4fSLaurent Vivier 105842043e4fSLaurent Vivier /* 1059d14f3397SMaxiwell S. Garcia * When migrating a running guest, read the clock just 1060d14f3397SMaxiwell S. Garcia * before migration, so that the guest clock counts 1061d14f3397SMaxiwell S. Garcia * during the events between: 106242043e4fSLaurent Vivier * 106342043e4fSLaurent Vivier * * vm_stop() 106442043e4fSLaurent Vivier * * 106542043e4fSLaurent Vivier * * pre_save() 106642043e4fSLaurent Vivier * 106742043e4fSLaurent Vivier * This reduces clock difference on migration from 5s 106842043e4fSLaurent Vivier * to 0.1s (when max_downtime == 5s), because sending the 106942043e4fSLaurent Vivier * final pages of memory (which happens between vm_stop() 107042043e4fSLaurent Vivier * and pre_save()) takes max_downtime. 107142043e4fSLaurent Vivier */ 107244b1ff31SDr. David Alan Gilbert static int timebase_pre_save(void *opaque) 107342043e4fSLaurent Vivier { 107442043e4fSLaurent Vivier PPCTimebase *tb = opaque; 107542043e4fSLaurent Vivier 1076d14f3397SMaxiwell S. Garcia /* guest_timebase won't be overridden in case of paused guest */ 1077d14f3397SMaxiwell S. Garcia if (!tb->runstate_paused) { 107842043e4fSLaurent Vivier timebase_save(tb); 1079d14f3397SMaxiwell S. Garcia } 108044b1ff31SDr. David Alan Gilbert 108144b1ff31SDr. David Alan Gilbert return 0; 108298a8b524SAlexey Kardashevskiy } 108398a8b524SAlexey Kardashevskiy 108498a8b524SAlexey Kardashevskiy const VMStateDescription vmstate_ppc_timebase = { 108598a8b524SAlexey Kardashevskiy .name = "timebase", 108698a8b524SAlexey Kardashevskiy .version_id = 1, 108798a8b524SAlexey Kardashevskiy .minimum_version_id = 1, 108898a8b524SAlexey Kardashevskiy .minimum_version_id_old = 1, 108998a8b524SAlexey Kardashevskiy .pre_save = timebase_pre_save, 109098a8b524SAlexey Kardashevskiy .fields = (VMStateField []) { 109198a8b524SAlexey Kardashevskiy VMSTATE_UINT64(guest_timebase, PPCTimebase), 109298a8b524SAlexey Kardashevskiy VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 109398a8b524SAlexey Kardashevskiy VMSTATE_END_OF_LIST() 109498a8b524SAlexey Kardashevskiy }, 109598a8b524SAlexey Kardashevskiy }; 109698a8b524SAlexey Kardashevskiy 109753018216SPaolo Bonzini /* Set up (once) timebase frequency (in Hz) */ 109853018216SPaolo Bonzini clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 109953018216SPaolo Bonzini { 1100db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env); 110153018216SPaolo Bonzini ppc_tb_t *tb_env; 110253018216SPaolo Bonzini 110353018216SPaolo Bonzini tb_env = g_malloc0(sizeof(ppc_tb_t)); 110453018216SPaolo Bonzini env->tb_env = tb_env; 110553018216SPaolo Bonzini tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1106d0db7cadSGreg Kurz if (is_book3s_arch2x(env)) { 1107e81a982aSAlexander Graf /* All Book3S 64bit CPUs implement level based DEC logic */ 1108e81a982aSAlexander Graf tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1109e81a982aSAlexander Graf } 111053018216SPaolo Bonzini /* Create new timer */ 1111bc72ad67SAlex Bligh tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 11124b236b62SBenjamin Herrenschmidt if (env->has_hv_mode) { 1113bc72ad67SAlex Bligh tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 111453018216SPaolo Bonzini cpu); 111553018216SPaolo Bonzini } else { 111653018216SPaolo Bonzini tb_env->hdecr_timer = NULL; 111753018216SPaolo Bonzini } 111853018216SPaolo Bonzini cpu_ppc_set_tb_clk(env, freq); 111953018216SPaolo Bonzini 112053018216SPaolo Bonzini return &cpu_ppc_set_tb_clk; 112153018216SPaolo Bonzini } 112253018216SPaolo Bonzini 112353018216SPaolo Bonzini /* Specific helpers for POWER & PowerPC 601 RTC */ 112453018216SPaolo Bonzini void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 112553018216SPaolo Bonzini { 112653018216SPaolo Bonzini _cpu_ppc_store_tbu(env, value); 112753018216SPaolo Bonzini } 112853018216SPaolo Bonzini 112953018216SPaolo Bonzini uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 113053018216SPaolo Bonzini { 113153018216SPaolo Bonzini return _cpu_ppc_load_tbu(env); 113253018216SPaolo Bonzini } 113353018216SPaolo Bonzini 113453018216SPaolo Bonzini void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 113553018216SPaolo Bonzini { 113653018216SPaolo Bonzini cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 113753018216SPaolo Bonzini } 113853018216SPaolo Bonzini 113953018216SPaolo Bonzini uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 114053018216SPaolo Bonzini { 114153018216SPaolo Bonzini return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 114253018216SPaolo Bonzini } 114353018216SPaolo Bonzini 114453018216SPaolo Bonzini /*****************************************************************************/ 114553018216SPaolo Bonzini /* PowerPC 40x timers */ 114653018216SPaolo Bonzini 114753018216SPaolo Bonzini /* PIT, FIT & WDT */ 114853018216SPaolo Bonzini typedef struct ppc40x_timer_t ppc40x_timer_t; 114953018216SPaolo Bonzini struct ppc40x_timer_t { 115053018216SPaolo Bonzini uint64_t pit_reload; /* PIT auto-reload value */ 115153018216SPaolo Bonzini uint64_t fit_next; /* Tick for next FIT interrupt */ 11521246b259SStefan Weil QEMUTimer *fit_timer; 115353018216SPaolo Bonzini uint64_t wdt_next; /* Tick for next WDT interrupt */ 11541246b259SStefan Weil QEMUTimer *wdt_timer; 115553018216SPaolo Bonzini 115653018216SPaolo Bonzini /* 405 have the PIT, 440 have a DECR. */ 115753018216SPaolo Bonzini unsigned int decr_excp; 115853018216SPaolo Bonzini }; 115953018216SPaolo Bonzini 116053018216SPaolo Bonzini /* Fixed interval timer */ 116153018216SPaolo Bonzini static void cpu_4xx_fit_cb (void *opaque) 116253018216SPaolo Bonzini { 116353018216SPaolo Bonzini PowerPCCPU *cpu; 116453018216SPaolo Bonzini CPUPPCState *env; 116553018216SPaolo Bonzini ppc_tb_t *tb_env; 116653018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 116753018216SPaolo Bonzini uint64_t now, next; 116853018216SPaolo Bonzini 116953018216SPaolo Bonzini env = opaque; 1170db70b311SRichard Henderson cpu = env_archcpu(env); 117153018216SPaolo Bonzini tb_env = env->tb_env; 117253018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 1173bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 117453018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 117553018216SPaolo Bonzini case 0: 117653018216SPaolo Bonzini next = 1 << 9; 117753018216SPaolo Bonzini break; 117853018216SPaolo Bonzini case 1: 117953018216SPaolo Bonzini next = 1 << 13; 118053018216SPaolo Bonzini break; 118153018216SPaolo Bonzini case 2: 118253018216SPaolo Bonzini next = 1 << 17; 118353018216SPaolo Bonzini break; 118453018216SPaolo Bonzini case 3: 118553018216SPaolo Bonzini next = 1 << 21; 118653018216SPaolo Bonzini break; 118753018216SPaolo Bonzini default: 118853018216SPaolo Bonzini /* Cannot occur, but makes gcc happy */ 118953018216SPaolo Bonzini return; 119053018216SPaolo Bonzini } 119173bcb24dSRutuja Shah next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 119253018216SPaolo Bonzini if (next == now) 119353018216SPaolo Bonzini next++; 1194bc72ad67SAlex Bligh timer_mod(ppc40x_timer->fit_timer, next); 119553018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 26; 119653018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 119753018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 119853018216SPaolo Bonzini } 119953018216SPaolo Bonzini LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 120053018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 120153018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 120253018216SPaolo Bonzini } 120353018216SPaolo Bonzini 120453018216SPaolo Bonzini /* Programmable interval timer */ 120553018216SPaolo Bonzini static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 120653018216SPaolo Bonzini { 120753018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 120853018216SPaolo Bonzini uint64_t now, next; 120953018216SPaolo Bonzini 121053018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 121153018216SPaolo Bonzini if (ppc40x_timer->pit_reload <= 1 || 121253018216SPaolo Bonzini !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 121353018216SPaolo Bonzini (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 121453018216SPaolo Bonzini /* Stop PIT */ 121553018216SPaolo Bonzini LOG_TB("%s: stop PIT\n", __func__); 1216bc72ad67SAlex Bligh timer_del(tb_env->decr_timer); 121753018216SPaolo Bonzini } else { 121853018216SPaolo Bonzini LOG_TB("%s: start PIT %016" PRIx64 "\n", 121953018216SPaolo Bonzini __func__, ppc40x_timer->pit_reload); 1220bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 122153018216SPaolo Bonzini next = now + muldiv64(ppc40x_timer->pit_reload, 122273bcb24dSRutuja Shah NANOSECONDS_PER_SECOND, tb_env->decr_freq); 122353018216SPaolo Bonzini if (is_excp) 122453018216SPaolo Bonzini next += tb_env->decr_next - now; 122553018216SPaolo Bonzini if (next == now) 122653018216SPaolo Bonzini next++; 1227bc72ad67SAlex Bligh timer_mod(tb_env->decr_timer, next); 122853018216SPaolo Bonzini tb_env->decr_next = next; 122953018216SPaolo Bonzini } 123053018216SPaolo Bonzini } 123153018216SPaolo Bonzini 123253018216SPaolo Bonzini static void cpu_4xx_pit_cb (void *opaque) 123353018216SPaolo Bonzini { 123453018216SPaolo Bonzini PowerPCCPU *cpu; 123553018216SPaolo Bonzini CPUPPCState *env; 123653018216SPaolo Bonzini ppc_tb_t *tb_env; 123753018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 123853018216SPaolo Bonzini 123953018216SPaolo Bonzini env = opaque; 1240db70b311SRichard Henderson cpu = env_archcpu(env); 124153018216SPaolo Bonzini tb_env = env->tb_env; 124253018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 124353018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 27; 124453018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 124553018216SPaolo Bonzini ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 124653018216SPaolo Bonzini } 124753018216SPaolo Bonzini start_stop_pit(env, tb_env, 1); 124853018216SPaolo Bonzini LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 124953018216SPaolo Bonzini "%016" PRIx64 "\n", __func__, 125053018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 125153018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 125253018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 125353018216SPaolo Bonzini ppc40x_timer->pit_reload); 125453018216SPaolo Bonzini } 125553018216SPaolo Bonzini 125653018216SPaolo Bonzini /* Watchdog timer */ 125753018216SPaolo Bonzini static void cpu_4xx_wdt_cb (void *opaque) 125853018216SPaolo Bonzini { 125953018216SPaolo Bonzini PowerPCCPU *cpu; 126053018216SPaolo Bonzini CPUPPCState *env; 126153018216SPaolo Bonzini ppc_tb_t *tb_env; 126253018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 126353018216SPaolo Bonzini uint64_t now, next; 126453018216SPaolo Bonzini 126553018216SPaolo Bonzini env = opaque; 1266db70b311SRichard Henderson cpu = env_archcpu(env); 126753018216SPaolo Bonzini tb_env = env->tb_env; 126853018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 1269bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 127053018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 127153018216SPaolo Bonzini case 0: 127253018216SPaolo Bonzini next = 1 << 17; 127353018216SPaolo Bonzini break; 127453018216SPaolo Bonzini case 1: 127553018216SPaolo Bonzini next = 1 << 21; 127653018216SPaolo Bonzini break; 127753018216SPaolo Bonzini case 2: 127853018216SPaolo Bonzini next = 1 << 25; 127953018216SPaolo Bonzini break; 128053018216SPaolo Bonzini case 3: 128153018216SPaolo Bonzini next = 1 << 29; 128253018216SPaolo Bonzini break; 128353018216SPaolo Bonzini default: 128453018216SPaolo Bonzini /* Cannot occur, but makes gcc happy */ 128553018216SPaolo Bonzini return; 128653018216SPaolo Bonzini } 128773bcb24dSRutuja Shah next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 128853018216SPaolo Bonzini if (next == now) 128953018216SPaolo Bonzini next++; 129053018216SPaolo Bonzini LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 129153018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 129253018216SPaolo Bonzini switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 129353018216SPaolo Bonzini case 0x0: 129453018216SPaolo Bonzini case 0x1: 1295bc72ad67SAlex Bligh timer_mod(ppc40x_timer->wdt_timer, next); 129653018216SPaolo Bonzini ppc40x_timer->wdt_next = next; 1297a1f7f97bSPeter Maydell env->spr[SPR_40x_TSR] |= 1U << 31; 129853018216SPaolo Bonzini break; 129953018216SPaolo Bonzini case 0x2: 1300bc72ad67SAlex Bligh timer_mod(ppc40x_timer->wdt_timer, next); 130153018216SPaolo Bonzini ppc40x_timer->wdt_next = next; 130253018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 30; 130353018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 130453018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 130553018216SPaolo Bonzini } 130653018216SPaolo Bonzini break; 130753018216SPaolo Bonzini case 0x3: 130853018216SPaolo Bonzini env->spr[SPR_40x_TSR] &= ~0x30000000; 130953018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 131053018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 131153018216SPaolo Bonzini case 0x0: 131253018216SPaolo Bonzini /* No reset */ 131353018216SPaolo Bonzini break; 131453018216SPaolo Bonzini case 0x1: /* Core reset */ 131553018216SPaolo Bonzini ppc40x_core_reset(cpu); 131653018216SPaolo Bonzini break; 131753018216SPaolo Bonzini case 0x2: /* Chip reset */ 131853018216SPaolo Bonzini ppc40x_chip_reset(cpu); 131953018216SPaolo Bonzini break; 132053018216SPaolo Bonzini case 0x3: /* System reset */ 132153018216SPaolo Bonzini ppc40x_system_reset(cpu); 132253018216SPaolo Bonzini break; 132353018216SPaolo Bonzini } 132453018216SPaolo Bonzini } 132553018216SPaolo Bonzini } 132653018216SPaolo Bonzini 132753018216SPaolo Bonzini void store_40x_pit (CPUPPCState *env, target_ulong val) 132853018216SPaolo Bonzini { 132953018216SPaolo Bonzini ppc_tb_t *tb_env; 133053018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 133153018216SPaolo Bonzini 133253018216SPaolo Bonzini tb_env = env->tb_env; 133353018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 133453018216SPaolo Bonzini LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 133553018216SPaolo Bonzini ppc40x_timer->pit_reload = val; 133653018216SPaolo Bonzini start_stop_pit(env, tb_env, 0); 133753018216SPaolo Bonzini } 133853018216SPaolo Bonzini 133953018216SPaolo Bonzini target_ulong load_40x_pit (CPUPPCState *env) 134053018216SPaolo Bonzini { 134153018216SPaolo Bonzini return cpu_ppc_load_decr(env); 134253018216SPaolo Bonzini } 134353018216SPaolo Bonzini 134453018216SPaolo Bonzini static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 134553018216SPaolo Bonzini { 134653018216SPaolo Bonzini CPUPPCState *env = opaque; 134753018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 134853018216SPaolo Bonzini 134953018216SPaolo Bonzini LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 135053018216SPaolo Bonzini freq); 135153018216SPaolo Bonzini tb_env->tb_freq = freq; 135253018216SPaolo Bonzini tb_env->decr_freq = freq; 135353018216SPaolo Bonzini /* XXX: we should also update all timers */ 135453018216SPaolo Bonzini } 135553018216SPaolo Bonzini 135653018216SPaolo Bonzini clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 135753018216SPaolo Bonzini unsigned int decr_excp) 135853018216SPaolo Bonzini { 135953018216SPaolo Bonzini ppc_tb_t *tb_env; 136053018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 136153018216SPaolo Bonzini 136253018216SPaolo Bonzini tb_env = g_malloc0(sizeof(ppc_tb_t)); 136353018216SPaolo Bonzini env->tb_env = tb_env; 136453018216SPaolo Bonzini tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 136553018216SPaolo Bonzini ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 136653018216SPaolo Bonzini tb_env->tb_freq = freq; 136753018216SPaolo Bonzini tb_env->decr_freq = freq; 136853018216SPaolo Bonzini tb_env->opaque = ppc40x_timer; 136953018216SPaolo Bonzini LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 137053018216SPaolo Bonzini if (ppc40x_timer != NULL) { 137153018216SPaolo Bonzini /* We use decr timer for PIT */ 1372bc72ad67SAlex Bligh tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 137353018216SPaolo Bonzini ppc40x_timer->fit_timer = 1374bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 137553018216SPaolo Bonzini ppc40x_timer->wdt_timer = 1376bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 137753018216SPaolo Bonzini ppc40x_timer->decr_excp = decr_excp; 137853018216SPaolo Bonzini } 137953018216SPaolo Bonzini 138053018216SPaolo Bonzini return &ppc_40x_set_tb_clk; 138153018216SPaolo Bonzini } 138253018216SPaolo Bonzini 138353018216SPaolo Bonzini /*****************************************************************************/ 138453018216SPaolo Bonzini /* Embedded PowerPC Device Control Registers */ 138553018216SPaolo Bonzini typedef struct ppc_dcrn_t ppc_dcrn_t; 138653018216SPaolo Bonzini struct ppc_dcrn_t { 138753018216SPaolo Bonzini dcr_read_cb dcr_read; 138853018216SPaolo Bonzini dcr_write_cb dcr_write; 138953018216SPaolo Bonzini void *opaque; 139053018216SPaolo Bonzini }; 139153018216SPaolo Bonzini 139253018216SPaolo Bonzini /* XXX: on 460, DCR addresses are 32 bits wide, 139353018216SPaolo Bonzini * using DCRIPR to get the 22 upper bits of the DCR address 139453018216SPaolo Bonzini */ 139553018216SPaolo Bonzini #define DCRN_NB 1024 139653018216SPaolo Bonzini struct ppc_dcr_t { 139753018216SPaolo Bonzini ppc_dcrn_t dcrn[DCRN_NB]; 139853018216SPaolo Bonzini int (*read_error)(int dcrn); 139953018216SPaolo Bonzini int (*write_error)(int dcrn); 140053018216SPaolo Bonzini }; 140153018216SPaolo Bonzini 140253018216SPaolo Bonzini int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 140353018216SPaolo Bonzini { 140453018216SPaolo Bonzini ppc_dcrn_t *dcr; 140553018216SPaolo Bonzini 140653018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 140753018216SPaolo Bonzini goto error; 140853018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 140953018216SPaolo Bonzini if (dcr->dcr_read == NULL) 141053018216SPaolo Bonzini goto error; 141153018216SPaolo Bonzini *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 141253018216SPaolo Bonzini 141353018216SPaolo Bonzini return 0; 141453018216SPaolo Bonzini 141553018216SPaolo Bonzini error: 141653018216SPaolo Bonzini if (dcr_env->read_error != NULL) 141753018216SPaolo Bonzini return (*dcr_env->read_error)(dcrn); 141853018216SPaolo Bonzini 141953018216SPaolo Bonzini return -1; 142053018216SPaolo Bonzini } 142153018216SPaolo Bonzini 142253018216SPaolo Bonzini int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 142353018216SPaolo Bonzini { 142453018216SPaolo Bonzini ppc_dcrn_t *dcr; 142553018216SPaolo Bonzini 142653018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 142753018216SPaolo Bonzini goto error; 142853018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 142953018216SPaolo Bonzini if (dcr->dcr_write == NULL) 143053018216SPaolo Bonzini goto error; 143153018216SPaolo Bonzini (*dcr->dcr_write)(dcr->opaque, dcrn, val); 143253018216SPaolo Bonzini 143353018216SPaolo Bonzini return 0; 143453018216SPaolo Bonzini 143553018216SPaolo Bonzini error: 143653018216SPaolo Bonzini if (dcr_env->write_error != NULL) 143753018216SPaolo Bonzini return (*dcr_env->write_error)(dcrn); 143853018216SPaolo Bonzini 143953018216SPaolo Bonzini return -1; 144053018216SPaolo Bonzini } 144153018216SPaolo Bonzini 144253018216SPaolo Bonzini int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 144353018216SPaolo Bonzini dcr_read_cb dcr_read, dcr_write_cb dcr_write) 144453018216SPaolo Bonzini { 144553018216SPaolo Bonzini ppc_dcr_t *dcr_env; 144653018216SPaolo Bonzini ppc_dcrn_t *dcr; 144753018216SPaolo Bonzini 144853018216SPaolo Bonzini dcr_env = env->dcr_env; 144953018216SPaolo Bonzini if (dcr_env == NULL) 145053018216SPaolo Bonzini return -1; 145153018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 145253018216SPaolo Bonzini return -1; 145353018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 145453018216SPaolo Bonzini if (dcr->opaque != NULL || 145553018216SPaolo Bonzini dcr->dcr_read != NULL || 145653018216SPaolo Bonzini dcr->dcr_write != NULL) 145753018216SPaolo Bonzini return -1; 145853018216SPaolo Bonzini dcr->opaque = opaque; 145953018216SPaolo Bonzini dcr->dcr_read = dcr_read; 146053018216SPaolo Bonzini dcr->dcr_write = dcr_write; 146153018216SPaolo Bonzini 146253018216SPaolo Bonzini return 0; 146353018216SPaolo Bonzini } 146453018216SPaolo Bonzini 146553018216SPaolo Bonzini int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 146653018216SPaolo Bonzini int (*write_error)(int dcrn)) 146753018216SPaolo Bonzini { 146853018216SPaolo Bonzini ppc_dcr_t *dcr_env; 146953018216SPaolo Bonzini 147053018216SPaolo Bonzini dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 147153018216SPaolo Bonzini dcr_env->read_error = read_error; 147253018216SPaolo Bonzini dcr_env->write_error = write_error; 147353018216SPaolo Bonzini env->dcr_env = dcr_env; 147453018216SPaolo Bonzini 147553018216SPaolo Bonzini return 0; 147653018216SPaolo Bonzini } 147753018216SPaolo Bonzini 147853018216SPaolo Bonzini /*****************************************************************************/ 147953018216SPaolo Bonzini /* Debug port */ 148053018216SPaolo Bonzini void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 148153018216SPaolo Bonzini { 148253018216SPaolo Bonzini addr &= 0xF; 148353018216SPaolo Bonzini switch (addr) { 148453018216SPaolo Bonzini case 0: 148553018216SPaolo Bonzini printf("%c", val); 148653018216SPaolo Bonzini break; 148753018216SPaolo Bonzini case 1: 148853018216SPaolo Bonzini printf("\n"); 148953018216SPaolo Bonzini fflush(stdout); 149053018216SPaolo Bonzini break; 149153018216SPaolo Bonzini case 2: 149253018216SPaolo Bonzini printf("Set loglevel to %04" PRIx32 "\n", val); 149353018216SPaolo Bonzini qemu_set_log(val | 0x100); 149453018216SPaolo Bonzini break; 149553018216SPaolo Bonzini } 149653018216SPaolo Bonzini } 1497051e2973SCédric Le Goater 14984a89e204SCédric Le Goater int ppc_cpu_pir(PowerPCCPU *cpu) 14994a89e204SCédric Le Goater { 15004a89e204SCédric Le Goater CPUPPCState *env = &cpu->env; 15014a89e204SCédric Le Goater return env->spr_cb[SPR_PIR].default_value; 15024a89e204SCédric Le Goater } 15034a89e204SCédric Le Goater 1504051e2973SCédric Le Goater PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1505051e2973SCédric Le Goater { 1506051e2973SCédric Le Goater CPUState *cs; 1507051e2973SCédric Le Goater 1508051e2973SCédric Le Goater CPU_FOREACH(cs) { 1509051e2973SCédric Le Goater PowerPCCPU *cpu = POWERPC_CPU(cs); 1510051e2973SCédric Le Goater 15114a89e204SCédric Le Goater if (ppc_cpu_pir(cpu) == pir) { 1512051e2973SCédric Le Goater return cpu; 1513051e2973SCédric Le Goater } 1514051e2973SCédric Le Goater } 1515051e2973SCédric Le Goater 1516051e2973SCédric Le Goater return NULL; 1517051e2973SCédric Le Goater } 1518*40177438SGreg Kurz 1519*40177438SGreg Kurz void ppc_irq_reset(PowerPCCPU *cpu) 1520*40177438SGreg Kurz { 1521*40177438SGreg Kurz CPUPPCState *env = &cpu->env; 1522*40177438SGreg Kurz 1523*40177438SGreg Kurz env->irq_input_state = 0; 1524*40177438SGreg Kurz kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); 1525*40177438SGreg Kurz } 1526