153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * QEMU generic PowerPC hardware System Emulator 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2003-2007 Jocelyn Mayer 553018216SPaolo Bonzini * 653018216SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 753018216SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 853018216SPaolo Bonzini * in the Software without restriction, including without limitation the rights 953018216SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1053018216SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1153018216SPaolo Bonzini * furnished to do so, subject to the following conditions: 1253018216SPaolo Bonzini * 1353018216SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1453018216SPaolo Bonzini * all copies or substantial portions of the Software. 1553018216SPaolo Bonzini * 1653018216SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1753018216SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1853018216SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1953018216SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2053018216SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2153018216SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2253018216SPaolo Bonzini * THE SOFTWARE. 2353018216SPaolo Bonzini */ 240d75590dSPeter Maydell #include "qemu/osdep.h" 254771d756SPaolo Bonzini #include "qemu-common.h" 264771d756SPaolo Bonzini #include "cpu.h" 2753018216SPaolo Bonzini #include "hw/hw.h" 280d09e41aSPaolo Bonzini #include "hw/ppc/ppc.h" 292b927571SAndreas Färber #include "hw/ppc/ppc_e500.h" 3053018216SPaolo Bonzini #include "qemu/timer.h" 3153018216SPaolo Bonzini #include "sysemu/sysemu.h" 320ce470cdSAlexey Kardashevskiy #include "sysemu/cpus.h" 330d09e41aSPaolo Bonzini #include "hw/timer/m48t59.h" 3453018216SPaolo Bonzini #include "qemu/log.h" 3598a8b524SAlexey Kardashevskiy #include "qemu/error-report.h" 3653018216SPaolo Bonzini #include "hw/loader.h" 3753018216SPaolo Bonzini #include "sysemu/kvm.h" 3853018216SPaolo Bonzini #include "kvm_ppc.h" 3998a8b524SAlexey Kardashevskiy #include "trace.h" 4053018216SPaolo Bonzini 4153018216SPaolo Bonzini //#define PPC_DEBUG_IRQ 4253018216SPaolo Bonzini //#define PPC_DEBUG_TB 4353018216SPaolo Bonzini 4453018216SPaolo Bonzini #ifdef PPC_DEBUG_IRQ 4553018216SPaolo Bonzini # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 4653018216SPaolo Bonzini #else 4753018216SPaolo Bonzini # define LOG_IRQ(...) do { } while (0) 4853018216SPaolo Bonzini #endif 4953018216SPaolo Bonzini 5053018216SPaolo Bonzini 5153018216SPaolo Bonzini #ifdef PPC_DEBUG_TB 5253018216SPaolo Bonzini # define LOG_TB(...) qemu_log(__VA_ARGS__) 5353018216SPaolo Bonzini #else 5453018216SPaolo Bonzini # define LOG_TB(...) do { } while (0) 5553018216SPaolo Bonzini #endif 5653018216SPaolo Bonzini 5753018216SPaolo Bonzini static void cpu_ppc_tb_stop (CPUPPCState *env); 5853018216SPaolo Bonzini static void cpu_ppc_tb_start (CPUPPCState *env); 5953018216SPaolo Bonzini 6053018216SPaolo Bonzini void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 6153018216SPaolo Bonzini { 62d8ed887bSAndreas Färber CPUState *cs = CPU(cpu); 6353018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 6453018216SPaolo Bonzini unsigned int old_pending = env->pending_interrupts; 6553018216SPaolo Bonzini 6653018216SPaolo Bonzini if (level) { 6753018216SPaolo Bonzini env->pending_interrupts |= 1 << n_IRQ; 68c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_HARD); 6953018216SPaolo Bonzini } else { 7053018216SPaolo Bonzini env->pending_interrupts &= ~(1 << n_IRQ); 71d8ed887bSAndreas Färber if (env->pending_interrupts == 0) { 72d8ed887bSAndreas Färber cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 73d8ed887bSAndreas Färber } 7453018216SPaolo Bonzini } 7553018216SPaolo Bonzini 7653018216SPaolo Bonzini if (old_pending != env->pending_interrupts) { 7753018216SPaolo Bonzini #ifdef CONFIG_KVM 7853018216SPaolo Bonzini kvmppc_set_interrupt(cpu, n_IRQ, level); 7953018216SPaolo Bonzini #endif 8053018216SPaolo Bonzini } 8153018216SPaolo Bonzini 8253018216SPaolo Bonzini LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 8353018216SPaolo Bonzini "req %08x\n", __func__, env, n_IRQ, level, 84259186a7SAndreas Färber env->pending_interrupts, CPU(cpu)->interrupt_request); 8553018216SPaolo Bonzini } 8653018216SPaolo Bonzini 8753018216SPaolo Bonzini /* PowerPC 6xx / 7xx internal IRQ controller */ 8853018216SPaolo Bonzini static void ppc6xx_set_irq(void *opaque, int pin, int level) 8953018216SPaolo Bonzini { 9053018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 9153018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 9253018216SPaolo Bonzini int cur_level; 9353018216SPaolo Bonzini 9453018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 9553018216SPaolo Bonzini env, pin, level); 9653018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 9753018216SPaolo Bonzini /* Don't generate spurious events */ 9853018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 99259186a7SAndreas Färber CPUState *cs = CPU(cpu); 100259186a7SAndreas Färber 10153018216SPaolo Bonzini switch (pin) { 10253018216SPaolo Bonzini case PPC6xx_INPUT_TBEN: 10353018216SPaolo Bonzini /* Level sensitive - active high */ 10453018216SPaolo Bonzini LOG_IRQ("%s: %s the time base\n", 10553018216SPaolo Bonzini __func__, level ? "start" : "stop"); 10653018216SPaolo Bonzini if (level) { 10753018216SPaolo Bonzini cpu_ppc_tb_start(env); 10853018216SPaolo Bonzini } else { 10953018216SPaolo Bonzini cpu_ppc_tb_stop(env); 11053018216SPaolo Bonzini } 11153018216SPaolo Bonzini case PPC6xx_INPUT_INT: 11253018216SPaolo Bonzini /* Level sensitive - active high */ 11353018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 11453018216SPaolo Bonzini __func__, level); 11553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 11653018216SPaolo Bonzini break; 11753018216SPaolo Bonzini case PPC6xx_INPUT_SMI: 11853018216SPaolo Bonzini /* Level sensitive - active high */ 11953018216SPaolo Bonzini LOG_IRQ("%s: set the SMI IRQ state to %d\n", 12053018216SPaolo Bonzini __func__, level); 12153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 12253018216SPaolo Bonzini break; 12353018216SPaolo Bonzini case PPC6xx_INPUT_MCP: 12453018216SPaolo Bonzini /* Negative edge sensitive */ 12553018216SPaolo Bonzini /* XXX: TODO: actual reaction may depends on HID0 status 12653018216SPaolo Bonzini * 603/604/740/750: check HID0[EMCP] 12753018216SPaolo Bonzini */ 12853018216SPaolo Bonzini if (cur_level == 1 && level == 0) { 12953018216SPaolo Bonzini LOG_IRQ("%s: raise machine check state\n", 13053018216SPaolo Bonzini __func__); 13153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 13253018216SPaolo Bonzini } 13353018216SPaolo Bonzini break; 13453018216SPaolo Bonzini case PPC6xx_INPUT_CKSTP_IN: 13553018216SPaolo Bonzini /* Level sensitive - active low */ 13653018216SPaolo Bonzini /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 13753018216SPaolo Bonzini /* XXX: Note that the only way to restart the CPU is to reset it */ 13853018216SPaolo Bonzini if (level) { 13953018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 140259186a7SAndreas Färber cs->halted = 1; 14153018216SPaolo Bonzini } 14253018216SPaolo Bonzini break; 14353018216SPaolo Bonzini case PPC6xx_INPUT_HRESET: 14453018216SPaolo Bonzini /* Level sensitive - active low */ 14553018216SPaolo Bonzini if (level) { 14653018216SPaolo Bonzini LOG_IRQ("%s: reset the CPU\n", __func__); 147c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_RESET); 14853018216SPaolo Bonzini } 14953018216SPaolo Bonzini break; 15053018216SPaolo Bonzini case PPC6xx_INPUT_SRESET: 15153018216SPaolo Bonzini LOG_IRQ("%s: set the RESET IRQ state to %d\n", 15253018216SPaolo Bonzini __func__, level); 15353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 15453018216SPaolo Bonzini break; 15553018216SPaolo Bonzini default: 15653018216SPaolo Bonzini /* Unknown pin - do nothing */ 15753018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 15853018216SPaolo Bonzini return; 15953018216SPaolo Bonzini } 16053018216SPaolo Bonzini if (level) 16153018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 16253018216SPaolo Bonzini else 16353018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 16453018216SPaolo Bonzini } 16553018216SPaolo Bonzini } 16653018216SPaolo Bonzini 167aa5a9e24SPaolo Bonzini void ppc6xx_irq_init(PowerPCCPU *cpu) 16853018216SPaolo Bonzini { 169aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 17053018216SPaolo Bonzini 17153018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 17253018216SPaolo Bonzini PPC6xx_INPUT_NB); 17353018216SPaolo Bonzini } 17453018216SPaolo Bonzini 17553018216SPaolo Bonzini #if defined(TARGET_PPC64) 17653018216SPaolo Bonzini /* PowerPC 970 internal IRQ controller */ 17753018216SPaolo Bonzini static void ppc970_set_irq(void *opaque, int pin, int level) 17853018216SPaolo Bonzini { 17953018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 18053018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 18153018216SPaolo Bonzini int cur_level; 18253018216SPaolo Bonzini 18353018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 18453018216SPaolo Bonzini env, pin, level); 18553018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 18653018216SPaolo Bonzini /* Don't generate spurious events */ 18753018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 188259186a7SAndreas Färber CPUState *cs = CPU(cpu); 189259186a7SAndreas Färber 19053018216SPaolo Bonzini switch (pin) { 19153018216SPaolo Bonzini case PPC970_INPUT_INT: 19253018216SPaolo Bonzini /* Level sensitive - active high */ 19353018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 19453018216SPaolo Bonzini __func__, level); 19553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 19653018216SPaolo Bonzini break; 19753018216SPaolo Bonzini case PPC970_INPUT_THINT: 19853018216SPaolo Bonzini /* Level sensitive - active high */ 19953018216SPaolo Bonzini LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 20053018216SPaolo Bonzini level); 20153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 20253018216SPaolo Bonzini break; 20353018216SPaolo Bonzini case PPC970_INPUT_MCP: 20453018216SPaolo Bonzini /* Negative edge sensitive */ 20553018216SPaolo Bonzini /* XXX: TODO: actual reaction may depends on HID0 status 20653018216SPaolo Bonzini * 603/604/740/750: check HID0[EMCP] 20753018216SPaolo Bonzini */ 20853018216SPaolo Bonzini if (cur_level == 1 && level == 0) { 20953018216SPaolo Bonzini LOG_IRQ("%s: raise machine check state\n", 21053018216SPaolo Bonzini __func__); 21153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 21253018216SPaolo Bonzini } 21353018216SPaolo Bonzini break; 21453018216SPaolo Bonzini case PPC970_INPUT_CKSTP: 21553018216SPaolo Bonzini /* Level sensitive - active low */ 21653018216SPaolo Bonzini /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 21753018216SPaolo Bonzini if (level) { 21853018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 219259186a7SAndreas Färber cs->halted = 1; 22053018216SPaolo Bonzini } else { 22153018216SPaolo Bonzini LOG_IRQ("%s: restart the CPU\n", __func__); 222259186a7SAndreas Färber cs->halted = 0; 223259186a7SAndreas Färber qemu_cpu_kick(cs); 22453018216SPaolo Bonzini } 22553018216SPaolo Bonzini break; 22653018216SPaolo Bonzini case PPC970_INPUT_HRESET: 22753018216SPaolo Bonzini /* Level sensitive - active low */ 22853018216SPaolo Bonzini if (level) { 229c3affe56SAndreas Färber cpu_interrupt(cs, CPU_INTERRUPT_RESET); 23053018216SPaolo Bonzini } 23153018216SPaolo Bonzini break; 23253018216SPaolo Bonzini case PPC970_INPUT_SRESET: 23353018216SPaolo Bonzini LOG_IRQ("%s: set the RESET IRQ state to %d\n", 23453018216SPaolo Bonzini __func__, level); 23553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 23653018216SPaolo Bonzini break; 23753018216SPaolo Bonzini case PPC970_INPUT_TBEN: 23853018216SPaolo Bonzini LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 23953018216SPaolo Bonzini level); 24053018216SPaolo Bonzini /* XXX: TODO */ 24153018216SPaolo Bonzini break; 24253018216SPaolo Bonzini default: 24353018216SPaolo Bonzini /* Unknown pin - do nothing */ 24453018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 24553018216SPaolo Bonzini return; 24653018216SPaolo Bonzini } 24753018216SPaolo Bonzini if (level) 24853018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 24953018216SPaolo Bonzini else 25053018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 25153018216SPaolo Bonzini } 25253018216SPaolo Bonzini } 25353018216SPaolo Bonzini 254aa5a9e24SPaolo Bonzini void ppc970_irq_init(PowerPCCPU *cpu) 25553018216SPaolo Bonzini { 256aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 25753018216SPaolo Bonzini 25853018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 25953018216SPaolo Bonzini PPC970_INPUT_NB); 26053018216SPaolo Bonzini } 26153018216SPaolo Bonzini 26253018216SPaolo Bonzini /* POWER7 internal IRQ controller */ 26353018216SPaolo Bonzini static void power7_set_irq(void *opaque, int pin, int level) 26453018216SPaolo Bonzini { 26553018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 26653018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 26753018216SPaolo Bonzini 26853018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 26953018216SPaolo Bonzini env, pin, level); 27053018216SPaolo Bonzini 27153018216SPaolo Bonzini switch (pin) { 27253018216SPaolo Bonzini case POWER7_INPUT_INT: 27353018216SPaolo Bonzini /* Level sensitive - active high */ 27453018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 27553018216SPaolo Bonzini __func__, level); 27653018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 27753018216SPaolo Bonzini break; 27853018216SPaolo Bonzini default: 27953018216SPaolo Bonzini /* Unknown pin - do nothing */ 28053018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 28153018216SPaolo Bonzini return; 28253018216SPaolo Bonzini } 28353018216SPaolo Bonzini if (level) { 28453018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 28553018216SPaolo Bonzini } else { 28653018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 28753018216SPaolo Bonzini } 28853018216SPaolo Bonzini } 28953018216SPaolo Bonzini 290aa5a9e24SPaolo Bonzini void ppcPOWER7_irq_init(PowerPCCPU *cpu) 29153018216SPaolo Bonzini { 292aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 29353018216SPaolo Bonzini 29453018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 29553018216SPaolo Bonzini POWER7_INPUT_NB); 29653018216SPaolo Bonzini } 29753018216SPaolo Bonzini #endif /* defined(TARGET_PPC64) */ 29853018216SPaolo Bonzini 29953018216SPaolo Bonzini /* PowerPC 40x internal IRQ controller */ 30053018216SPaolo Bonzini static void ppc40x_set_irq(void *opaque, int pin, int level) 30153018216SPaolo Bonzini { 30253018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 30353018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 30453018216SPaolo Bonzini int cur_level; 30553018216SPaolo Bonzini 30653018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 30753018216SPaolo Bonzini env, pin, level); 30853018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 30953018216SPaolo Bonzini /* Don't generate spurious events */ 31053018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 311259186a7SAndreas Färber CPUState *cs = CPU(cpu); 312259186a7SAndreas Färber 31353018216SPaolo Bonzini switch (pin) { 31453018216SPaolo Bonzini case PPC40x_INPUT_RESET_SYS: 31553018216SPaolo Bonzini if (level) { 31653018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC system\n", 31753018216SPaolo Bonzini __func__); 31853018216SPaolo Bonzini ppc40x_system_reset(cpu); 31953018216SPaolo Bonzini } 32053018216SPaolo Bonzini break; 32153018216SPaolo Bonzini case PPC40x_INPUT_RESET_CHIP: 32253018216SPaolo Bonzini if (level) { 32353018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 32453018216SPaolo Bonzini ppc40x_chip_reset(cpu); 32553018216SPaolo Bonzini } 32653018216SPaolo Bonzini break; 32753018216SPaolo Bonzini case PPC40x_INPUT_RESET_CORE: 32853018216SPaolo Bonzini /* XXX: TODO: update DBSR[MRR] */ 32953018216SPaolo Bonzini if (level) { 33053018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC core\n", __func__); 33153018216SPaolo Bonzini ppc40x_core_reset(cpu); 33253018216SPaolo Bonzini } 33353018216SPaolo Bonzini break; 33453018216SPaolo Bonzini case PPC40x_INPUT_CINT: 33553018216SPaolo Bonzini /* Level sensitive - active high */ 33653018216SPaolo Bonzini LOG_IRQ("%s: set the critical IRQ state to %d\n", 33753018216SPaolo Bonzini __func__, level); 33853018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 33953018216SPaolo Bonzini break; 34053018216SPaolo Bonzini case PPC40x_INPUT_INT: 34153018216SPaolo Bonzini /* Level sensitive - active high */ 34253018216SPaolo Bonzini LOG_IRQ("%s: set the external IRQ state to %d\n", 34353018216SPaolo Bonzini __func__, level); 34453018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 34553018216SPaolo Bonzini break; 34653018216SPaolo Bonzini case PPC40x_INPUT_HALT: 34753018216SPaolo Bonzini /* Level sensitive - active low */ 34853018216SPaolo Bonzini if (level) { 34953018216SPaolo Bonzini LOG_IRQ("%s: stop the CPU\n", __func__); 350259186a7SAndreas Färber cs->halted = 1; 35153018216SPaolo Bonzini } else { 35253018216SPaolo Bonzini LOG_IRQ("%s: restart the CPU\n", __func__); 353259186a7SAndreas Färber cs->halted = 0; 354259186a7SAndreas Färber qemu_cpu_kick(cs); 35553018216SPaolo Bonzini } 35653018216SPaolo Bonzini break; 35753018216SPaolo Bonzini case PPC40x_INPUT_DEBUG: 35853018216SPaolo Bonzini /* Level sensitive - active high */ 35953018216SPaolo Bonzini LOG_IRQ("%s: set the debug pin state to %d\n", 36053018216SPaolo Bonzini __func__, level); 36153018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 36253018216SPaolo Bonzini break; 36353018216SPaolo Bonzini default: 36453018216SPaolo Bonzini /* Unknown pin - do nothing */ 36553018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 36653018216SPaolo Bonzini return; 36753018216SPaolo Bonzini } 36853018216SPaolo Bonzini if (level) 36953018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 37053018216SPaolo Bonzini else 37153018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 37253018216SPaolo Bonzini } 37353018216SPaolo Bonzini } 37453018216SPaolo Bonzini 375aa5a9e24SPaolo Bonzini void ppc40x_irq_init(PowerPCCPU *cpu) 37653018216SPaolo Bonzini { 377aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 37853018216SPaolo Bonzini 37953018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 38053018216SPaolo Bonzini cpu, PPC40x_INPUT_NB); 38153018216SPaolo Bonzini } 38253018216SPaolo Bonzini 38353018216SPaolo Bonzini /* PowerPC E500 internal IRQ controller */ 38453018216SPaolo Bonzini static void ppce500_set_irq(void *opaque, int pin, int level) 38553018216SPaolo Bonzini { 38653018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 38753018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 38853018216SPaolo Bonzini int cur_level; 38953018216SPaolo Bonzini 39053018216SPaolo Bonzini LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 39153018216SPaolo Bonzini env, pin, level); 39253018216SPaolo Bonzini cur_level = (env->irq_input_state >> pin) & 1; 39353018216SPaolo Bonzini /* Don't generate spurious events */ 39453018216SPaolo Bonzini if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 39553018216SPaolo Bonzini switch (pin) { 39653018216SPaolo Bonzini case PPCE500_INPUT_MCK: 39753018216SPaolo Bonzini if (level) { 39853018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC system\n", 39953018216SPaolo Bonzini __func__); 40053018216SPaolo Bonzini qemu_system_reset_request(); 40153018216SPaolo Bonzini } 40253018216SPaolo Bonzini break; 40353018216SPaolo Bonzini case PPCE500_INPUT_RESET_CORE: 40453018216SPaolo Bonzini if (level) { 40553018216SPaolo Bonzini LOG_IRQ("%s: reset the PowerPC core\n", __func__); 40653018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 40753018216SPaolo Bonzini } 40853018216SPaolo Bonzini break; 40953018216SPaolo Bonzini case PPCE500_INPUT_CINT: 41053018216SPaolo Bonzini /* Level sensitive - active high */ 41153018216SPaolo Bonzini LOG_IRQ("%s: set the critical IRQ state to %d\n", 41253018216SPaolo Bonzini __func__, level); 41353018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 41453018216SPaolo Bonzini break; 41553018216SPaolo Bonzini case PPCE500_INPUT_INT: 41653018216SPaolo Bonzini /* Level sensitive - active high */ 41753018216SPaolo Bonzini LOG_IRQ("%s: set the core IRQ state to %d\n", 41853018216SPaolo Bonzini __func__, level); 41953018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 42053018216SPaolo Bonzini break; 42153018216SPaolo Bonzini case PPCE500_INPUT_DEBUG: 42253018216SPaolo Bonzini /* Level sensitive - active high */ 42353018216SPaolo Bonzini LOG_IRQ("%s: set the debug pin state to %d\n", 42453018216SPaolo Bonzini __func__, level); 42553018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 42653018216SPaolo Bonzini break; 42753018216SPaolo Bonzini default: 42853018216SPaolo Bonzini /* Unknown pin - do nothing */ 42953018216SPaolo Bonzini LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 43053018216SPaolo Bonzini return; 43153018216SPaolo Bonzini } 43253018216SPaolo Bonzini if (level) 43353018216SPaolo Bonzini env->irq_input_state |= 1 << pin; 43453018216SPaolo Bonzini else 43553018216SPaolo Bonzini env->irq_input_state &= ~(1 << pin); 43653018216SPaolo Bonzini } 43753018216SPaolo Bonzini } 43853018216SPaolo Bonzini 439aa5a9e24SPaolo Bonzini void ppce500_irq_init(PowerPCCPU *cpu) 44053018216SPaolo Bonzini { 441aa5a9e24SPaolo Bonzini CPUPPCState *env = &cpu->env; 44253018216SPaolo Bonzini 44353018216SPaolo Bonzini env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 44453018216SPaolo Bonzini cpu, PPCE500_INPUT_NB); 44553018216SPaolo Bonzini } 44653018216SPaolo Bonzini 44753018216SPaolo Bonzini /* Enable or Disable the E500 EPR capability */ 44853018216SPaolo Bonzini void ppce500_set_mpic_proxy(bool enabled) 44953018216SPaolo Bonzini { 450182735efSAndreas Färber CPUState *cs; 45153018216SPaolo Bonzini 452bdc44640SAndreas Färber CPU_FOREACH(cs) { 453182735efSAndreas Färber PowerPCCPU *cpu = POWERPC_CPU(cs); 45453018216SPaolo Bonzini 455182735efSAndreas Färber cpu->env.mpic_proxy = enabled; 45653018216SPaolo Bonzini if (kvm_enabled()) { 457182735efSAndreas Färber kvmppc_set_mpic_proxy(cpu, enabled); 45853018216SPaolo Bonzini } 45953018216SPaolo Bonzini } 46053018216SPaolo Bonzini } 46153018216SPaolo Bonzini 46253018216SPaolo Bonzini /*****************************************************************************/ 46353018216SPaolo Bonzini /* PowerPC time base and decrementer emulation */ 46453018216SPaolo Bonzini 46553018216SPaolo Bonzini uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 46653018216SPaolo Bonzini { 46753018216SPaolo Bonzini /* TB time in tb periods */ 46873bcb24dSRutuja Shah return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 46953018216SPaolo Bonzini } 47053018216SPaolo Bonzini 47153018216SPaolo Bonzini uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 47253018216SPaolo Bonzini { 47353018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 47453018216SPaolo Bonzini uint64_t tb; 47553018216SPaolo Bonzini 47653018216SPaolo Bonzini if (kvm_enabled()) { 47753018216SPaolo Bonzini return env->spr[SPR_TBL]; 47853018216SPaolo Bonzini } 47953018216SPaolo Bonzini 480bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 48153018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 48253018216SPaolo Bonzini 48353018216SPaolo Bonzini return tb; 48453018216SPaolo Bonzini } 48553018216SPaolo Bonzini 48653018216SPaolo Bonzini static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 48753018216SPaolo Bonzini { 48853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 48953018216SPaolo Bonzini uint64_t tb; 49053018216SPaolo Bonzini 491bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 49253018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 49353018216SPaolo Bonzini 49453018216SPaolo Bonzini return tb >> 32; 49553018216SPaolo Bonzini } 49653018216SPaolo Bonzini 49753018216SPaolo Bonzini uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 49853018216SPaolo Bonzini { 49953018216SPaolo Bonzini if (kvm_enabled()) { 50053018216SPaolo Bonzini return env->spr[SPR_TBU]; 50153018216SPaolo Bonzini } 50253018216SPaolo Bonzini 50353018216SPaolo Bonzini return _cpu_ppc_load_tbu(env); 50453018216SPaolo Bonzini } 50553018216SPaolo Bonzini 50653018216SPaolo Bonzini static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 50753018216SPaolo Bonzini int64_t *tb_offsetp, uint64_t value) 50853018216SPaolo Bonzini { 50973bcb24dSRutuja Shah *tb_offsetp = value - 51073bcb24dSRutuja Shah muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 51173bcb24dSRutuja Shah 51253018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 51353018216SPaolo Bonzini __func__, value, *tb_offsetp); 51453018216SPaolo Bonzini } 51553018216SPaolo Bonzini 51653018216SPaolo Bonzini void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 51753018216SPaolo Bonzini { 51853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 51953018216SPaolo Bonzini uint64_t tb; 52053018216SPaolo Bonzini 521bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 52253018216SPaolo Bonzini tb &= 0xFFFFFFFF00000000ULL; 523bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 52453018216SPaolo Bonzini &tb_env->tb_offset, tb | (uint64_t)value); 52553018216SPaolo Bonzini } 52653018216SPaolo Bonzini 52753018216SPaolo Bonzini static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 52853018216SPaolo Bonzini { 52953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 53053018216SPaolo Bonzini uint64_t tb; 53153018216SPaolo Bonzini 532bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 53353018216SPaolo Bonzini tb &= 0x00000000FFFFFFFFULL; 534bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 53553018216SPaolo Bonzini &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 53653018216SPaolo Bonzini } 53753018216SPaolo Bonzini 53853018216SPaolo Bonzini void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 53953018216SPaolo Bonzini { 54053018216SPaolo Bonzini _cpu_ppc_store_tbu(env, value); 54153018216SPaolo Bonzini } 54253018216SPaolo Bonzini 54353018216SPaolo Bonzini uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 54453018216SPaolo Bonzini { 54553018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 54653018216SPaolo Bonzini uint64_t tb; 54753018216SPaolo Bonzini 548bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 54953018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 55053018216SPaolo Bonzini 55153018216SPaolo Bonzini return tb; 55253018216SPaolo Bonzini } 55353018216SPaolo Bonzini 55453018216SPaolo Bonzini uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 55553018216SPaolo Bonzini { 55653018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 55753018216SPaolo Bonzini uint64_t tb; 55853018216SPaolo Bonzini 559bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 56053018216SPaolo Bonzini LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 56153018216SPaolo Bonzini 56253018216SPaolo Bonzini return tb >> 32; 56353018216SPaolo Bonzini } 56453018216SPaolo Bonzini 56553018216SPaolo Bonzini void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 56653018216SPaolo Bonzini { 56753018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 56853018216SPaolo Bonzini uint64_t tb; 56953018216SPaolo Bonzini 570bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 57153018216SPaolo Bonzini tb &= 0xFFFFFFFF00000000ULL; 572bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 57353018216SPaolo Bonzini &tb_env->atb_offset, tb | (uint64_t)value); 57453018216SPaolo Bonzini } 57553018216SPaolo Bonzini 57653018216SPaolo Bonzini void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 57753018216SPaolo Bonzini { 57853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 57953018216SPaolo Bonzini uint64_t tb; 58053018216SPaolo Bonzini 581bc72ad67SAlex Bligh tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 58253018216SPaolo Bonzini tb &= 0x00000000FFFFFFFFULL; 583bc72ad67SAlex Bligh cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 58453018216SPaolo Bonzini &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 58553018216SPaolo Bonzini } 58653018216SPaolo Bonzini 58753018216SPaolo Bonzini static void cpu_ppc_tb_stop (CPUPPCState *env) 58853018216SPaolo Bonzini { 58953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 59053018216SPaolo Bonzini uint64_t tb, atb, vmclk; 59153018216SPaolo Bonzini 59253018216SPaolo Bonzini /* If the time base is already frozen, do nothing */ 59353018216SPaolo Bonzini if (tb_env->tb_freq != 0) { 594bc72ad67SAlex Bligh vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 59553018216SPaolo Bonzini /* Get the time base */ 59653018216SPaolo Bonzini tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 59753018216SPaolo Bonzini /* Get the alternate time base */ 59853018216SPaolo Bonzini atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 59953018216SPaolo Bonzini /* Store the time base value (ie compute the current offset) */ 60053018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 60153018216SPaolo Bonzini /* Store the alternate time base value (compute the current offset) */ 60253018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 60353018216SPaolo Bonzini /* Set the time base frequency to zero */ 60453018216SPaolo Bonzini tb_env->tb_freq = 0; 60553018216SPaolo Bonzini /* Now, the time bases are frozen to tb_offset / atb_offset value */ 60653018216SPaolo Bonzini } 60753018216SPaolo Bonzini } 60853018216SPaolo Bonzini 60953018216SPaolo Bonzini static void cpu_ppc_tb_start (CPUPPCState *env) 61053018216SPaolo Bonzini { 61153018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 61253018216SPaolo Bonzini uint64_t tb, atb, vmclk; 61353018216SPaolo Bonzini 61453018216SPaolo Bonzini /* If the time base is not frozen, do nothing */ 61553018216SPaolo Bonzini if (tb_env->tb_freq == 0) { 616bc72ad67SAlex Bligh vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 61753018216SPaolo Bonzini /* Get the time base from tb_offset */ 61853018216SPaolo Bonzini tb = tb_env->tb_offset; 61953018216SPaolo Bonzini /* Get the alternate time base from atb_offset */ 62053018216SPaolo Bonzini atb = tb_env->atb_offset; 62153018216SPaolo Bonzini /* Restore the tb frequency from the decrementer frequency */ 62253018216SPaolo Bonzini tb_env->tb_freq = tb_env->decr_freq; 62353018216SPaolo Bonzini /* Store the time base value */ 62453018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 62553018216SPaolo Bonzini /* Store the alternate time base value */ 62653018216SPaolo Bonzini cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 62753018216SPaolo Bonzini } 62853018216SPaolo Bonzini } 62953018216SPaolo Bonzini 630e81a982aSAlexander Graf bool ppc_decr_clear_on_delivery(CPUPPCState *env) 631e81a982aSAlexander Graf { 632e81a982aSAlexander Graf ppc_tb_t *tb_env = env->tb_env; 633e81a982aSAlexander Graf int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 634e81a982aSAlexander Graf return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 635e81a982aSAlexander Graf } 636e81a982aSAlexander Graf 63753018216SPaolo Bonzini static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 63853018216SPaolo Bonzini { 63953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 64053018216SPaolo Bonzini uint32_t decr; 64153018216SPaolo Bonzini int64_t diff; 64253018216SPaolo Bonzini 643bc72ad67SAlex Bligh diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 64453018216SPaolo Bonzini if (diff >= 0) { 64573bcb24dSRutuja Shah decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 64653018216SPaolo Bonzini } else if (tb_env->flags & PPC_TIMER_BOOKE) { 64753018216SPaolo Bonzini decr = 0; 64853018216SPaolo Bonzini } else { 64973bcb24dSRutuja Shah decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 65053018216SPaolo Bonzini } 65153018216SPaolo Bonzini LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); 65253018216SPaolo Bonzini 65353018216SPaolo Bonzini return decr; 65453018216SPaolo Bonzini } 65553018216SPaolo Bonzini 65653018216SPaolo Bonzini uint32_t cpu_ppc_load_decr (CPUPPCState *env) 65753018216SPaolo Bonzini { 65853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 65953018216SPaolo Bonzini 66053018216SPaolo Bonzini if (kvm_enabled()) { 66153018216SPaolo Bonzini return env->spr[SPR_DECR]; 66253018216SPaolo Bonzini } 66353018216SPaolo Bonzini 66453018216SPaolo Bonzini return _cpu_ppc_load_decr(env, tb_env->decr_next); 66553018216SPaolo Bonzini } 66653018216SPaolo Bonzini 66753018216SPaolo Bonzini uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) 66853018216SPaolo Bonzini { 66953018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 67053018216SPaolo Bonzini 67153018216SPaolo Bonzini return _cpu_ppc_load_decr(env, tb_env->hdecr_next); 67253018216SPaolo Bonzini } 67353018216SPaolo Bonzini 67453018216SPaolo Bonzini uint64_t cpu_ppc_load_purr (CPUPPCState *env) 67553018216SPaolo Bonzini { 67653018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 67753018216SPaolo Bonzini uint64_t diff; 67853018216SPaolo Bonzini 679bc72ad67SAlex Bligh diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; 68053018216SPaolo Bonzini 68173bcb24dSRutuja Shah return tb_env->purr_load + 68273bcb24dSRutuja Shah muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 68353018216SPaolo Bonzini } 68453018216SPaolo Bonzini 68553018216SPaolo Bonzini /* When decrementer expires, 68653018216SPaolo Bonzini * all we need to do is generate or queue a CPU exception 68753018216SPaolo Bonzini */ 68853018216SPaolo Bonzini static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 68953018216SPaolo Bonzini { 69053018216SPaolo Bonzini /* Raise it */ 69153018216SPaolo Bonzini LOG_TB("raise decrementer exception\n"); 69253018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 69353018216SPaolo Bonzini } 69453018216SPaolo Bonzini 695e81a982aSAlexander Graf static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 696e81a982aSAlexander Graf { 697e81a982aSAlexander Graf ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 698e81a982aSAlexander Graf } 699e81a982aSAlexander Graf 70053018216SPaolo Bonzini static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 70153018216SPaolo Bonzini { 702*4b236b62SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 703*4b236b62SBenjamin Herrenschmidt 70453018216SPaolo Bonzini /* Raise it */ 705*4b236b62SBenjamin Herrenschmidt LOG_TB("raise hv decrementer exception\n"); 706*4b236b62SBenjamin Herrenschmidt 707*4b236b62SBenjamin Herrenschmidt /* The architecture specifies that we don't deliver HDEC 708*4b236b62SBenjamin Herrenschmidt * interrupts in a PM state. Not only they don't cause a 709*4b236b62SBenjamin Herrenschmidt * wakeup but they also get effectively discarded. 710*4b236b62SBenjamin Herrenschmidt */ 711*4b236b62SBenjamin Herrenschmidt if (!env->in_pm_state) { 71253018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 71353018216SPaolo Bonzini } 714*4b236b62SBenjamin Herrenschmidt } 71553018216SPaolo Bonzini 716e81a982aSAlexander Graf static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 717e81a982aSAlexander Graf { 718e81a982aSAlexander Graf ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 719e81a982aSAlexander Graf } 720e81a982aSAlexander Graf 72153018216SPaolo Bonzini static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 7221246b259SStefan Weil QEMUTimer *timer, 723e81a982aSAlexander Graf void (*raise_excp)(void *), 724e81a982aSAlexander Graf void (*lower_excp)(PowerPCCPU *), 725e81a982aSAlexander Graf uint32_t decr, uint32_t value) 72653018216SPaolo Bonzini { 72753018216SPaolo Bonzini CPUPPCState *env = &cpu->env; 72853018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 72953018216SPaolo Bonzini uint64_t now, next; 73053018216SPaolo Bonzini 73153018216SPaolo Bonzini LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, 73253018216SPaolo Bonzini decr, value); 73353018216SPaolo Bonzini 73453018216SPaolo Bonzini if (kvm_enabled()) { 73553018216SPaolo Bonzini /* KVM handles decrementer exceptions, we don't need our own timer */ 73653018216SPaolo Bonzini return; 73753018216SPaolo Bonzini } 73853018216SPaolo Bonzini 739e81a982aSAlexander Graf /* 740e81a982aSAlexander Graf * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 741e81a982aSAlexander Graf * interrupt. 742e81a982aSAlexander Graf * 743e81a982aSAlexander Graf * If we get a really small DEC value, we can assume that by the time we 744e81a982aSAlexander Graf * handled it we should inject an interrupt already. 745e81a982aSAlexander Graf * 746e81a982aSAlexander Graf * On MSB level based DEC implementations the MSB always means the interrupt 747e81a982aSAlexander Graf * is pending, so raise it on those. 748e81a982aSAlexander Graf * 749e81a982aSAlexander Graf * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 750e81a982aSAlexander Graf * an edge interrupt, so raise it here too. 751e81a982aSAlexander Graf */ 752e81a982aSAlexander Graf if ((value < 3) || 753e81a982aSAlexander Graf ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) || 754e81a982aSAlexander Graf ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000) 755e81a982aSAlexander Graf && !(decr & 0x80000000))) { 756e81a982aSAlexander Graf (*raise_excp)(cpu); 757e81a982aSAlexander Graf return; 758e81a982aSAlexander Graf } 759e81a982aSAlexander Graf 760e81a982aSAlexander Graf /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 761e81a982aSAlexander Graf if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 762e81a982aSAlexander Graf (*lower_excp)(cpu); 763e81a982aSAlexander Graf } 764e81a982aSAlexander Graf 765e81a982aSAlexander Graf /* Calculate the next timer event */ 766bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 76773bcb24dSRutuja Shah next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 76853018216SPaolo Bonzini *nextp = next; 769e81a982aSAlexander Graf 77053018216SPaolo Bonzini /* Adjust timer */ 771bc72ad67SAlex Bligh timer_mod(timer, next); 77253018216SPaolo Bonzini } 77353018216SPaolo Bonzini 77453018216SPaolo Bonzini static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr, 775e81a982aSAlexander Graf uint32_t value) 77653018216SPaolo Bonzini { 77753018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 77853018216SPaolo Bonzini 77953018216SPaolo Bonzini __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 780e81a982aSAlexander Graf tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 781e81a982aSAlexander Graf value); 78253018216SPaolo Bonzini } 78353018216SPaolo Bonzini 78453018216SPaolo Bonzini void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) 78553018216SPaolo Bonzini { 78653018216SPaolo Bonzini PowerPCCPU *cpu = ppc_env_get_cpu(env); 78753018216SPaolo Bonzini 788e81a982aSAlexander Graf _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value); 78953018216SPaolo Bonzini } 79053018216SPaolo Bonzini 79153018216SPaolo Bonzini static void cpu_ppc_decr_cb(void *opaque) 79253018216SPaolo Bonzini { 79353018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 79453018216SPaolo Bonzini 795e81a982aSAlexander Graf cpu_ppc_decr_excp(cpu); 79653018216SPaolo Bonzini } 79753018216SPaolo Bonzini 79853018216SPaolo Bonzini static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr, 799e81a982aSAlexander Graf uint32_t value) 80053018216SPaolo Bonzini { 80153018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 80253018216SPaolo Bonzini 80353018216SPaolo Bonzini if (tb_env->hdecr_timer != NULL) { 80453018216SPaolo Bonzini __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 805e81a982aSAlexander Graf tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 806e81a982aSAlexander Graf hdecr, value); 80753018216SPaolo Bonzini } 80853018216SPaolo Bonzini } 80953018216SPaolo Bonzini 81053018216SPaolo Bonzini void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) 81153018216SPaolo Bonzini { 81253018216SPaolo Bonzini PowerPCCPU *cpu = ppc_env_get_cpu(env); 81353018216SPaolo Bonzini 814e81a982aSAlexander Graf _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value); 81553018216SPaolo Bonzini } 81653018216SPaolo Bonzini 81753018216SPaolo Bonzini static void cpu_ppc_hdecr_cb(void *opaque) 81853018216SPaolo Bonzini { 81953018216SPaolo Bonzini PowerPCCPU *cpu = opaque; 82053018216SPaolo Bonzini 821e81a982aSAlexander Graf cpu_ppc_hdecr_excp(cpu); 82253018216SPaolo Bonzini } 82353018216SPaolo Bonzini 82453018216SPaolo Bonzini static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) 82553018216SPaolo Bonzini { 82653018216SPaolo Bonzini ppc_tb_t *tb_env = cpu->env.tb_env; 82753018216SPaolo Bonzini 82853018216SPaolo Bonzini tb_env->purr_load = value; 829bc72ad67SAlex Bligh tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 83053018216SPaolo Bonzini } 83153018216SPaolo Bonzini 83253018216SPaolo Bonzini static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 83353018216SPaolo Bonzini { 83453018216SPaolo Bonzini CPUPPCState *env = opaque; 83553018216SPaolo Bonzini PowerPCCPU *cpu = ppc_env_get_cpu(env); 83653018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 83753018216SPaolo Bonzini 83853018216SPaolo Bonzini tb_env->tb_freq = freq; 83953018216SPaolo Bonzini tb_env->decr_freq = freq; 84053018216SPaolo Bonzini /* There is a bug in Linux 2.4 kernels: 84153018216SPaolo Bonzini * if a decrementer exception is pending when it enables msr_ee at startup, 84253018216SPaolo Bonzini * it's not ready to handle it... 84353018216SPaolo Bonzini */ 844e81a982aSAlexander Graf _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); 845e81a982aSAlexander Graf _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); 84653018216SPaolo Bonzini cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); 84753018216SPaolo Bonzini } 84853018216SPaolo Bonzini 84998a8b524SAlexey Kardashevskiy static void timebase_pre_save(void *opaque) 85098a8b524SAlexey Kardashevskiy { 85198a8b524SAlexey Kardashevskiy PPCTimebase *tb = opaque; 8524a7428c5SChristopher Covington uint64_t ticks = cpu_get_host_ticks(); 85398a8b524SAlexey Kardashevskiy PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 85498a8b524SAlexey Kardashevskiy 85598a8b524SAlexey Kardashevskiy if (!first_ppc_cpu->env.tb_env) { 85698a8b524SAlexey Kardashevskiy error_report("No timebase object"); 85798a8b524SAlexey Kardashevskiy return; 85898a8b524SAlexey Kardashevskiy } 85998a8b524SAlexey Kardashevskiy 86077bad151SPaolo Bonzini tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 86198a8b524SAlexey Kardashevskiy /* 86298a8b524SAlexey Kardashevskiy * tb_offset is only expected to be changed by migration so 86398a8b524SAlexey Kardashevskiy * there is no need to update it from KVM here 86498a8b524SAlexey Kardashevskiy */ 86598a8b524SAlexey Kardashevskiy tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 86698a8b524SAlexey Kardashevskiy } 86798a8b524SAlexey Kardashevskiy 86898a8b524SAlexey Kardashevskiy static int timebase_post_load(void *opaque, int version_id) 86998a8b524SAlexey Kardashevskiy { 87098a8b524SAlexey Kardashevskiy PPCTimebase *tb_remote = opaque; 87198a8b524SAlexey Kardashevskiy CPUState *cpu; 87298a8b524SAlexey Kardashevskiy PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 87398a8b524SAlexey Kardashevskiy int64_t tb_off_adj, tb_off, ns_diff; 87498a8b524SAlexey Kardashevskiy int64_t migration_duration_ns, migration_duration_tb, guest_tb, host_ns; 87598a8b524SAlexey Kardashevskiy unsigned long freq; 87698a8b524SAlexey Kardashevskiy 87798a8b524SAlexey Kardashevskiy if (!first_ppc_cpu->env.tb_env) { 87898a8b524SAlexey Kardashevskiy error_report("No timebase object"); 87998a8b524SAlexey Kardashevskiy return -1; 88098a8b524SAlexey Kardashevskiy } 88198a8b524SAlexey Kardashevskiy 88298a8b524SAlexey Kardashevskiy freq = first_ppc_cpu->env.tb_env->tb_freq; 88398a8b524SAlexey Kardashevskiy /* 88498a8b524SAlexey Kardashevskiy * Calculate timebase on the destination side of migration. 88598a8b524SAlexey Kardashevskiy * The destination timebase must be not less than the source timebase. 88698a8b524SAlexey Kardashevskiy * We try to adjust timebase by downtime if host clocks are not 88798a8b524SAlexey Kardashevskiy * too much out of sync (1 second for now). 88898a8b524SAlexey Kardashevskiy */ 88977bad151SPaolo Bonzini host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 89098a8b524SAlexey Kardashevskiy ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns); 89113566fe3SStefan Hajnoczi migration_duration_ns = MIN(NANOSECONDS_PER_SECOND, ns_diff); 892a2c5eaf7SLaurent Vivier migration_duration_tb = muldiv64(freq, migration_duration_ns, 89313566fe3SStefan Hajnoczi NANOSECONDS_PER_SECOND); 89498a8b524SAlexey Kardashevskiy guest_tb = tb_remote->guest_timebase + MIN(0, migration_duration_tb); 89598a8b524SAlexey Kardashevskiy 8964a7428c5SChristopher Covington tb_off_adj = guest_tb - cpu_get_host_ticks(); 89798a8b524SAlexey Kardashevskiy 89898a8b524SAlexey Kardashevskiy tb_off = first_ppc_cpu->env.tb_env->tb_offset; 89998a8b524SAlexey Kardashevskiy trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 90098a8b524SAlexey Kardashevskiy (tb_off_adj - tb_off) / freq); 90198a8b524SAlexey Kardashevskiy 90298a8b524SAlexey Kardashevskiy /* Set new offset to all CPUs */ 90398a8b524SAlexey Kardashevskiy CPU_FOREACH(cpu) { 90498a8b524SAlexey Kardashevskiy PowerPCCPU *pcpu = POWERPC_CPU(cpu); 90598a8b524SAlexey Kardashevskiy pcpu->env.tb_env->tb_offset = tb_off_adj; 90698a8b524SAlexey Kardashevskiy } 90798a8b524SAlexey Kardashevskiy 90898a8b524SAlexey Kardashevskiy return 0; 90998a8b524SAlexey Kardashevskiy } 91098a8b524SAlexey Kardashevskiy 91198a8b524SAlexey Kardashevskiy const VMStateDescription vmstate_ppc_timebase = { 91298a8b524SAlexey Kardashevskiy .name = "timebase", 91398a8b524SAlexey Kardashevskiy .version_id = 1, 91498a8b524SAlexey Kardashevskiy .minimum_version_id = 1, 91598a8b524SAlexey Kardashevskiy .minimum_version_id_old = 1, 91698a8b524SAlexey Kardashevskiy .pre_save = timebase_pre_save, 91798a8b524SAlexey Kardashevskiy .post_load = timebase_post_load, 91898a8b524SAlexey Kardashevskiy .fields = (VMStateField []) { 91998a8b524SAlexey Kardashevskiy VMSTATE_UINT64(guest_timebase, PPCTimebase), 92098a8b524SAlexey Kardashevskiy VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 92198a8b524SAlexey Kardashevskiy VMSTATE_END_OF_LIST() 92298a8b524SAlexey Kardashevskiy }, 92398a8b524SAlexey Kardashevskiy }; 92498a8b524SAlexey Kardashevskiy 92553018216SPaolo Bonzini /* Set up (once) timebase frequency (in Hz) */ 92653018216SPaolo Bonzini clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 92753018216SPaolo Bonzini { 92853018216SPaolo Bonzini PowerPCCPU *cpu = ppc_env_get_cpu(env); 92953018216SPaolo Bonzini ppc_tb_t *tb_env; 93053018216SPaolo Bonzini 93153018216SPaolo Bonzini tb_env = g_malloc0(sizeof(ppc_tb_t)); 93253018216SPaolo Bonzini env->tb_env = tb_env; 93353018216SPaolo Bonzini tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 934e81a982aSAlexander Graf if (env->insns_flags & PPC_SEGMENT_64B) { 935e81a982aSAlexander Graf /* All Book3S 64bit CPUs implement level based DEC logic */ 936e81a982aSAlexander Graf tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 937e81a982aSAlexander Graf } 93853018216SPaolo Bonzini /* Create new timer */ 939bc72ad67SAlex Bligh tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 940*4b236b62SBenjamin Herrenschmidt if (env->has_hv_mode) { 941bc72ad67SAlex Bligh tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 94253018216SPaolo Bonzini cpu); 94353018216SPaolo Bonzini } else { 94453018216SPaolo Bonzini tb_env->hdecr_timer = NULL; 94553018216SPaolo Bonzini } 94653018216SPaolo Bonzini cpu_ppc_set_tb_clk(env, freq); 94753018216SPaolo Bonzini 94853018216SPaolo Bonzini return &cpu_ppc_set_tb_clk; 94953018216SPaolo Bonzini } 95053018216SPaolo Bonzini 95153018216SPaolo Bonzini /* Specific helpers for POWER & PowerPC 601 RTC */ 95253018216SPaolo Bonzini #if 0 95353018216SPaolo Bonzini static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) 95453018216SPaolo Bonzini { 95553018216SPaolo Bonzini return cpu_ppc_tb_init(env, 7812500); 95653018216SPaolo Bonzini } 95753018216SPaolo Bonzini #endif 95853018216SPaolo Bonzini 95953018216SPaolo Bonzini void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 96053018216SPaolo Bonzini { 96153018216SPaolo Bonzini _cpu_ppc_store_tbu(env, value); 96253018216SPaolo Bonzini } 96353018216SPaolo Bonzini 96453018216SPaolo Bonzini uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 96553018216SPaolo Bonzini { 96653018216SPaolo Bonzini return _cpu_ppc_load_tbu(env); 96753018216SPaolo Bonzini } 96853018216SPaolo Bonzini 96953018216SPaolo Bonzini void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 97053018216SPaolo Bonzini { 97153018216SPaolo Bonzini cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 97253018216SPaolo Bonzini } 97353018216SPaolo Bonzini 97453018216SPaolo Bonzini uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 97553018216SPaolo Bonzini { 97653018216SPaolo Bonzini return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 97753018216SPaolo Bonzini } 97853018216SPaolo Bonzini 97953018216SPaolo Bonzini /*****************************************************************************/ 98053018216SPaolo Bonzini /* PowerPC 40x timers */ 98153018216SPaolo Bonzini 98253018216SPaolo Bonzini /* PIT, FIT & WDT */ 98353018216SPaolo Bonzini typedef struct ppc40x_timer_t ppc40x_timer_t; 98453018216SPaolo Bonzini struct ppc40x_timer_t { 98553018216SPaolo Bonzini uint64_t pit_reload; /* PIT auto-reload value */ 98653018216SPaolo Bonzini uint64_t fit_next; /* Tick for next FIT interrupt */ 9871246b259SStefan Weil QEMUTimer *fit_timer; 98853018216SPaolo Bonzini uint64_t wdt_next; /* Tick for next WDT interrupt */ 9891246b259SStefan Weil QEMUTimer *wdt_timer; 99053018216SPaolo Bonzini 99153018216SPaolo Bonzini /* 405 have the PIT, 440 have a DECR. */ 99253018216SPaolo Bonzini unsigned int decr_excp; 99353018216SPaolo Bonzini }; 99453018216SPaolo Bonzini 99553018216SPaolo Bonzini /* Fixed interval timer */ 99653018216SPaolo Bonzini static void cpu_4xx_fit_cb (void *opaque) 99753018216SPaolo Bonzini { 99853018216SPaolo Bonzini PowerPCCPU *cpu; 99953018216SPaolo Bonzini CPUPPCState *env; 100053018216SPaolo Bonzini ppc_tb_t *tb_env; 100153018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 100253018216SPaolo Bonzini uint64_t now, next; 100353018216SPaolo Bonzini 100453018216SPaolo Bonzini env = opaque; 100553018216SPaolo Bonzini cpu = ppc_env_get_cpu(env); 100653018216SPaolo Bonzini tb_env = env->tb_env; 100753018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 1008bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 100953018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 101053018216SPaolo Bonzini case 0: 101153018216SPaolo Bonzini next = 1 << 9; 101253018216SPaolo Bonzini break; 101353018216SPaolo Bonzini case 1: 101453018216SPaolo Bonzini next = 1 << 13; 101553018216SPaolo Bonzini break; 101653018216SPaolo Bonzini case 2: 101753018216SPaolo Bonzini next = 1 << 17; 101853018216SPaolo Bonzini break; 101953018216SPaolo Bonzini case 3: 102053018216SPaolo Bonzini next = 1 << 21; 102153018216SPaolo Bonzini break; 102253018216SPaolo Bonzini default: 102353018216SPaolo Bonzini /* Cannot occur, but makes gcc happy */ 102453018216SPaolo Bonzini return; 102553018216SPaolo Bonzini } 102673bcb24dSRutuja Shah next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 102753018216SPaolo Bonzini if (next == now) 102853018216SPaolo Bonzini next++; 1029bc72ad67SAlex Bligh timer_mod(ppc40x_timer->fit_timer, next); 103053018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 26; 103153018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 103253018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 103353018216SPaolo Bonzini } 103453018216SPaolo Bonzini LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 103553018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 103653018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 103753018216SPaolo Bonzini } 103853018216SPaolo Bonzini 103953018216SPaolo Bonzini /* Programmable interval timer */ 104053018216SPaolo Bonzini static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 104153018216SPaolo Bonzini { 104253018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 104353018216SPaolo Bonzini uint64_t now, next; 104453018216SPaolo Bonzini 104553018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 104653018216SPaolo Bonzini if (ppc40x_timer->pit_reload <= 1 || 104753018216SPaolo Bonzini !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 104853018216SPaolo Bonzini (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 104953018216SPaolo Bonzini /* Stop PIT */ 105053018216SPaolo Bonzini LOG_TB("%s: stop PIT\n", __func__); 1051bc72ad67SAlex Bligh timer_del(tb_env->decr_timer); 105253018216SPaolo Bonzini } else { 105353018216SPaolo Bonzini LOG_TB("%s: start PIT %016" PRIx64 "\n", 105453018216SPaolo Bonzini __func__, ppc40x_timer->pit_reload); 1055bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 105653018216SPaolo Bonzini next = now + muldiv64(ppc40x_timer->pit_reload, 105773bcb24dSRutuja Shah NANOSECONDS_PER_SECOND, tb_env->decr_freq); 105853018216SPaolo Bonzini if (is_excp) 105953018216SPaolo Bonzini next += tb_env->decr_next - now; 106053018216SPaolo Bonzini if (next == now) 106153018216SPaolo Bonzini next++; 1062bc72ad67SAlex Bligh timer_mod(tb_env->decr_timer, next); 106353018216SPaolo Bonzini tb_env->decr_next = next; 106453018216SPaolo Bonzini } 106553018216SPaolo Bonzini } 106653018216SPaolo Bonzini 106753018216SPaolo Bonzini static void cpu_4xx_pit_cb (void *opaque) 106853018216SPaolo Bonzini { 106953018216SPaolo Bonzini PowerPCCPU *cpu; 107053018216SPaolo Bonzini CPUPPCState *env; 107153018216SPaolo Bonzini ppc_tb_t *tb_env; 107253018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 107353018216SPaolo Bonzini 107453018216SPaolo Bonzini env = opaque; 107553018216SPaolo Bonzini cpu = ppc_env_get_cpu(env); 107653018216SPaolo Bonzini tb_env = env->tb_env; 107753018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 107853018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 27; 107953018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 108053018216SPaolo Bonzini ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 108153018216SPaolo Bonzini } 108253018216SPaolo Bonzini start_stop_pit(env, tb_env, 1); 108353018216SPaolo Bonzini LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 108453018216SPaolo Bonzini "%016" PRIx64 "\n", __func__, 108553018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 108653018216SPaolo Bonzini (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 108753018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 108853018216SPaolo Bonzini ppc40x_timer->pit_reload); 108953018216SPaolo Bonzini } 109053018216SPaolo Bonzini 109153018216SPaolo Bonzini /* Watchdog timer */ 109253018216SPaolo Bonzini static void cpu_4xx_wdt_cb (void *opaque) 109353018216SPaolo Bonzini { 109453018216SPaolo Bonzini PowerPCCPU *cpu; 109553018216SPaolo Bonzini CPUPPCState *env; 109653018216SPaolo Bonzini ppc_tb_t *tb_env; 109753018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 109853018216SPaolo Bonzini uint64_t now, next; 109953018216SPaolo Bonzini 110053018216SPaolo Bonzini env = opaque; 110153018216SPaolo Bonzini cpu = ppc_env_get_cpu(env); 110253018216SPaolo Bonzini tb_env = env->tb_env; 110353018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 1104bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 110553018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 110653018216SPaolo Bonzini case 0: 110753018216SPaolo Bonzini next = 1 << 17; 110853018216SPaolo Bonzini break; 110953018216SPaolo Bonzini case 1: 111053018216SPaolo Bonzini next = 1 << 21; 111153018216SPaolo Bonzini break; 111253018216SPaolo Bonzini case 2: 111353018216SPaolo Bonzini next = 1 << 25; 111453018216SPaolo Bonzini break; 111553018216SPaolo Bonzini case 3: 111653018216SPaolo Bonzini next = 1 << 29; 111753018216SPaolo Bonzini break; 111853018216SPaolo Bonzini default: 111953018216SPaolo Bonzini /* Cannot occur, but makes gcc happy */ 112053018216SPaolo Bonzini return; 112153018216SPaolo Bonzini } 112273bcb24dSRutuja Shah next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 112353018216SPaolo Bonzini if (next == now) 112453018216SPaolo Bonzini next++; 112553018216SPaolo Bonzini LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 112653018216SPaolo Bonzini env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 112753018216SPaolo Bonzini switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 112853018216SPaolo Bonzini case 0x0: 112953018216SPaolo Bonzini case 0x1: 1130bc72ad67SAlex Bligh timer_mod(ppc40x_timer->wdt_timer, next); 113153018216SPaolo Bonzini ppc40x_timer->wdt_next = next; 1132a1f7f97bSPeter Maydell env->spr[SPR_40x_TSR] |= 1U << 31; 113353018216SPaolo Bonzini break; 113453018216SPaolo Bonzini case 0x2: 1135bc72ad67SAlex Bligh timer_mod(ppc40x_timer->wdt_timer, next); 113653018216SPaolo Bonzini ppc40x_timer->wdt_next = next; 113753018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= 1 << 30; 113853018216SPaolo Bonzini if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 113953018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 114053018216SPaolo Bonzini } 114153018216SPaolo Bonzini break; 114253018216SPaolo Bonzini case 0x3: 114353018216SPaolo Bonzini env->spr[SPR_40x_TSR] &= ~0x30000000; 114453018216SPaolo Bonzini env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 114553018216SPaolo Bonzini switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 114653018216SPaolo Bonzini case 0x0: 114753018216SPaolo Bonzini /* No reset */ 114853018216SPaolo Bonzini break; 114953018216SPaolo Bonzini case 0x1: /* Core reset */ 115053018216SPaolo Bonzini ppc40x_core_reset(cpu); 115153018216SPaolo Bonzini break; 115253018216SPaolo Bonzini case 0x2: /* Chip reset */ 115353018216SPaolo Bonzini ppc40x_chip_reset(cpu); 115453018216SPaolo Bonzini break; 115553018216SPaolo Bonzini case 0x3: /* System reset */ 115653018216SPaolo Bonzini ppc40x_system_reset(cpu); 115753018216SPaolo Bonzini break; 115853018216SPaolo Bonzini } 115953018216SPaolo Bonzini } 116053018216SPaolo Bonzini } 116153018216SPaolo Bonzini 116253018216SPaolo Bonzini void store_40x_pit (CPUPPCState *env, target_ulong val) 116353018216SPaolo Bonzini { 116453018216SPaolo Bonzini ppc_tb_t *tb_env; 116553018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 116653018216SPaolo Bonzini 116753018216SPaolo Bonzini tb_env = env->tb_env; 116853018216SPaolo Bonzini ppc40x_timer = tb_env->opaque; 116953018216SPaolo Bonzini LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 117053018216SPaolo Bonzini ppc40x_timer->pit_reload = val; 117153018216SPaolo Bonzini start_stop_pit(env, tb_env, 0); 117253018216SPaolo Bonzini } 117353018216SPaolo Bonzini 117453018216SPaolo Bonzini target_ulong load_40x_pit (CPUPPCState *env) 117553018216SPaolo Bonzini { 117653018216SPaolo Bonzini return cpu_ppc_load_decr(env); 117753018216SPaolo Bonzini } 117853018216SPaolo Bonzini 117953018216SPaolo Bonzini static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 118053018216SPaolo Bonzini { 118153018216SPaolo Bonzini CPUPPCState *env = opaque; 118253018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env; 118353018216SPaolo Bonzini 118453018216SPaolo Bonzini LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 118553018216SPaolo Bonzini freq); 118653018216SPaolo Bonzini tb_env->tb_freq = freq; 118753018216SPaolo Bonzini tb_env->decr_freq = freq; 118853018216SPaolo Bonzini /* XXX: we should also update all timers */ 118953018216SPaolo Bonzini } 119053018216SPaolo Bonzini 119153018216SPaolo Bonzini clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 119253018216SPaolo Bonzini unsigned int decr_excp) 119353018216SPaolo Bonzini { 119453018216SPaolo Bonzini ppc_tb_t *tb_env; 119553018216SPaolo Bonzini ppc40x_timer_t *ppc40x_timer; 119653018216SPaolo Bonzini 119753018216SPaolo Bonzini tb_env = g_malloc0(sizeof(ppc_tb_t)); 119853018216SPaolo Bonzini env->tb_env = tb_env; 119953018216SPaolo Bonzini tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 120053018216SPaolo Bonzini ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 120153018216SPaolo Bonzini tb_env->tb_freq = freq; 120253018216SPaolo Bonzini tb_env->decr_freq = freq; 120353018216SPaolo Bonzini tb_env->opaque = ppc40x_timer; 120453018216SPaolo Bonzini LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 120553018216SPaolo Bonzini if (ppc40x_timer != NULL) { 120653018216SPaolo Bonzini /* We use decr timer for PIT */ 1207bc72ad67SAlex Bligh tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 120853018216SPaolo Bonzini ppc40x_timer->fit_timer = 1209bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 121053018216SPaolo Bonzini ppc40x_timer->wdt_timer = 1211bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 121253018216SPaolo Bonzini ppc40x_timer->decr_excp = decr_excp; 121353018216SPaolo Bonzini } 121453018216SPaolo Bonzini 121553018216SPaolo Bonzini return &ppc_40x_set_tb_clk; 121653018216SPaolo Bonzini } 121753018216SPaolo Bonzini 121853018216SPaolo Bonzini /*****************************************************************************/ 121953018216SPaolo Bonzini /* Embedded PowerPC Device Control Registers */ 122053018216SPaolo Bonzini typedef struct ppc_dcrn_t ppc_dcrn_t; 122153018216SPaolo Bonzini struct ppc_dcrn_t { 122253018216SPaolo Bonzini dcr_read_cb dcr_read; 122353018216SPaolo Bonzini dcr_write_cb dcr_write; 122453018216SPaolo Bonzini void *opaque; 122553018216SPaolo Bonzini }; 122653018216SPaolo Bonzini 122753018216SPaolo Bonzini /* XXX: on 460, DCR addresses are 32 bits wide, 122853018216SPaolo Bonzini * using DCRIPR to get the 22 upper bits of the DCR address 122953018216SPaolo Bonzini */ 123053018216SPaolo Bonzini #define DCRN_NB 1024 123153018216SPaolo Bonzini struct ppc_dcr_t { 123253018216SPaolo Bonzini ppc_dcrn_t dcrn[DCRN_NB]; 123353018216SPaolo Bonzini int (*read_error)(int dcrn); 123453018216SPaolo Bonzini int (*write_error)(int dcrn); 123553018216SPaolo Bonzini }; 123653018216SPaolo Bonzini 123753018216SPaolo Bonzini int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 123853018216SPaolo Bonzini { 123953018216SPaolo Bonzini ppc_dcrn_t *dcr; 124053018216SPaolo Bonzini 124153018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 124253018216SPaolo Bonzini goto error; 124353018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 124453018216SPaolo Bonzini if (dcr->dcr_read == NULL) 124553018216SPaolo Bonzini goto error; 124653018216SPaolo Bonzini *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 124753018216SPaolo Bonzini 124853018216SPaolo Bonzini return 0; 124953018216SPaolo Bonzini 125053018216SPaolo Bonzini error: 125153018216SPaolo Bonzini if (dcr_env->read_error != NULL) 125253018216SPaolo Bonzini return (*dcr_env->read_error)(dcrn); 125353018216SPaolo Bonzini 125453018216SPaolo Bonzini return -1; 125553018216SPaolo Bonzini } 125653018216SPaolo Bonzini 125753018216SPaolo Bonzini int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 125853018216SPaolo Bonzini { 125953018216SPaolo Bonzini ppc_dcrn_t *dcr; 126053018216SPaolo Bonzini 126153018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 126253018216SPaolo Bonzini goto error; 126353018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 126453018216SPaolo Bonzini if (dcr->dcr_write == NULL) 126553018216SPaolo Bonzini goto error; 126653018216SPaolo Bonzini (*dcr->dcr_write)(dcr->opaque, dcrn, val); 126753018216SPaolo Bonzini 126853018216SPaolo Bonzini return 0; 126953018216SPaolo Bonzini 127053018216SPaolo Bonzini error: 127153018216SPaolo Bonzini if (dcr_env->write_error != NULL) 127253018216SPaolo Bonzini return (*dcr_env->write_error)(dcrn); 127353018216SPaolo Bonzini 127453018216SPaolo Bonzini return -1; 127553018216SPaolo Bonzini } 127653018216SPaolo Bonzini 127753018216SPaolo Bonzini int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 127853018216SPaolo Bonzini dcr_read_cb dcr_read, dcr_write_cb dcr_write) 127953018216SPaolo Bonzini { 128053018216SPaolo Bonzini ppc_dcr_t *dcr_env; 128153018216SPaolo Bonzini ppc_dcrn_t *dcr; 128253018216SPaolo Bonzini 128353018216SPaolo Bonzini dcr_env = env->dcr_env; 128453018216SPaolo Bonzini if (dcr_env == NULL) 128553018216SPaolo Bonzini return -1; 128653018216SPaolo Bonzini if (dcrn < 0 || dcrn >= DCRN_NB) 128753018216SPaolo Bonzini return -1; 128853018216SPaolo Bonzini dcr = &dcr_env->dcrn[dcrn]; 128953018216SPaolo Bonzini if (dcr->opaque != NULL || 129053018216SPaolo Bonzini dcr->dcr_read != NULL || 129153018216SPaolo Bonzini dcr->dcr_write != NULL) 129253018216SPaolo Bonzini return -1; 129353018216SPaolo Bonzini dcr->opaque = opaque; 129453018216SPaolo Bonzini dcr->dcr_read = dcr_read; 129553018216SPaolo Bonzini dcr->dcr_write = dcr_write; 129653018216SPaolo Bonzini 129753018216SPaolo Bonzini return 0; 129853018216SPaolo Bonzini } 129953018216SPaolo Bonzini 130053018216SPaolo Bonzini int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 130153018216SPaolo Bonzini int (*write_error)(int dcrn)) 130253018216SPaolo Bonzini { 130353018216SPaolo Bonzini ppc_dcr_t *dcr_env; 130453018216SPaolo Bonzini 130553018216SPaolo Bonzini dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 130653018216SPaolo Bonzini dcr_env->read_error = read_error; 130753018216SPaolo Bonzini dcr_env->write_error = write_error; 130853018216SPaolo Bonzini env->dcr_env = dcr_env; 130953018216SPaolo Bonzini 131053018216SPaolo Bonzini return 0; 131153018216SPaolo Bonzini } 131253018216SPaolo Bonzini 131353018216SPaolo Bonzini /*****************************************************************************/ 131453018216SPaolo Bonzini /* Debug port */ 131553018216SPaolo Bonzini void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 131653018216SPaolo Bonzini { 131753018216SPaolo Bonzini addr &= 0xF; 131853018216SPaolo Bonzini switch (addr) { 131953018216SPaolo Bonzini case 0: 132053018216SPaolo Bonzini printf("%c", val); 132153018216SPaolo Bonzini break; 132253018216SPaolo Bonzini case 1: 132353018216SPaolo Bonzini printf("\n"); 132453018216SPaolo Bonzini fflush(stdout); 132553018216SPaolo Bonzini break; 132653018216SPaolo Bonzini case 2: 132753018216SPaolo Bonzini printf("Set loglevel to %04" PRIx32 "\n", val); 132853018216SPaolo Bonzini qemu_set_log(val | 0x100); 132953018216SPaolo Bonzini break; 133053018216SPaolo Bonzini } 133153018216SPaolo Bonzini } 133253018216SPaolo Bonzini 13330ce470cdSAlexey Kardashevskiy /* CPU device-tree ID helpers */ 13340ce470cdSAlexey Kardashevskiy int ppc_get_vcpu_dt_id(PowerPCCPU *cpu) 13350ce470cdSAlexey Kardashevskiy { 13360ce470cdSAlexey Kardashevskiy return cpu->cpu_dt_id; 13370ce470cdSAlexey Kardashevskiy } 13380ce470cdSAlexey Kardashevskiy 13390ce470cdSAlexey Kardashevskiy PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id) 13400ce470cdSAlexey Kardashevskiy { 13410ce470cdSAlexey Kardashevskiy CPUState *cs; 13420ce470cdSAlexey Kardashevskiy 13430ce470cdSAlexey Kardashevskiy CPU_FOREACH(cs) { 13440ce470cdSAlexey Kardashevskiy PowerPCCPU *cpu = POWERPC_CPU(cs); 13450ce470cdSAlexey Kardashevskiy 13460ce470cdSAlexey Kardashevskiy if (cpu->cpu_dt_id == cpu_dt_id) { 13470ce470cdSAlexey Kardashevskiy return cpu; 13480ce470cdSAlexey Kardashevskiy } 13490ce470cdSAlexey Kardashevskiy } 13500ce470cdSAlexey Kardashevskiy 13510ce470cdSAlexey Kardashevskiy return NULL; 13520ce470cdSAlexey Kardashevskiy } 1353