147b43a1fSPaolo Bonzini /* 247b43a1fSPaolo Bonzini * QEMU PowerPC 405 shared definitions 347b43a1fSPaolo Bonzini * 447b43a1fSPaolo Bonzini * Copyright (c) 2007 Jocelyn Mayer 547b43a1fSPaolo Bonzini * 647b43a1fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 747b43a1fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 847b43a1fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 947b43a1fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1047b43a1fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1147b43a1fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1247b43a1fSPaolo Bonzini * 1347b43a1fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1447b43a1fSPaolo Bonzini * all copies or substantial portions of the Software. 1547b43a1fSPaolo Bonzini * 1647b43a1fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1747b43a1fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1847b43a1fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1947b43a1fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2047b43a1fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2147b43a1fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2247b43a1fSPaolo Bonzini * THE SOFTWARE. 2347b43a1fSPaolo Bonzini */ 2447b43a1fSPaolo Bonzini 25121d0712SMarkus Armbruster #ifndef PPC405_H 26121d0712SMarkus Armbruster #define PPC405_H 2747b43a1fSPaolo Bonzini 283b758ca2SCédric Le Goater #include "qom/object.h" 2947b43a1fSPaolo Bonzini #include "hw/ppc/ppc4xx.h" 3047b43a1fSPaolo Bonzini 31f61b99d3SCédric Le Goater #define PPC405EP_SDRAM_BASE 0x00000000 32f61b99d3SCédric Le Goater #define PPC405EP_NVRAM_BASE 0xF0000000 33f61b99d3SCédric Le Goater #define PPC405EP_FPGA_BASE 0xF0300000 34f61b99d3SCédric Le Goater #define PPC405EP_SRAM_BASE 0xFFF00000 35f61b99d3SCédric Le Goater #define PPC405EP_SRAM_SIZE (512 * KiB) 36f61b99d3SCédric Le Goater #define PPC405EP_FLASH_BASE 0xFFF80000 37f61b99d3SCédric Le Goater 3847b43a1fSPaolo Bonzini /* Bootinfo as set-up by u-boot */ 3947b43a1fSPaolo Bonzini typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; 4047b43a1fSPaolo Bonzini struct ppc4xx_bd_info_t { 4147b43a1fSPaolo Bonzini uint32_t bi_memstart; 4247b43a1fSPaolo Bonzini uint32_t bi_memsize; 4347b43a1fSPaolo Bonzini uint32_t bi_flashstart; 4447b43a1fSPaolo Bonzini uint32_t bi_flashsize; 4547b43a1fSPaolo Bonzini uint32_t bi_flashoffset; /* 0x10 */ 4647b43a1fSPaolo Bonzini uint32_t bi_sramstart; 4747b43a1fSPaolo Bonzini uint32_t bi_sramsize; 4847b43a1fSPaolo Bonzini uint32_t bi_bootflags; 4947b43a1fSPaolo Bonzini uint32_t bi_ipaddr; /* 0x20 */ 5047b43a1fSPaolo Bonzini uint8_t bi_enetaddr[6]; 5147b43a1fSPaolo Bonzini uint16_t bi_ethspeed; 5247b43a1fSPaolo Bonzini uint32_t bi_intfreq; 5347b43a1fSPaolo Bonzini uint32_t bi_busfreq; /* 0x30 */ 5447b43a1fSPaolo Bonzini uint32_t bi_baudrate; 5547b43a1fSPaolo Bonzini uint8_t bi_s_version[4]; 5647b43a1fSPaolo Bonzini uint8_t bi_r_version[32]; 5747b43a1fSPaolo Bonzini uint32_t bi_procfreq; 5847b43a1fSPaolo Bonzini uint32_t bi_plb_busfreq; 5947b43a1fSPaolo Bonzini uint32_t bi_pci_busfreq; 6047b43a1fSPaolo Bonzini uint8_t bi_pci_enetaddr[6]; 61e0caa8e6SCédric Le Goater uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ 6247b43a1fSPaolo Bonzini uint32_t bi_opbfreq; 6347b43a1fSPaolo Bonzini uint32_t bi_iic_fast[2]; 6447b43a1fSPaolo Bonzini }; 6547b43a1fSPaolo Bonzini 662847eb40SCédric Le Goater /* On Chip Memory */ 672847eb40SCédric Le Goater #define TYPE_PPC405_OCM "ppc405-ocm" 682847eb40SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); 692847eb40SCédric Le Goater struct Ppc405OcmState { 702847eb40SCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 712847eb40SCédric Le Goater 722847eb40SCédric Le Goater MemoryRegion ram; 732847eb40SCédric Le Goater MemoryRegion isarc_ram; 742847eb40SCédric Le Goater MemoryRegion dsarc_ram; 752847eb40SCédric Le Goater uint32_t isarc; 762847eb40SCédric Le Goater uint32_t isacntl; 772847eb40SCédric Le Goater uint32_t dsarc; 782847eb40SCédric Le Goater uint32_t dsacntl; 792847eb40SCédric Le Goater }; 802847eb40SCédric Le Goater 81269fbb5bSCédric Le Goater /* General purpose timers */ 82269fbb5bSCédric Le Goater #define TYPE_PPC405_GPT "ppc405-gpt" 83269fbb5bSCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); 84269fbb5bSCédric Le Goater struct Ppc405GptState { 85269fbb5bSCédric Le Goater SysBusDevice parent_obj; 86269fbb5bSCédric Le Goater 87269fbb5bSCédric Le Goater MemoryRegion iomem; 88269fbb5bSCédric Le Goater 89269fbb5bSCédric Le Goater int64_t tb_offset; 90269fbb5bSCédric Le Goater uint32_t tb_freq; 91269fbb5bSCédric Le Goater QEMUTimer *timer; 92269fbb5bSCédric Le Goater qemu_irq irqs[5]; 93269fbb5bSCédric Le Goater uint32_t oe; 94269fbb5bSCédric Le Goater uint32_t ol; 95269fbb5bSCédric Le Goater uint32_t im; 96269fbb5bSCédric Le Goater uint32_t is; 97269fbb5bSCédric Le Goater uint32_t ie; 98269fbb5bSCédric Le Goater uint32_t comp[5]; 99269fbb5bSCédric Le Goater uint32_t mask[5]; 100269fbb5bSCédric Le Goater }; 101269fbb5bSCédric Le Goater 1024a7d2b7eSCédric Le Goater #define TYPE_PPC405_CPC "ppc405-cpc" 1034a7d2b7eSCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); 1044a7d2b7eSCédric Le Goater 1054a7d2b7eSCédric Le Goater enum { 1064a7d2b7eSCédric Le Goater PPC405EP_CPU_CLK = 0, 1074a7d2b7eSCédric Le Goater PPC405EP_PLB_CLK = 1, 1084a7d2b7eSCédric Le Goater PPC405EP_OPB_CLK = 2, 1094a7d2b7eSCédric Le Goater PPC405EP_EBC_CLK = 3, 1104a7d2b7eSCédric Le Goater PPC405EP_MAL_CLK = 4, 1114a7d2b7eSCédric Le Goater PPC405EP_PCI_CLK = 5, 1124a7d2b7eSCédric Le Goater PPC405EP_UART0_CLK = 6, 1134a7d2b7eSCédric Le Goater PPC405EP_UART1_CLK = 7, 1144a7d2b7eSCédric Le Goater PPC405EP_CLK_NB = 8, 1154a7d2b7eSCédric Le Goater }; 1164a7d2b7eSCédric Le Goater 1174a7d2b7eSCédric Le Goater struct Ppc405CpcState { 1184a7d2b7eSCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 1194a7d2b7eSCédric Le Goater 1204a7d2b7eSCédric Le Goater uint32_t sysclk; 1214a7d2b7eSCédric Le Goater clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1224a7d2b7eSCédric Le Goater uint32_t boot; 1234a7d2b7eSCédric Le Goater uint32_t epctl; 1244a7d2b7eSCédric Le Goater uint32_t pllmr[2]; 1254a7d2b7eSCédric Le Goater uint32_t ucr; 1264a7d2b7eSCédric Le Goater uint32_t srr; 1274a7d2b7eSCédric Le Goater uint32_t jtagid; 1284a7d2b7eSCédric Le Goater uint32_t pci; 1294a7d2b7eSCédric Le Goater /* Clock and power management */ 1304a7d2b7eSCédric Le Goater uint32_t er; 1314a7d2b7eSCédric Le Goater uint32_t fr; 1324a7d2b7eSCédric Le Goater uint32_t sr; 1334a7d2b7eSCédric Le Goater }; 1344a7d2b7eSCédric Le Goater 1353b758ca2SCédric Le Goater #define TYPE_PPC405_SOC "ppc405-soc" 1363b758ca2SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); 1373b758ca2SCédric Le Goater 1383b758ca2SCédric Le Goater struct Ppc405SoCState { 1393b758ca2SCédric Le Goater /* Private */ 1403b758ca2SCédric Le Goater DeviceState parent_obj; 1413b758ca2SCédric Le Goater 1423b758ca2SCédric Le Goater /* Public */ 1433b758ca2SCédric Le Goater MemoryRegion ram_banks[2]; 1443b758ca2SCédric Le Goater hwaddr ram_bases[2], ram_sizes[2]; 1455b0f170aSCédric Le Goater bool do_dram_init; 1463b758ca2SCédric Le Goater 1473b758ca2SCédric Le Goater MemoryRegion *dram_mr; 1483b758ca2SCédric Le Goater hwaddr ram_size; 1495b0f170aSCédric Le Goater 150b42ad437SCédric Le Goater PowerPCCPU cpu; 1515b0f170aSCédric Le Goater DeviceState *uic; 1524a7d2b7eSCédric Le Goater Ppc405CpcState cpc; 153269fbb5bSCédric Le Goater Ppc405GptState gpt; 1542847eb40SCédric Le Goater Ppc405OcmState ocm; 1553b758ca2SCédric Le Goater }; 1563b758ca2SCédric Le Goater 15747b43a1fSPaolo Bonzini /* PowerPC 405 core */ 158e3931ecaSCédric Le Goater ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); 15947b43a1fSPaolo Bonzini 16097c2acb5SBALATON Zoltan void ppc4xx_plb_init(CPUPPCState *env); 16197c2acb5SBALATON Zoltan void ppc405_ebc_init(CPUPPCState *env); 16297c2acb5SBALATON Zoltan 163121d0712SMarkus Armbruster #endif /* PPC405_H */ 164