147b43a1fSPaolo Bonzini /* 247b43a1fSPaolo Bonzini * QEMU PowerPC 405 shared definitions 347b43a1fSPaolo Bonzini * 447b43a1fSPaolo Bonzini * Copyright (c) 2007 Jocelyn Mayer 547b43a1fSPaolo Bonzini * 647b43a1fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 747b43a1fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 847b43a1fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 947b43a1fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1047b43a1fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1147b43a1fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1247b43a1fSPaolo Bonzini * 1347b43a1fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1447b43a1fSPaolo Bonzini * all copies or substantial portions of the Software. 1547b43a1fSPaolo Bonzini * 1647b43a1fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1747b43a1fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1847b43a1fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1947b43a1fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2047b43a1fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2147b43a1fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2247b43a1fSPaolo Bonzini * THE SOFTWARE. 2347b43a1fSPaolo Bonzini */ 2447b43a1fSPaolo Bonzini 25121d0712SMarkus Armbruster #ifndef PPC405_H 26121d0712SMarkus Armbruster #define PPC405_H 2747b43a1fSPaolo Bonzini 283b758ca2SCédric Le Goater #include "qom/object.h" 2947b43a1fSPaolo Bonzini #include "hw/ppc/ppc4xx.h" 3047b43a1fSPaolo Bonzini 31f61b99d3SCédric Le Goater #define PPC405EP_SDRAM_BASE 0x00000000 32f61b99d3SCédric Le Goater #define PPC405EP_NVRAM_BASE 0xF0000000 33f61b99d3SCédric Le Goater #define PPC405EP_FPGA_BASE 0xF0300000 34f61b99d3SCédric Le Goater #define PPC405EP_SRAM_BASE 0xFFF00000 35f61b99d3SCédric Le Goater #define PPC405EP_SRAM_SIZE (512 * KiB) 36f61b99d3SCédric Le Goater #define PPC405EP_FLASH_BASE 0xFFF80000 37f61b99d3SCédric Le Goater 3847b43a1fSPaolo Bonzini /* Bootinfo as set-up by u-boot */ 3947b43a1fSPaolo Bonzini typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; 4047b43a1fSPaolo Bonzini struct ppc4xx_bd_info_t { 4147b43a1fSPaolo Bonzini uint32_t bi_memstart; 4247b43a1fSPaolo Bonzini uint32_t bi_memsize; 4347b43a1fSPaolo Bonzini uint32_t bi_flashstart; 4447b43a1fSPaolo Bonzini uint32_t bi_flashsize; 4547b43a1fSPaolo Bonzini uint32_t bi_flashoffset; /* 0x10 */ 4647b43a1fSPaolo Bonzini uint32_t bi_sramstart; 4747b43a1fSPaolo Bonzini uint32_t bi_sramsize; 4847b43a1fSPaolo Bonzini uint32_t bi_bootflags; 4947b43a1fSPaolo Bonzini uint32_t bi_ipaddr; /* 0x20 */ 5047b43a1fSPaolo Bonzini uint8_t bi_enetaddr[6]; 5147b43a1fSPaolo Bonzini uint16_t bi_ethspeed; 5247b43a1fSPaolo Bonzini uint32_t bi_intfreq; 5347b43a1fSPaolo Bonzini uint32_t bi_busfreq; /* 0x30 */ 5447b43a1fSPaolo Bonzini uint32_t bi_baudrate; 5547b43a1fSPaolo Bonzini uint8_t bi_s_version[4]; 5647b43a1fSPaolo Bonzini uint8_t bi_r_version[32]; 5747b43a1fSPaolo Bonzini uint32_t bi_procfreq; 5847b43a1fSPaolo Bonzini uint32_t bi_plb_busfreq; 5947b43a1fSPaolo Bonzini uint32_t bi_pci_busfreq; 6047b43a1fSPaolo Bonzini uint8_t bi_pci_enetaddr[6]; 61e0caa8e6SCédric Le Goater uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ 6247b43a1fSPaolo Bonzini uint32_t bi_opbfreq; 6347b43a1fSPaolo Bonzini uint32_t bi_iic_fast[2]; 6447b43a1fSPaolo Bonzini }; 6547b43a1fSPaolo Bonzini 663b758ca2SCédric Le Goater #define TYPE_PPC405_SOC "ppc405-soc" 673b758ca2SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); 683b758ca2SCédric Le Goater 693b758ca2SCédric Le Goater struct Ppc405SoCState { 703b758ca2SCédric Le Goater /* Private */ 713b758ca2SCédric Le Goater DeviceState parent_obj; 723b758ca2SCédric Le Goater 733b758ca2SCédric Le Goater /* Public */ 743b758ca2SCédric Le Goater MemoryRegion ram_banks[2]; 753b758ca2SCédric Le Goater hwaddr ram_bases[2], ram_sizes[2]; 765b0f170aSCédric Le Goater bool do_dram_init; 773b758ca2SCédric Le Goater 783b758ca2SCédric Le Goater MemoryRegion *dram_mr; 793b758ca2SCédric Le Goater hwaddr ram_size; 805b0f170aSCédric Le Goater 815b0f170aSCédric Le Goater uint32_t sysclk; 82b42ad437SCédric Le Goater PowerPCCPU cpu; 835b0f170aSCédric Le Goater DeviceState *uic; 843b758ca2SCédric Le Goater }; 853b758ca2SCédric Le Goater 8647b43a1fSPaolo Bonzini /* PowerPC 405 core */ 87e3931ecaSCédric Le Goater ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); 8847b43a1fSPaolo Bonzini 8997c2acb5SBALATON Zoltan void ppc4xx_plb_init(CPUPPCState *env); 9097c2acb5SBALATON Zoltan void ppc405_ebc_init(CPUPPCState *env); 9197c2acb5SBALATON Zoltan 92121d0712SMarkus Armbruster #endif /* PPC405_H */ 93