147b43a1fSPaolo Bonzini /* 247b43a1fSPaolo Bonzini * QEMU PowerPC 405 shared definitions 347b43a1fSPaolo Bonzini * 447b43a1fSPaolo Bonzini * Copyright (c) 2007 Jocelyn Mayer 547b43a1fSPaolo Bonzini * 647b43a1fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 747b43a1fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 847b43a1fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 947b43a1fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1047b43a1fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1147b43a1fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1247b43a1fSPaolo Bonzini * 1347b43a1fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1447b43a1fSPaolo Bonzini * all copies or substantial portions of the Software. 1547b43a1fSPaolo Bonzini * 1647b43a1fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1747b43a1fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1847b43a1fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1947b43a1fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2047b43a1fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2147b43a1fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2247b43a1fSPaolo Bonzini * THE SOFTWARE. 2347b43a1fSPaolo Bonzini */ 2447b43a1fSPaolo Bonzini 25121d0712SMarkus Armbruster #ifndef PPC405_H 26121d0712SMarkus Armbruster #define PPC405_H 2747b43a1fSPaolo Bonzini 283b758ca2SCédric Le Goater #include "qom/object.h" 2947b43a1fSPaolo Bonzini #include "hw/ppc/ppc4xx.h" 3047b43a1fSPaolo Bonzini 31f61b99d3SCédric Le Goater #define PPC405EP_SDRAM_BASE 0x00000000 32f61b99d3SCédric Le Goater #define PPC405EP_NVRAM_BASE 0xF0000000 33f61b99d3SCédric Le Goater #define PPC405EP_FPGA_BASE 0xF0300000 34f61b99d3SCédric Le Goater #define PPC405EP_SRAM_BASE 0xFFF00000 35f61b99d3SCédric Le Goater #define PPC405EP_SRAM_SIZE (512 * KiB) 36f61b99d3SCédric Le Goater #define PPC405EP_FLASH_BASE 0xFFF80000 37f61b99d3SCédric Le Goater 3847b43a1fSPaolo Bonzini /* Bootinfo as set-up by u-boot */ 3947b43a1fSPaolo Bonzini typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; 4047b43a1fSPaolo Bonzini struct ppc4xx_bd_info_t { 4147b43a1fSPaolo Bonzini uint32_t bi_memstart; 4247b43a1fSPaolo Bonzini uint32_t bi_memsize; 4347b43a1fSPaolo Bonzini uint32_t bi_flashstart; 4447b43a1fSPaolo Bonzini uint32_t bi_flashsize; 4547b43a1fSPaolo Bonzini uint32_t bi_flashoffset; /* 0x10 */ 4647b43a1fSPaolo Bonzini uint32_t bi_sramstart; 4747b43a1fSPaolo Bonzini uint32_t bi_sramsize; 4847b43a1fSPaolo Bonzini uint32_t bi_bootflags; 4947b43a1fSPaolo Bonzini uint32_t bi_ipaddr; /* 0x20 */ 5047b43a1fSPaolo Bonzini uint8_t bi_enetaddr[6]; 5147b43a1fSPaolo Bonzini uint16_t bi_ethspeed; 5247b43a1fSPaolo Bonzini uint32_t bi_intfreq; 5347b43a1fSPaolo Bonzini uint32_t bi_busfreq; /* 0x30 */ 5447b43a1fSPaolo Bonzini uint32_t bi_baudrate; 5547b43a1fSPaolo Bonzini uint8_t bi_s_version[4]; 5647b43a1fSPaolo Bonzini uint8_t bi_r_version[32]; 5747b43a1fSPaolo Bonzini uint32_t bi_procfreq; 5847b43a1fSPaolo Bonzini uint32_t bi_plb_busfreq; 5947b43a1fSPaolo Bonzini uint32_t bi_pci_busfreq; 6047b43a1fSPaolo Bonzini uint8_t bi_pci_enetaddr[6]; 61e0caa8e6SCédric Le Goater uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ 6247b43a1fSPaolo Bonzini uint32_t bi_opbfreq; 6347b43a1fSPaolo Bonzini uint32_t bi_iic_fast[2]; 6447b43a1fSPaolo Bonzini }; 6547b43a1fSPaolo Bonzini 66695bce07SCédric Le Goater /* Peripheral local bus arbitrer */ 67695bce07SCédric Le Goater #define TYPE_PPC405_PLB "ppc405-plb" 68695bce07SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); 69695bce07SCédric Le Goater struct Ppc405PlbState { 70695bce07SCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 71695bce07SCédric Le Goater 72695bce07SCédric Le Goater uint32_t acr; 73695bce07SCédric Le Goater uint32_t bear; 74695bce07SCédric Le Goater uint32_t besr; 75695bce07SCédric Le Goater }; 76695bce07SCédric Le Goater 772841430eSCédric Le Goater /* PLB to OPB bridge */ 782841430eSCédric Le Goater #define TYPE_PPC405_POB "ppc405-pob" 792841430eSCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); 802841430eSCédric Le Goater struct Ppc405PobState { 812841430eSCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 822841430eSCédric Le Goater 832841430eSCédric Le Goater uint32_t bear; 842841430eSCédric Le Goater uint32_t besr0; 852841430eSCédric Le Goater uint32_t besr1; 862841430eSCédric Le Goater }; 872841430eSCédric Le Goater 8872beecc2SCédric Le Goater /* OPB arbitrer */ 8972beecc2SCédric Le Goater #define TYPE_PPC405_OPBA "ppc405-opba" 9072beecc2SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA); 9172beecc2SCédric Le Goater struct Ppc405OpbaState { 9272beecc2SCédric Le Goater SysBusDevice parent_obj; 9372beecc2SCédric Le Goater 9472beecc2SCédric Le Goater MemoryRegion io; 9572beecc2SCédric Le Goater uint8_t cr; 9672beecc2SCédric Le Goater uint8_t pr; 9772beecc2SCédric Le Goater }; 9872beecc2SCédric Le Goater 99415a6333SCédric Le Goater /* Peripheral controller */ 100415a6333SCédric Le Goater #define TYPE_PPC405_EBC "ppc405-ebc" 101415a6333SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); 102415a6333SCédric Le Goater struct Ppc405EbcState { 103415a6333SCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 104415a6333SCédric Le Goater 105415a6333SCédric Le Goater uint32_t addr; 106415a6333SCédric Le Goater uint32_t bcr[8]; 107415a6333SCédric Le Goater uint32_t bap[8]; 108415a6333SCédric Le Goater uint32_t bear; 109415a6333SCédric Le Goater uint32_t besr0; 110415a6333SCédric Le Goater uint32_t besr1; 111415a6333SCédric Le Goater uint32_t cfg; 112415a6333SCédric Le Goater }; 113415a6333SCédric Le Goater 11482c86e30SCédric Le Goater /* DMA controller */ 11582c86e30SCédric Le Goater #define TYPE_PPC405_DMA "ppc405-dma" 11682c86e30SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); 11782c86e30SCédric Le Goater struct Ppc405DmaState { 11882c86e30SCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 11982c86e30SCédric Le Goater 12082c86e30SCédric Le Goater qemu_irq irqs[4]; 12182c86e30SCédric Le Goater uint32_t cr[4]; 12282c86e30SCédric Le Goater uint32_t ct[4]; 12382c86e30SCédric Le Goater uint32_t da[4]; 12482c86e30SCédric Le Goater uint32_t sa[4]; 12582c86e30SCédric Le Goater uint32_t sg[4]; 12682c86e30SCédric Le Goater uint32_t sr; 12782c86e30SCédric Le Goater uint32_t sgc; 12882c86e30SCédric Le Goater uint32_t slp; 12982c86e30SCédric Le Goater uint32_t pol; 13082c86e30SCédric Le Goater }; 13182c86e30SCédric Le Goater 132125277c6SCédric Le Goater /* GPIO */ 133125277c6SCédric Le Goater #define TYPE_PPC405_GPIO "ppc405-gpio" 134125277c6SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); 135125277c6SCédric Le Goater struct Ppc405GpioState { 136125277c6SCédric Le Goater SysBusDevice parent_obj; 137125277c6SCédric Le Goater 138125277c6SCédric Le Goater MemoryRegion io; 139125277c6SCédric Le Goater uint32_t or; 140125277c6SCédric Le Goater uint32_t tcr; 141125277c6SCédric Le Goater uint32_t osrh; 142125277c6SCédric Le Goater uint32_t osrl; 143125277c6SCédric Le Goater uint32_t tsrh; 144125277c6SCédric Le Goater uint32_t tsrl; 145125277c6SCédric Le Goater uint32_t odr; 146125277c6SCédric Le Goater uint32_t ir; 147125277c6SCédric Le Goater uint32_t rr1; 148125277c6SCédric Le Goater uint32_t isr1h; 149125277c6SCédric Le Goater uint32_t isr1l; 150125277c6SCédric Le Goater }; 151125277c6SCédric Le Goater 1522847eb40SCédric Le Goater /* On Chip Memory */ 1532847eb40SCédric Le Goater #define TYPE_PPC405_OCM "ppc405-ocm" 1542847eb40SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); 1552847eb40SCédric Le Goater struct Ppc405OcmState { 1562847eb40SCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 1572847eb40SCédric Le Goater 1582847eb40SCédric Le Goater MemoryRegion ram; 1592847eb40SCédric Le Goater MemoryRegion isarc_ram; 1602847eb40SCédric Le Goater MemoryRegion dsarc_ram; 1612847eb40SCédric Le Goater uint32_t isarc; 1622847eb40SCédric Le Goater uint32_t isacntl; 1632847eb40SCédric Le Goater uint32_t dsarc; 1642847eb40SCédric Le Goater uint32_t dsacntl; 1652847eb40SCédric Le Goater }; 1662847eb40SCédric Le Goater 167269fbb5bSCédric Le Goater /* General purpose timers */ 168269fbb5bSCédric Le Goater #define TYPE_PPC405_GPT "ppc405-gpt" 169269fbb5bSCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); 170269fbb5bSCédric Le Goater struct Ppc405GptState { 171269fbb5bSCédric Le Goater SysBusDevice parent_obj; 172269fbb5bSCédric Le Goater 173269fbb5bSCédric Le Goater MemoryRegion iomem; 174269fbb5bSCédric Le Goater 175269fbb5bSCédric Le Goater int64_t tb_offset; 176269fbb5bSCédric Le Goater uint32_t tb_freq; 177269fbb5bSCédric Le Goater QEMUTimer *timer; 178269fbb5bSCédric Le Goater qemu_irq irqs[5]; 179269fbb5bSCédric Le Goater uint32_t oe; 180269fbb5bSCédric Le Goater uint32_t ol; 181269fbb5bSCédric Le Goater uint32_t im; 182269fbb5bSCédric Le Goater uint32_t is; 183269fbb5bSCédric Le Goater uint32_t ie; 184269fbb5bSCédric Le Goater uint32_t comp[5]; 185269fbb5bSCédric Le Goater uint32_t mask[5]; 186269fbb5bSCédric Le Goater }; 187269fbb5bSCédric Le Goater 1884a7d2b7eSCédric Le Goater #define TYPE_PPC405_CPC "ppc405-cpc" 1894a7d2b7eSCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); 1904a7d2b7eSCédric Le Goater 1914a7d2b7eSCédric Le Goater enum { 1924a7d2b7eSCédric Le Goater PPC405EP_CPU_CLK = 0, 1934a7d2b7eSCédric Le Goater PPC405EP_PLB_CLK = 1, 1944a7d2b7eSCédric Le Goater PPC405EP_OPB_CLK = 2, 1954a7d2b7eSCédric Le Goater PPC405EP_EBC_CLK = 3, 1964a7d2b7eSCédric Le Goater PPC405EP_MAL_CLK = 4, 1974a7d2b7eSCédric Le Goater PPC405EP_PCI_CLK = 5, 1984a7d2b7eSCédric Le Goater PPC405EP_UART0_CLK = 6, 1994a7d2b7eSCédric Le Goater PPC405EP_UART1_CLK = 7, 2004a7d2b7eSCédric Le Goater PPC405EP_CLK_NB = 8, 2014a7d2b7eSCédric Le Goater }; 2024a7d2b7eSCédric Le Goater 2034a7d2b7eSCédric Le Goater struct Ppc405CpcState { 2044a7d2b7eSCédric Le Goater Ppc4xxDcrDeviceState parent_obj; 2054a7d2b7eSCédric Le Goater 2064a7d2b7eSCédric Le Goater uint32_t sysclk; 2074a7d2b7eSCédric Le Goater clk_setup_t clk_setup[PPC405EP_CLK_NB]; 2084a7d2b7eSCédric Le Goater uint32_t boot; 2094a7d2b7eSCédric Le Goater uint32_t epctl; 2104a7d2b7eSCédric Le Goater uint32_t pllmr[2]; 2114a7d2b7eSCédric Le Goater uint32_t ucr; 2124a7d2b7eSCédric Le Goater uint32_t srr; 2134a7d2b7eSCédric Le Goater uint32_t jtagid; 2144a7d2b7eSCédric Le Goater uint32_t pci; 2154a7d2b7eSCédric Le Goater /* Clock and power management */ 2164a7d2b7eSCédric Le Goater uint32_t er; 2174a7d2b7eSCédric Le Goater uint32_t fr; 2184a7d2b7eSCédric Le Goater uint32_t sr; 2194a7d2b7eSCédric Le Goater }; 2204a7d2b7eSCédric Le Goater 2213b758ca2SCédric Le Goater #define TYPE_PPC405_SOC "ppc405-soc" 2223b758ca2SCédric Le Goater OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); 2233b758ca2SCédric Le Goater 2243b758ca2SCédric Le Goater struct Ppc405SoCState { 2253b758ca2SCédric Le Goater /* Private */ 2263b758ca2SCédric Le Goater DeviceState parent_obj; 2273b758ca2SCédric Le Goater 2283b758ca2SCédric Le Goater /* Public */ 2293b758ca2SCédric Le Goater MemoryRegion ram_banks[2]; 2303b758ca2SCédric Le Goater hwaddr ram_bases[2], ram_sizes[2]; 2315b0f170aSCédric Le Goater bool do_dram_init; 2323b758ca2SCédric Le Goater 2333b758ca2SCédric Le Goater MemoryRegion *dram_mr; 2343b758ca2SCédric Le Goater hwaddr ram_size; 2355b0f170aSCédric Le Goater 236b42ad437SCédric Le Goater PowerPCCPU cpu; 2375b0f170aSCédric Le Goater DeviceState *uic; 2384a7d2b7eSCédric Le Goater Ppc405CpcState cpc; 239269fbb5bSCédric Le Goater Ppc405GptState gpt; 2402847eb40SCédric Le Goater Ppc405OcmState ocm; 241125277c6SCédric Le Goater Ppc405GpioState gpio; 24282c86e30SCédric Le Goater Ppc405DmaState dma; 243415a6333SCédric Le Goater Ppc405EbcState ebc; 24472beecc2SCédric Le Goater Ppc405OpbaState opba; 2452841430eSCédric Le Goater Ppc405PobState pob; 246695bce07SCédric Le Goater Ppc405PlbState plb; 247da116a8aSCédric Le Goater Ppc4xxMalState mal; 2483b758ca2SCédric Le Goater }; 2493b758ca2SCédric Le Goater 25047b43a1fSPaolo Bonzini /* PowerPC 405 core */ 251e3931ecaSCédric Le Goater ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); 25247b43a1fSPaolo Bonzini 253121d0712SMarkus Armbruster #endif /* PPC405_H */ 254