1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/ppc/ppc.h" 31 #include "ppc405.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/block/flash.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/block-backend.h" 37 #include "hw/boards.h" 38 #include "qemu/log.h" 39 #include "qemu/error-report.h" 40 #include "hw/loader.h" 41 #include "exec/address-spaces.h" 42 43 #define BIOS_FILENAME "ppc405_rom.bin" 44 #define BIOS_SIZE (2 * MiB) 45 46 #define KERNEL_LOAD_ADDR 0x00000000 47 #define INITRD_LOAD_ADDR 0x01800000 48 49 #define USE_FLASH_BIOS 50 51 //#define DEBUG_BOARD_INIT 52 53 /*****************************************************************************/ 54 /* PPC405EP reference board (IBM) */ 55 /* Standalone board with: 56 * - PowerPC 405EP CPU 57 * - SDRAM (0x00000000) 58 * - Flash (0xFFF80000) 59 * - SRAM (0xFFF00000) 60 * - NVRAM (0xF0000000) 61 * - FPGA (0xF0300000) 62 */ 63 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 64 struct ref405ep_fpga_t { 65 uint8_t reg0; 66 uint8_t reg1; 67 }; 68 69 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 70 { 71 ref405ep_fpga_t *fpga; 72 uint32_t ret; 73 74 fpga = opaque; 75 switch (addr) { 76 case 0x0: 77 ret = fpga->reg0; 78 break; 79 case 0x1: 80 ret = fpga->reg1; 81 break; 82 default: 83 ret = 0; 84 break; 85 } 86 87 return ret; 88 } 89 90 static void ref405ep_fpga_writeb (void *opaque, 91 hwaddr addr, uint32_t value) 92 { 93 ref405ep_fpga_t *fpga; 94 95 fpga = opaque; 96 switch (addr) { 97 case 0x0: 98 /* Read only */ 99 break; 100 case 0x1: 101 fpga->reg1 = value; 102 break; 103 default: 104 break; 105 } 106 } 107 108 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 109 { 110 uint32_t ret; 111 112 ret = ref405ep_fpga_readb(opaque, addr) << 8; 113 ret |= ref405ep_fpga_readb(opaque, addr + 1); 114 115 return ret; 116 } 117 118 static void ref405ep_fpga_writew (void *opaque, 119 hwaddr addr, uint32_t value) 120 { 121 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 122 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 123 } 124 125 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 126 { 127 uint32_t ret; 128 129 ret = ref405ep_fpga_readb(opaque, addr) << 24; 130 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 131 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 132 ret |= ref405ep_fpga_readb(opaque, addr + 3); 133 134 return ret; 135 } 136 137 static void ref405ep_fpga_writel (void *opaque, 138 hwaddr addr, uint32_t value) 139 { 140 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 141 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 142 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 143 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 144 } 145 146 static const MemoryRegionOps ref405ep_fpga_ops = { 147 .old_mmio = { 148 .read = { 149 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 150 }, 151 .write = { 152 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 153 }, 154 }, 155 .endianness = DEVICE_NATIVE_ENDIAN, 156 }; 157 158 static void ref405ep_fpga_reset (void *opaque) 159 { 160 ref405ep_fpga_t *fpga; 161 162 fpga = opaque; 163 fpga->reg0 = 0x00; 164 fpga->reg1 = 0x0F; 165 } 166 167 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 168 { 169 ref405ep_fpga_t *fpga; 170 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 171 172 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 173 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 174 "fpga", 0x00000100); 175 memory_region_add_subregion(sysmem, base, fpga_memory); 176 qemu_register_reset(&ref405ep_fpga_reset, fpga); 177 } 178 179 static void ref405ep_init(MachineState *machine) 180 { 181 ram_addr_t ram_size = machine->ram_size; 182 const char *kernel_filename = machine->kernel_filename; 183 const char *kernel_cmdline = machine->kernel_cmdline; 184 const char *initrd_filename = machine->initrd_filename; 185 char *filename; 186 ppc4xx_bd_info_t bd; 187 CPUPPCState *env; 188 qemu_irq *pic; 189 MemoryRegion *bios; 190 MemoryRegion *sram = g_new(MemoryRegion, 1); 191 ram_addr_t bdloc; 192 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 193 hwaddr ram_bases[2], ram_sizes[2]; 194 target_ulong sram_size; 195 long bios_size; 196 //int phy_addr = 0; 197 //static int phy_addr = 1; 198 target_ulong kernel_base, initrd_base; 199 long kernel_size, initrd_size; 200 int linux_boot; 201 int fl_idx, fl_sectors, len; 202 DriveInfo *dinfo; 203 MemoryRegion *sysmem = get_system_memory(); 204 205 #ifdef TARGET_PPCEMB 206 if (!qtest_enabled()) { 207 warn_report("qemu-system-ppcemb is deprecated, " 208 "please use qemu-system-ppc instead."); 209 } 210 #endif 211 212 /* XXX: fix this */ 213 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 214 0x08000000); 215 ram_bases[0] = 0; 216 ram_sizes[0] = 0x08000000; 217 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 218 ram_bases[1] = 0x00000000; 219 ram_sizes[1] = 0x00000000; 220 ram_size = 128 * MiB; 221 #ifdef DEBUG_BOARD_INIT 222 printf("%s: register cpu\n", __func__); 223 #endif 224 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 225 33333333, &pic, kernel_filename == NULL ? 0 : 1); 226 /* allocate SRAM */ 227 sram_size = 512 * KiB; 228 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 229 &error_fatal); 230 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 231 /* allocate and load BIOS */ 232 #ifdef DEBUG_BOARD_INIT 233 printf("%s: register BIOS\n", __func__); 234 #endif 235 fl_idx = 0; 236 #ifdef USE_FLASH_BIOS 237 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 238 if (dinfo) { 239 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 240 241 bios_size = blk_getlength(blk); 242 fl_sectors = (bios_size + 65535) >> 16; 243 #ifdef DEBUG_BOARD_INIT 244 printf("Register parallel flash %d size %lx" 245 " at addr %lx '%s' %d\n", 246 fl_idx, bios_size, -bios_size, 247 blk_name(blk), fl_sectors); 248 #endif 249 pflash_cfi02_register((uint32_t)(-bios_size), 250 NULL, "ef405ep.bios", bios_size, 251 blk, 65536, fl_sectors, 1, 252 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 253 1); 254 fl_idx++; 255 } else 256 #endif 257 { 258 #ifdef DEBUG_BOARD_INIT 259 printf("Load BIOS from file\n"); 260 #endif 261 bios = g_new(MemoryRegion, 1); 262 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 263 &error_fatal); 264 265 if (bios_name == NULL) 266 bios_name = BIOS_FILENAME; 267 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 268 if (filename) { 269 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 270 g_free(filename); 271 if (bios_size < 0 || bios_size > BIOS_SIZE) { 272 error_report("Could not load PowerPC BIOS '%s'", bios_name); 273 exit(1); 274 } 275 bios_size = (bios_size + 0xfff) & ~0xfff; 276 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 277 } else if (!qtest_enabled() || kernel_filename != NULL) { 278 error_report("Could not load PowerPC BIOS '%s'", bios_name); 279 exit(1); 280 } else { 281 /* Avoid an uninitialized variable warning */ 282 bios_size = -1; 283 } 284 memory_region_set_readonly(bios, true); 285 } 286 /* Register FPGA */ 287 #ifdef DEBUG_BOARD_INIT 288 printf("%s: register FPGA\n", __func__); 289 #endif 290 ref405ep_fpga_init(sysmem, 0xF0300000); 291 /* Register NVRAM */ 292 #ifdef DEBUG_BOARD_INIT 293 printf("%s: register NVRAM\n", __func__); 294 #endif 295 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 296 /* Load kernel */ 297 linux_boot = (kernel_filename != NULL); 298 if (linux_boot) { 299 #ifdef DEBUG_BOARD_INIT 300 printf("%s: load kernel\n", __func__); 301 #endif 302 memset(&bd, 0, sizeof(bd)); 303 bd.bi_memstart = 0x00000000; 304 bd.bi_memsize = ram_size; 305 bd.bi_flashstart = -bios_size; 306 bd.bi_flashsize = -bios_size; 307 bd.bi_flashoffset = 0; 308 bd.bi_sramstart = 0xFFF00000; 309 bd.bi_sramsize = sram_size; 310 bd.bi_bootflags = 0; 311 bd.bi_intfreq = 133333333; 312 bd.bi_busfreq = 33333333; 313 bd.bi_baudrate = 115200; 314 bd.bi_s_version[0] = 'Q'; 315 bd.bi_s_version[1] = 'M'; 316 bd.bi_s_version[2] = 'U'; 317 bd.bi_s_version[3] = '\0'; 318 bd.bi_r_version[0] = 'Q'; 319 bd.bi_r_version[1] = 'E'; 320 bd.bi_r_version[2] = 'M'; 321 bd.bi_r_version[3] = 'U'; 322 bd.bi_r_version[4] = '\0'; 323 bd.bi_procfreq = 133333333; 324 bd.bi_plb_busfreq = 33333333; 325 bd.bi_pci_busfreq = 33333333; 326 bd.bi_opbfreq = 33333333; 327 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 328 env->gpr[3] = bdloc; 329 kernel_base = KERNEL_LOAD_ADDR; 330 /* now we can load the kernel */ 331 kernel_size = load_image_targphys(kernel_filename, kernel_base, 332 ram_size - kernel_base); 333 if (kernel_size < 0) { 334 error_report("could not load kernel '%s'", kernel_filename); 335 exit(1); 336 } 337 printf("Load kernel size %ld at " TARGET_FMT_lx, 338 kernel_size, kernel_base); 339 /* load initrd */ 340 if (initrd_filename) { 341 initrd_base = INITRD_LOAD_ADDR; 342 initrd_size = load_image_targphys(initrd_filename, initrd_base, 343 ram_size - initrd_base); 344 if (initrd_size < 0) { 345 error_report("could not load initial ram disk '%s'", 346 initrd_filename); 347 exit(1); 348 } 349 } else { 350 initrd_base = 0; 351 initrd_size = 0; 352 } 353 env->gpr[4] = initrd_base; 354 env->gpr[5] = initrd_size; 355 if (kernel_cmdline != NULL) { 356 len = strlen(kernel_cmdline); 357 bdloc -= ((len + 255) & ~255); 358 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 359 env->gpr[6] = bdloc; 360 env->gpr[7] = bdloc + len; 361 } else { 362 env->gpr[6] = 0; 363 env->gpr[7] = 0; 364 } 365 env->nip = KERNEL_LOAD_ADDR; 366 } else { 367 kernel_base = 0; 368 kernel_size = 0; 369 initrd_base = 0; 370 initrd_size = 0; 371 bdloc = 0; 372 } 373 #ifdef DEBUG_BOARD_INIT 374 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 375 printf("%s: Done\n", __func__); 376 #endif 377 } 378 379 static void ref405ep_class_init(ObjectClass *oc, void *data) 380 { 381 MachineClass *mc = MACHINE_CLASS(oc); 382 383 mc->desc = "ref405ep"; 384 mc->init = ref405ep_init; 385 } 386 387 static const TypeInfo ref405ep_type = { 388 .name = MACHINE_TYPE_NAME("ref405ep"), 389 .parent = TYPE_MACHINE, 390 .class_init = ref405ep_class_init, 391 }; 392 393 /*****************************************************************************/ 394 /* AMCC Taihu evaluation board */ 395 /* - PowerPC 405EP processor 396 * - SDRAM 128 MB at 0x00000000 397 * - Boot flash 2 MB at 0xFFE00000 398 * - Application flash 32 MB at 0xFC000000 399 * - 2 serial ports 400 * - 2 ethernet PHY 401 * - 1 USB 1.1 device 0x50000000 402 * - 1 LCD display 0x50100000 403 * - 1 CPLD 0x50100000 404 * - 1 I2C EEPROM 405 * - 1 I2C thermal sensor 406 * - a set of LEDs 407 * - bit-bang SPI port using GPIOs 408 * - 1 EBC interface connector 0 0x50200000 409 * - 1 cardbus controller + expansion slot. 410 * - 1 PCI expansion slot. 411 */ 412 typedef struct taihu_cpld_t taihu_cpld_t; 413 struct taihu_cpld_t { 414 uint8_t reg0; 415 uint8_t reg1; 416 }; 417 418 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 419 { 420 taihu_cpld_t *cpld; 421 uint32_t ret; 422 423 cpld = opaque; 424 switch (addr) { 425 case 0x0: 426 ret = cpld->reg0; 427 break; 428 case 0x1: 429 ret = cpld->reg1; 430 break; 431 default: 432 ret = 0; 433 break; 434 } 435 436 return ret; 437 } 438 439 static void taihu_cpld_write(void *opaque, hwaddr addr, 440 uint64_t value, unsigned size) 441 { 442 taihu_cpld_t *cpld; 443 444 cpld = opaque; 445 switch (addr) { 446 case 0x0: 447 /* Read only */ 448 break; 449 case 0x1: 450 cpld->reg1 = value; 451 break; 452 default: 453 break; 454 } 455 } 456 457 static const MemoryRegionOps taihu_cpld_ops = { 458 .read = taihu_cpld_read, 459 .write = taihu_cpld_write, 460 .impl = { 461 .min_access_size = 1, 462 .max_access_size = 1, 463 }, 464 .endianness = DEVICE_NATIVE_ENDIAN, 465 }; 466 467 static void taihu_cpld_reset (void *opaque) 468 { 469 taihu_cpld_t *cpld; 470 471 cpld = opaque; 472 cpld->reg0 = 0x01; 473 cpld->reg1 = 0x80; 474 } 475 476 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 477 { 478 taihu_cpld_t *cpld; 479 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 480 481 cpld = g_malloc0(sizeof(taihu_cpld_t)); 482 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 483 memory_region_add_subregion(sysmem, base, cpld_memory); 484 qemu_register_reset(&taihu_cpld_reset, cpld); 485 } 486 487 static void taihu_405ep_init(MachineState *machine) 488 { 489 ram_addr_t ram_size = machine->ram_size; 490 const char *kernel_filename = machine->kernel_filename; 491 const char *initrd_filename = machine->initrd_filename; 492 char *filename; 493 qemu_irq *pic; 494 MemoryRegion *sysmem = get_system_memory(); 495 MemoryRegion *bios; 496 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 497 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 498 hwaddr ram_bases[2], ram_sizes[2]; 499 long bios_size; 500 target_ulong kernel_base, initrd_base; 501 long kernel_size, initrd_size; 502 int linux_boot; 503 int fl_idx, fl_sectors; 504 DriveInfo *dinfo; 505 506 #ifdef TARGET_PPCEMB 507 if (!qtest_enabled()) { 508 warn_report("qemu-system-ppcemb is deprecated, " 509 "please use qemu-system-ppc instead."); 510 } 511 #endif 512 513 /* RAM is soldered to the board so the size cannot be changed */ 514 ram_size = 0x08000000; 515 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 516 ram_size); 517 518 ram_bases[0] = 0; 519 ram_sizes[0] = 0x04000000; 520 memory_region_init_alias(&ram_memories[0], NULL, 521 "taihu_405ep.ram-0", ram, ram_bases[0], 522 ram_sizes[0]); 523 ram_bases[1] = 0x04000000; 524 ram_sizes[1] = 0x04000000; 525 memory_region_init_alias(&ram_memories[1], NULL, 526 "taihu_405ep.ram-1", ram, ram_bases[1], 527 ram_sizes[1]); 528 #ifdef DEBUG_BOARD_INIT 529 printf("%s: register cpu\n", __func__); 530 #endif 531 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 532 33333333, &pic, kernel_filename == NULL ? 0 : 1); 533 /* allocate and load BIOS */ 534 #ifdef DEBUG_BOARD_INIT 535 printf("%s: register BIOS\n", __func__); 536 #endif 537 fl_idx = 0; 538 #if defined(USE_FLASH_BIOS) 539 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 540 if (dinfo) { 541 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 542 543 bios_size = blk_getlength(blk); 544 /* XXX: should check that size is 2MB */ 545 // bios_size = 2 * 1024 * 1024; 546 fl_sectors = (bios_size + 65535) >> 16; 547 #ifdef DEBUG_BOARD_INIT 548 printf("Register parallel flash %d size %lx" 549 " at addr %lx '%s' %d\n", 550 fl_idx, bios_size, -bios_size, 551 blk_name(blk), fl_sectors); 552 #endif 553 pflash_cfi02_register((uint32_t)(-bios_size), 554 NULL, "taihu_405ep.bios", bios_size, 555 blk, 65536, fl_sectors, 1, 556 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 557 1); 558 fl_idx++; 559 } else 560 #endif 561 { 562 #ifdef DEBUG_BOARD_INIT 563 printf("Load BIOS from file\n"); 564 #endif 565 if (bios_name == NULL) 566 bios_name = BIOS_FILENAME; 567 bios = g_new(MemoryRegion, 1); 568 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 569 &error_fatal); 570 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 571 if (filename) { 572 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 573 g_free(filename); 574 if (bios_size < 0 || bios_size > BIOS_SIZE) { 575 error_report("Could not load PowerPC BIOS '%s'", bios_name); 576 exit(1); 577 } 578 bios_size = (bios_size + 0xfff) & ~0xfff; 579 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 580 } else if (!qtest_enabled()) { 581 error_report("Could not load PowerPC BIOS '%s'", bios_name); 582 exit(1); 583 } 584 memory_region_set_readonly(bios, true); 585 } 586 /* Register Linux flash */ 587 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 588 if (dinfo) { 589 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 590 591 bios_size = blk_getlength(blk); 592 /* XXX: should check that size is 32MB */ 593 bios_size = 32 * MiB; 594 fl_sectors = (bios_size + 65535) >> 16; 595 #ifdef DEBUG_BOARD_INIT 596 printf("Register parallel flash %d size %lx" 597 " at addr " TARGET_FMT_lx " '%s'\n", 598 fl_idx, bios_size, (target_ulong)0xfc000000, 599 blk_name(blk)); 600 #endif 601 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 602 blk, 65536, fl_sectors, 1, 603 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 604 1); 605 fl_idx++; 606 } 607 /* Register CLPD & LCD display */ 608 #ifdef DEBUG_BOARD_INIT 609 printf("%s: register CPLD\n", __func__); 610 #endif 611 taihu_cpld_init(sysmem, 0x50100000); 612 /* Load kernel */ 613 linux_boot = (kernel_filename != NULL); 614 if (linux_boot) { 615 #ifdef DEBUG_BOARD_INIT 616 printf("%s: load kernel\n", __func__); 617 #endif 618 kernel_base = KERNEL_LOAD_ADDR; 619 /* now we can load the kernel */ 620 kernel_size = load_image_targphys(kernel_filename, kernel_base, 621 ram_size - kernel_base); 622 if (kernel_size < 0) { 623 error_report("could not load kernel '%s'", kernel_filename); 624 exit(1); 625 } 626 /* load initrd */ 627 if (initrd_filename) { 628 initrd_base = INITRD_LOAD_ADDR; 629 initrd_size = load_image_targphys(initrd_filename, initrd_base, 630 ram_size - initrd_base); 631 if (initrd_size < 0) { 632 error_report("could not load initial ram disk '%s'", 633 initrd_filename); 634 exit(1); 635 } 636 } else { 637 initrd_base = 0; 638 initrd_size = 0; 639 } 640 } else { 641 kernel_base = 0; 642 kernel_size = 0; 643 initrd_base = 0; 644 initrd_size = 0; 645 } 646 #ifdef DEBUG_BOARD_INIT 647 printf("%s: Done\n", __func__); 648 #endif 649 } 650 651 static void taihu_class_init(ObjectClass *oc, void *data) 652 { 653 MachineClass *mc = MACHINE_CLASS(oc); 654 655 mc->desc = "taihu"; 656 mc->init = taihu_405ep_init; 657 } 658 659 static const TypeInfo taihu_type = { 660 .name = MACHINE_TYPE_NAME("taihu"), 661 .parent = TYPE_MACHINE, 662 .class_init = taihu_class_init, 663 }; 664 665 static void ppc405_machine_init(void) 666 { 667 type_register_static(&ref405ep_type); 668 type_register_static(&taihu_type); 669 } 670 671 type_init(ppc405_machine_init) 672