1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/sysbus.h" 33 #include "ppc405.h" 34 #include "hw/rtc/m48t59.h" 35 #include "hw/block/flash.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/block-backend.h" 39 #include "hw/boards.h" 40 #include "qemu/error-report.h" 41 #include "hw/loader.h" 42 #include "qemu/cutils.h" 43 #include "elf.h" 44 45 #define BIOS_FILENAME "ppc405_rom.bin" 46 #define BIOS_SIZE (2 * MiB) 47 48 #define KERNEL_LOAD_ADDR 0x01000000 49 #define INITRD_LOAD_ADDR 0x01800000 50 51 #define PPC405EP_SDRAM_BASE 0x00000000 52 #define PPC405EP_SRAM_BASE 0xFFF00000 53 #define PPC405EP_SRAM_SIZE (512 * KiB) 54 55 #define USE_FLASH_BIOS 56 57 #define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405") 58 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE); 59 60 struct Ppc405MachineState { 61 /* Private */ 62 MachineState parent_obj; 63 /* Public */ 64 65 Ppc405SoCState soc; 66 }; 67 68 /* CPU reset handler when booting directly from a loaded kernel */ 69 static struct boot_info { 70 uint32_t entry; 71 uint32_t bdloc; 72 uint32_t initrd_base; 73 uint32_t initrd_size; 74 uint32_t cmdline_base; 75 uint32_t cmdline_size; 76 } boot_info; 77 78 static void main_cpu_reset(void *opaque) 79 { 80 PowerPCCPU *cpu = opaque; 81 CPUPPCState *env = &cpu->env; 82 struct boot_info *bi = env->load_info; 83 84 cpu_reset(CPU(cpu)); 85 86 /* stack: top of sram */ 87 env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8; 88 89 /* Tune our boot state */ 90 env->gpr[3] = bi->bdloc; 91 env->gpr[4] = bi->initrd_base; 92 env->gpr[5] = bi->initrd_base + bi->initrd_size; 93 env->gpr[6] = bi->cmdline_base; 94 env->gpr[7] = bi->cmdline_size; 95 96 env->nip = bi->entry; 97 } 98 99 /* Bootinfo as set-up by u-boot */ 100 typedef struct { 101 uint32_t bi_memstart; 102 uint32_t bi_memsize; 103 uint32_t bi_flashstart; 104 uint32_t bi_flashsize; 105 uint32_t bi_flashoffset; /* 0x10 */ 106 uint32_t bi_sramstart; 107 uint32_t bi_sramsize; 108 uint32_t bi_bootflags; 109 uint32_t bi_ipaddr; /* 0x20 */ 110 uint8_t bi_enetaddr[6]; 111 uint16_t bi_ethspeed; 112 uint32_t bi_intfreq; 113 uint32_t bi_busfreq; /* 0x30 */ 114 uint32_t bi_baudrate; 115 uint8_t bi_s_version[4]; 116 uint8_t bi_r_version[32]; 117 uint32_t bi_procfreq; 118 uint32_t bi_plb_busfreq; 119 uint32_t bi_pci_busfreq; 120 uint8_t bi_pci_enetaddr[6]; 121 uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ 122 uint32_t bi_opbfreq; 123 uint32_t bi_iic_fast[2]; 124 } ppc4xx_bd_info_t; 125 126 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, 127 ram_addr_t ram_size) 128 { 129 memset(bd, 0, sizeof(*bd)); 130 131 bd->bi_memstart = PPC405EP_SDRAM_BASE; 132 bd->bi_memsize = ram_size; 133 bd->bi_sramstart = PPC405EP_SRAM_BASE; 134 bd->bi_sramsize = PPC405EP_SRAM_SIZE; 135 bd->bi_bootflags = 0; 136 bd->bi_intfreq = 133333333; 137 bd->bi_busfreq = 33333333; 138 bd->bi_baudrate = 115200; 139 bd->bi_s_version[0] = 'Q'; 140 bd->bi_s_version[1] = 'M'; 141 bd->bi_s_version[2] = 'U'; 142 bd->bi_s_version[3] = '\0'; 143 bd->bi_r_version[0] = 'Q'; 144 bd->bi_r_version[1] = 'E'; 145 bd->bi_r_version[2] = 'M'; 146 bd->bi_r_version[3] = 'U'; 147 bd->bi_r_version[4] = '\0'; 148 bd->bi_procfreq = 133333333; 149 bd->bi_plb_busfreq = 33333333; 150 bd->bi_pci_busfreq = 33333333; 151 bd->bi_opbfreq = 33333333; 152 } 153 154 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) 155 { 156 CPUState *cs = env_cpu(env); 157 ram_addr_t bdloc; 158 int i, n; 159 160 /* We put the bd structure at the top of memory */ 161 if (bd->bi_memsize >= 0x01000000UL) { 162 bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t); 163 } else { 164 bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t); 165 } 166 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 167 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 168 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 169 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 170 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 171 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 172 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 173 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 174 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 175 for (i = 0; i < 6; i++) { 176 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 177 } 178 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 179 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 180 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 181 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 182 for (i = 0; i < 4; i++) { 183 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 184 } 185 for (i = 0; i < 32; i++) { 186 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 187 } 188 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); 189 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); 190 stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); 191 for (i = 0; i < 6; i++) { 192 stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); 193 } 194 n = 0x70; /* includes 2 bytes hole */ 195 for (i = 0; i < 6; i++) { 196 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 197 } 198 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 199 n += 4; 200 for (i = 0; i < 2; i++) { 201 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 202 n += 4; 203 } 204 205 return bdloc; 206 } 207 208 static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) 209 { 210 ppc4xx_bd_info_t bd; 211 212 memset(&bd, 0, sizeof(bd)); 213 214 ppc405_set_default_bootinfo(&bd, ram_size); 215 216 return __ppc405_set_bootinfo(env, &bd); 217 } 218 219 static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) 220 { 221 CPUPPCState *env = &cpu->env; 222 hwaddr boot_entry; 223 hwaddr kernel_base; 224 int kernel_size; 225 hwaddr initrd_base; 226 int initrd_size; 227 ram_addr_t bdloc; 228 int len; 229 230 bdloc = ppc405_set_bootinfo(env, machine->ram_size); 231 boot_info.bdloc = bdloc; 232 233 kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL, 234 &boot_entry, &kernel_base, NULL, NULL, 235 1, PPC_ELF_MACHINE, 0, 0); 236 if (kernel_size < 0) { 237 error_report("Could not load kernel '%s' : %s", 238 machine->kernel_filename, load_elf_strerror(kernel_size)); 239 exit(1); 240 } 241 boot_info.entry = boot_entry; 242 243 /* load initrd */ 244 if (machine->initrd_filename) { 245 initrd_base = INITRD_LOAD_ADDR; 246 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 247 machine->ram_size - initrd_base); 248 if (initrd_size < 0) { 249 error_report("could not load initial ram disk '%s'", 250 machine->initrd_filename); 251 exit(1); 252 } 253 254 boot_info.initrd_base = initrd_base; 255 boot_info.initrd_size = initrd_size; 256 } 257 258 if (machine->kernel_cmdline) { 259 len = strlen(machine->kernel_cmdline); 260 bdloc -= ((len + 255) & ~255); 261 cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1); 262 boot_info.cmdline_base = bdloc; 263 boot_info.cmdline_size = bdloc + len; 264 } 265 266 /* Install our custom reset handler to start from Linux */ 267 qemu_register_reset(main_cpu_reset, cpu); 268 env->load_info = &boot_info; 269 } 270 271 static void ppc405_init(MachineState *machine) 272 { 273 Ppc405MachineState *ppc405 = PPC405_MACHINE(machine); 274 MachineClass *mc = MACHINE_GET_CLASS(machine); 275 const char *kernel_filename = machine->kernel_filename; 276 MemoryRegion *sysmem = get_system_memory(); 277 278 if (machine->ram_size != mc->default_ram_size) { 279 char *sz = size_to_str(mc->default_ram_size); 280 error_report("Invalid RAM size, should be %s", sz); 281 g_free(sz); 282 exit(EXIT_FAILURE); 283 } 284 285 object_initialize_child(OBJECT(machine), "soc", &ppc405->soc, 286 TYPE_PPC405_SOC); 287 object_property_set_uint(OBJECT(&ppc405->soc), "ram-size", 288 machine->ram_size, &error_fatal); 289 object_property_set_link(OBJECT(&ppc405->soc), "dram", 290 OBJECT(machine->ram), &error_abort); 291 object_property_set_bool(OBJECT(&ppc405->soc), "dram-init", 292 kernel_filename != NULL, &error_abort); 293 object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, 294 &error_abort); 295 qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal); 296 297 /* allocate and load BIOS */ 298 if (machine->firmware) { 299 MemoryRegion *bios = g_new(MemoryRegion, 1); 300 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 301 machine->firmware); 302 long bios_size; 303 304 memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, 305 &error_fatal); 306 307 if (!filename) { 308 error_report("Could not find firmware '%s'", machine->firmware); 309 exit(1); 310 } 311 312 bios_size = load_image_size(filename, 313 memory_region_get_ram_ptr(bios), 314 BIOS_SIZE); 315 if (bios_size < 0) { 316 error_report("Could not load PowerPC BIOS '%s'", machine->firmware); 317 exit(1); 318 } 319 320 bios_size = (bios_size + 0xfff) & ~0xfff; 321 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 322 } 323 324 /* Load kernel and initrd using U-Boot images */ 325 if (kernel_filename && machine->firmware) { 326 target_ulong kernel_base, initrd_base; 327 long kernel_size, initrd_size; 328 329 kernel_base = KERNEL_LOAD_ADDR; 330 kernel_size = load_image_targphys(kernel_filename, kernel_base, 331 machine->ram_size - kernel_base); 332 if (kernel_size < 0) { 333 error_report("could not load kernel '%s'", kernel_filename); 334 exit(1); 335 } 336 337 /* load initrd */ 338 if (machine->initrd_filename) { 339 initrd_base = INITRD_LOAD_ADDR; 340 initrd_size = load_image_targphys(machine->initrd_filename, 341 initrd_base, 342 machine->ram_size - initrd_base); 343 if (initrd_size < 0) { 344 error_report("could not load initial ram disk '%s'", 345 machine->initrd_filename); 346 exit(1); 347 } 348 } 349 350 /* Load ELF kernel and rootfs.cpio */ 351 } else if (kernel_filename && !machine->firmware) { 352 boot_from_kernel(machine, &ppc405->soc.cpu); 353 } 354 } 355 356 static void ppc405_machine_class_init(ObjectClass *oc, void *data) 357 { 358 MachineClass *mc = MACHINE_CLASS(oc); 359 360 mc->desc = "PPC405 generic machine"; 361 mc->init = ppc405_init; 362 mc->default_ram_size = 128 * MiB; 363 mc->default_ram_id = "ppc405.ram"; 364 } 365 366 static const TypeInfo ppc405_machine_type = { 367 .name = TYPE_PPC405_MACHINE, 368 .parent = TYPE_MACHINE, 369 .instance_size = sizeof(Ppc405MachineState), 370 .class_init = ppc405_machine_class_init, 371 .abstract = true, 372 }; 373 374 /*****************************************************************************/ 375 /* PPC405EP reference board (IBM) */ 376 /* 377 * Standalone board with: 378 * - PowerPC 405EP CPU 379 * - SDRAM (0x00000000) 380 * - Flash (0xFFF80000) 381 * - SRAM (0xFFF00000) 382 * - NVRAM (0xF0000000) 383 * - FPGA (0xF0300000) 384 */ 385 386 #define PPC405EP_NVRAM_BASE 0xF0000000 387 #define PPC405EP_FPGA_BASE 0xF0300000 388 #define PPC405EP_FLASH_BASE 0xFFF80000 389 390 #define TYPE_REF405EP_FPGA "ref405ep-fpga" 391 OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA); 392 struct Ref405epFpgaState { 393 SysBusDevice parent_obj; 394 395 MemoryRegion iomem; 396 397 uint8_t reg0; 398 uint8_t reg1; 399 }; 400 401 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) 402 { 403 Ref405epFpgaState *fpga = opaque; 404 uint32_t ret; 405 406 switch (addr) { 407 case 0x0: 408 ret = fpga->reg0; 409 break; 410 case 0x1: 411 ret = fpga->reg1; 412 break; 413 default: 414 ret = 0; 415 break; 416 } 417 418 return ret; 419 } 420 421 static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, 422 unsigned size) 423 { 424 Ref405epFpgaState *fpga = opaque; 425 426 switch (addr) { 427 case 0x0: 428 /* Read only */ 429 break; 430 case 0x1: 431 fpga->reg1 = value; 432 break; 433 default: 434 break; 435 } 436 } 437 438 static const MemoryRegionOps ref405ep_fpga_ops = { 439 .read = ref405ep_fpga_readb, 440 .write = ref405ep_fpga_writeb, 441 .impl.min_access_size = 1, 442 .impl.max_access_size = 1, 443 .valid.min_access_size = 1, 444 .valid.max_access_size = 4, 445 .endianness = DEVICE_BIG_ENDIAN, 446 }; 447 448 static void ref405ep_fpga_reset(DeviceState *dev) 449 { 450 Ref405epFpgaState *fpga = REF405EP_FPGA(dev); 451 452 fpga->reg0 = 0x00; 453 fpga->reg1 = 0x0F; 454 } 455 456 static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) 457 { 458 Ref405epFpgaState *s = REF405EP_FPGA(dev); 459 460 memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, 461 "fpga", 0x00000100); 462 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 463 } 464 465 static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) 466 { 467 DeviceClass *dc = DEVICE_CLASS(oc); 468 469 dc->realize = ref405ep_fpga_realize; 470 dc->reset = ref405ep_fpga_reset; 471 /* Reason: only works as part of a ppc405 board */ 472 dc->user_creatable = false; 473 } 474 475 static const TypeInfo ref405ep_fpga_type = { 476 .name = TYPE_REF405EP_FPGA, 477 .parent = TYPE_SYS_BUS_DEVICE, 478 .instance_size = sizeof(Ref405epFpgaState), 479 .class_init = ref405ep_fpga_class_init, 480 }; 481 482 static void ref405ep_init(MachineState *machine) 483 { 484 DeviceState *dev; 485 SysBusDevice *s; 486 MemoryRegion *sram = g_new(MemoryRegion, 1); 487 488 ppc405_init(machine); 489 490 /* allocate SRAM */ 491 memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE, 492 &error_fatal); 493 memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram); 494 495 /* Register FPGA */ 496 dev = qdev_new(TYPE_REF405EP_FPGA); 497 object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev)); 498 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 499 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE); 500 501 /* Register NVRAM */ 502 dev = qdev_new("sysbus-m48t08"); 503 qdev_prop_set_int32(dev, "base-year", 1968); 504 s = SYS_BUS_DEVICE(dev); 505 sysbus_realize_and_unref(s, &error_fatal); 506 sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); 507 } 508 509 static void ref405ep_class_init(ObjectClass *oc, void *data) 510 { 511 MachineClass *mc = MACHINE_CLASS(oc); 512 513 mc->desc = "ref405ep"; 514 mc->init = ref405ep_init; 515 } 516 517 static const TypeInfo ref405ep_type = { 518 .name = MACHINE_TYPE_NAME("ref405ep"), 519 .parent = TYPE_PPC405_MACHINE, 520 .class_init = ref405ep_class_init, 521 }; 522 523 static void ppc405_machine_init(void) 524 { 525 type_register_static(&ppc405_machine_type); 526 type_register_static(&ref405ep_type); 527 type_register_static(&ref405ep_fpga_type); 528 } 529 530 type_init(ppc405_machine_init) 531