1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "ppc405.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/qtest.h" 31 #include "block/block.h" 32 #include "hw/boards.h" 33 #include "qemu/log.h" 34 #include "qemu/error-report.h" 35 #include "hw/loader.h" 36 #include "sysemu/blockdev.h" 37 #include "exec/address-spaces.h" 38 39 #define BIOS_FILENAME "ppc405_rom.bin" 40 #define BIOS_SIZE (2048 * 1024) 41 42 #define KERNEL_LOAD_ADDR 0x00000000 43 #define INITRD_LOAD_ADDR 0x01800000 44 45 #define USE_FLASH_BIOS 46 47 //#define DEBUG_BOARD_INIT 48 49 /*****************************************************************************/ 50 /* PPC405EP reference board (IBM) */ 51 /* Standalone board with: 52 * - PowerPC 405EP CPU 53 * - SDRAM (0x00000000) 54 * - Flash (0xFFF80000) 55 * - SRAM (0xFFF00000) 56 * - NVRAM (0xF0000000) 57 * - FPGA (0xF0300000) 58 */ 59 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 60 struct ref405ep_fpga_t { 61 uint8_t reg0; 62 uint8_t reg1; 63 }; 64 65 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 66 { 67 ref405ep_fpga_t *fpga; 68 uint32_t ret; 69 70 fpga = opaque; 71 switch (addr) { 72 case 0x0: 73 ret = fpga->reg0; 74 break; 75 case 0x1: 76 ret = fpga->reg1; 77 break; 78 default: 79 ret = 0; 80 break; 81 } 82 83 return ret; 84 } 85 86 static void ref405ep_fpga_writeb (void *opaque, 87 hwaddr addr, uint32_t value) 88 { 89 ref405ep_fpga_t *fpga; 90 91 fpga = opaque; 92 switch (addr) { 93 case 0x0: 94 /* Read only */ 95 break; 96 case 0x1: 97 fpga->reg1 = value; 98 break; 99 default: 100 break; 101 } 102 } 103 104 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 105 { 106 uint32_t ret; 107 108 ret = ref405ep_fpga_readb(opaque, addr) << 8; 109 ret |= ref405ep_fpga_readb(opaque, addr + 1); 110 111 return ret; 112 } 113 114 static void ref405ep_fpga_writew (void *opaque, 115 hwaddr addr, uint32_t value) 116 { 117 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 118 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 119 } 120 121 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 122 { 123 uint32_t ret; 124 125 ret = ref405ep_fpga_readb(opaque, addr) << 24; 126 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 127 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 128 ret |= ref405ep_fpga_readb(opaque, addr + 3); 129 130 return ret; 131 } 132 133 static void ref405ep_fpga_writel (void *opaque, 134 hwaddr addr, uint32_t value) 135 { 136 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 137 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 138 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 139 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 140 } 141 142 static const MemoryRegionOps ref405ep_fpga_ops = { 143 .old_mmio = { 144 .read = { 145 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 146 }, 147 .write = { 148 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 149 }, 150 }, 151 .endianness = DEVICE_NATIVE_ENDIAN, 152 }; 153 154 static void ref405ep_fpga_reset (void *opaque) 155 { 156 ref405ep_fpga_t *fpga; 157 158 fpga = opaque; 159 fpga->reg0 = 0x00; 160 fpga->reg1 = 0x0F; 161 } 162 163 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 164 { 165 ref405ep_fpga_t *fpga; 166 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 167 168 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 169 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 170 "fpga", 0x00000100); 171 memory_region_add_subregion(sysmem, base, fpga_memory); 172 qemu_register_reset(&ref405ep_fpga_reset, fpga); 173 } 174 175 static void ref405ep_init(MachineState *machine) 176 { 177 ram_addr_t ram_size = machine->ram_size; 178 const char *kernel_filename = machine->kernel_filename; 179 const char *kernel_cmdline = machine->kernel_cmdline; 180 const char *initrd_filename = machine->initrd_filename; 181 char *filename; 182 ppc4xx_bd_info_t bd; 183 CPUPPCState *env; 184 qemu_irq *pic; 185 MemoryRegion *bios; 186 MemoryRegion *sram = g_new(MemoryRegion, 1); 187 ram_addr_t bdloc; 188 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 189 hwaddr ram_bases[2], ram_sizes[2]; 190 target_ulong sram_size; 191 long bios_size; 192 //int phy_addr = 0; 193 //static int phy_addr = 1; 194 target_ulong kernel_base, initrd_base; 195 long kernel_size, initrd_size; 196 int linux_boot; 197 int fl_idx, fl_sectors, len; 198 DriveInfo *dinfo; 199 MemoryRegion *sysmem = get_system_memory(); 200 201 /* XXX: fix this */ 202 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 203 0x08000000); 204 ram_bases[0] = 0; 205 ram_sizes[0] = 0x08000000; 206 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 207 ram_bases[1] = 0x00000000; 208 ram_sizes[1] = 0x00000000; 209 ram_size = 128 * 1024 * 1024; 210 #ifdef DEBUG_BOARD_INIT 211 printf("%s: register cpu\n", __func__); 212 #endif 213 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 214 33333333, &pic, kernel_filename == NULL ? 0 : 1); 215 /* allocate SRAM */ 216 sram_size = 512 * 1024; 217 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size); 218 vmstate_register_ram_global(sram); 219 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 220 /* allocate and load BIOS */ 221 #ifdef DEBUG_BOARD_INIT 222 printf("%s: register BIOS\n", __func__); 223 #endif 224 fl_idx = 0; 225 #ifdef USE_FLASH_BIOS 226 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 227 if (dinfo) { 228 bios_size = bdrv_getlength(dinfo->bdrv); 229 fl_sectors = (bios_size + 65535) >> 16; 230 #ifdef DEBUG_BOARD_INIT 231 printf("Register parallel flash %d size %lx" 232 " at addr %lx '%s' %d\n", 233 fl_idx, bios_size, -bios_size, 234 bdrv_get_device_name(dinfo->bdrv), fl_sectors); 235 #endif 236 pflash_cfi02_register((uint32_t)(-bios_size), 237 NULL, "ef405ep.bios", bios_size, 238 dinfo->bdrv, 65536, fl_sectors, 1, 239 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 240 1); 241 fl_idx++; 242 } else 243 #endif 244 { 245 #ifdef DEBUG_BOARD_INIT 246 printf("Load BIOS from file\n"); 247 #endif 248 bios = g_new(MemoryRegion, 1); 249 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE); 250 vmstate_register_ram_global(bios); 251 252 if (bios_name == NULL) 253 bios_name = BIOS_FILENAME; 254 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 255 if (filename) { 256 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 257 g_free(filename); 258 if (bios_size < 0 || bios_size > BIOS_SIZE) { 259 error_report("Could not load PowerPC BIOS '%s'", bios_name); 260 exit(1); 261 } 262 bios_size = (bios_size + 0xfff) & ~0xfff; 263 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 264 } else if (!qtest_enabled() || kernel_filename != NULL) { 265 error_report("Could not load PowerPC BIOS '%s'", bios_name); 266 exit(1); 267 } else { 268 /* Avoid an uninitialized variable warning */ 269 bios_size = -1; 270 } 271 memory_region_set_readonly(bios, true); 272 } 273 /* Register FPGA */ 274 #ifdef DEBUG_BOARD_INIT 275 printf("%s: register FPGA\n", __func__); 276 #endif 277 ref405ep_fpga_init(sysmem, 0xF0300000); 278 /* Register NVRAM */ 279 #ifdef DEBUG_BOARD_INIT 280 printf("%s: register NVRAM\n", __func__); 281 #endif 282 m48t59_init(NULL, 0xF0000000, 0, 8192, 8); 283 /* Load kernel */ 284 linux_boot = (kernel_filename != NULL); 285 if (linux_boot) { 286 #ifdef DEBUG_BOARD_INIT 287 printf("%s: load kernel\n", __func__); 288 #endif 289 memset(&bd, 0, sizeof(bd)); 290 bd.bi_memstart = 0x00000000; 291 bd.bi_memsize = ram_size; 292 bd.bi_flashstart = -bios_size; 293 bd.bi_flashsize = -bios_size; 294 bd.bi_flashoffset = 0; 295 bd.bi_sramstart = 0xFFF00000; 296 bd.bi_sramsize = sram_size; 297 bd.bi_bootflags = 0; 298 bd.bi_intfreq = 133333333; 299 bd.bi_busfreq = 33333333; 300 bd.bi_baudrate = 115200; 301 bd.bi_s_version[0] = 'Q'; 302 bd.bi_s_version[1] = 'M'; 303 bd.bi_s_version[2] = 'U'; 304 bd.bi_s_version[3] = '\0'; 305 bd.bi_r_version[0] = 'Q'; 306 bd.bi_r_version[1] = 'E'; 307 bd.bi_r_version[2] = 'M'; 308 bd.bi_r_version[3] = 'U'; 309 bd.bi_r_version[4] = '\0'; 310 bd.bi_procfreq = 133333333; 311 bd.bi_plb_busfreq = 33333333; 312 bd.bi_pci_busfreq = 33333333; 313 bd.bi_opbfreq = 33333333; 314 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 315 env->gpr[3] = bdloc; 316 kernel_base = KERNEL_LOAD_ADDR; 317 /* now we can load the kernel */ 318 kernel_size = load_image_targphys(kernel_filename, kernel_base, 319 ram_size - kernel_base); 320 if (kernel_size < 0) { 321 fprintf(stderr, "qemu: could not load kernel '%s'\n", 322 kernel_filename); 323 exit(1); 324 } 325 printf("Load kernel size %ld at " TARGET_FMT_lx, 326 kernel_size, kernel_base); 327 /* load initrd */ 328 if (initrd_filename) { 329 initrd_base = INITRD_LOAD_ADDR; 330 initrd_size = load_image_targphys(initrd_filename, initrd_base, 331 ram_size - initrd_base); 332 if (initrd_size < 0) { 333 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 334 initrd_filename); 335 exit(1); 336 } 337 } else { 338 initrd_base = 0; 339 initrd_size = 0; 340 } 341 env->gpr[4] = initrd_base; 342 env->gpr[5] = initrd_size; 343 if (kernel_cmdline != NULL) { 344 len = strlen(kernel_cmdline); 345 bdloc -= ((len + 255) & ~255); 346 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 347 env->gpr[6] = bdloc; 348 env->gpr[7] = bdloc + len; 349 } else { 350 env->gpr[6] = 0; 351 env->gpr[7] = 0; 352 } 353 env->nip = KERNEL_LOAD_ADDR; 354 } else { 355 kernel_base = 0; 356 kernel_size = 0; 357 initrd_base = 0; 358 initrd_size = 0; 359 bdloc = 0; 360 } 361 #ifdef DEBUG_BOARD_INIT 362 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 363 printf("%s: Done\n", __func__); 364 #endif 365 } 366 367 static QEMUMachine ref405ep_machine = { 368 .name = "ref405ep", 369 .desc = "ref405ep", 370 .init = ref405ep_init, 371 }; 372 373 /*****************************************************************************/ 374 /* AMCC Taihu evaluation board */ 375 /* - PowerPC 405EP processor 376 * - SDRAM 128 MB at 0x00000000 377 * - Boot flash 2 MB at 0xFFE00000 378 * - Application flash 32 MB at 0xFC000000 379 * - 2 serial ports 380 * - 2 ethernet PHY 381 * - 1 USB 1.1 device 0x50000000 382 * - 1 LCD display 0x50100000 383 * - 1 CPLD 0x50100000 384 * - 1 I2C EEPROM 385 * - 1 I2C thermal sensor 386 * - a set of LEDs 387 * - bit-bang SPI port using GPIOs 388 * - 1 EBC interface connector 0 0x50200000 389 * - 1 cardbus controller + expansion slot. 390 * - 1 PCI expansion slot. 391 */ 392 typedef struct taihu_cpld_t taihu_cpld_t; 393 struct taihu_cpld_t { 394 uint8_t reg0; 395 uint8_t reg1; 396 }; 397 398 static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr) 399 { 400 taihu_cpld_t *cpld; 401 uint32_t ret; 402 403 cpld = opaque; 404 switch (addr) { 405 case 0x0: 406 ret = cpld->reg0; 407 break; 408 case 0x1: 409 ret = cpld->reg1; 410 break; 411 default: 412 ret = 0; 413 break; 414 } 415 416 return ret; 417 } 418 419 static void taihu_cpld_writeb (void *opaque, 420 hwaddr addr, uint32_t value) 421 { 422 taihu_cpld_t *cpld; 423 424 cpld = opaque; 425 switch (addr) { 426 case 0x0: 427 /* Read only */ 428 break; 429 case 0x1: 430 cpld->reg1 = value; 431 break; 432 default: 433 break; 434 } 435 } 436 437 static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr) 438 { 439 uint32_t ret; 440 441 ret = taihu_cpld_readb(opaque, addr) << 8; 442 ret |= taihu_cpld_readb(opaque, addr + 1); 443 444 return ret; 445 } 446 447 static void taihu_cpld_writew (void *opaque, 448 hwaddr addr, uint32_t value) 449 { 450 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); 451 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); 452 } 453 454 static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr) 455 { 456 uint32_t ret; 457 458 ret = taihu_cpld_readb(opaque, addr) << 24; 459 ret |= taihu_cpld_readb(opaque, addr + 1) << 16; 460 ret |= taihu_cpld_readb(opaque, addr + 2) << 8; 461 ret |= taihu_cpld_readb(opaque, addr + 3); 462 463 return ret; 464 } 465 466 static void taihu_cpld_writel (void *opaque, 467 hwaddr addr, uint32_t value) 468 { 469 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); 470 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); 471 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); 472 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); 473 } 474 475 static const MemoryRegionOps taihu_cpld_ops = { 476 .old_mmio = { 477 .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, 478 .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, 479 }, 480 .endianness = DEVICE_NATIVE_ENDIAN, 481 }; 482 483 static void taihu_cpld_reset (void *opaque) 484 { 485 taihu_cpld_t *cpld; 486 487 cpld = opaque; 488 cpld->reg0 = 0x01; 489 cpld->reg1 = 0x80; 490 } 491 492 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 493 { 494 taihu_cpld_t *cpld; 495 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 496 497 cpld = g_malloc0(sizeof(taihu_cpld_t)); 498 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 499 memory_region_add_subregion(sysmem, base, cpld_memory); 500 qemu_register_reset(&taihu_cpld_reset, cpld); 501 } 502 503 static void taihu_405ep_init(MachineState *machine) 504 { 505 ram_addr_t ram_size = machine->ram_size; 506 const char *kernel_filename = machine->kernel_filename; 507 const char *initrd_filename = machine->initrd_filename; 508 char *filename; 509 qemu_irq *pic; 510 MemoryRegion *sysmem = get_system_memory(); 511 MemoryRegion *bios; 512 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 513 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 514 hwaddr ram_bases[2], ram_sizes[2]; 515 long bios_size; 516 target_ulong kernel_base, initrd_base; 517 long kernel_size, initrd_size; 518 int linux_boot; 519 int fl_idx, fl_sectors; 520 DriveInfo *dinfo; 521 522 /* RAM is soldered to the board so the size cannot be changed */ 523 ram_size = 0x08000000; 524 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 525 ram_size); 526 527 ram_bases[0] = 0; 528 ram_sizes[0] = 0x04000000; 529 memory_region_init_alias(&ram_memories[0], NULL, 530 "taihu_405ep.ram-0", ram, ram_bases[0], 531 ram_sizes[0]); 532 ram_bases[1] = 0x04000000; 533 ram_sizes[1] = 0x04000000; 534 memory_region_init_alias(&ram_memories[1], NULL, 535 "taihu_405ep.ram-1", ram, ram_bases[1], 536 ram_sizes[1]); 537 #ifdef DEBUG_BOARD_INIT 538 printf("%s: register cpu\n", __func__); 539 #endif 540 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 541 33333333, &pic, kernel_filename == NULL ? 0 : 1); 542 /* allocate and load BIOS */ 543 #ifdef DEBUG_BOARD_INIT 544 printf("%s: register BIOS\n", __func__); 545 #endif 546 fl_idx = 0; 547 #if defined(USE_FLASH_BIOS) 548 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 549 if (dinfo) { 550 bios_size = bdrv_getlength(dinfo->bdrv); 551 /* XXX: should check that size is 2MB */ 552 // bios_size = 2 * 1024 * 1024; 553 fl_sectors = (bios_size + 65535) >> 16; 554 #ifdef DEBUG_BOARD_INIT 555 printf("Register parallel flash %d size %lx" 556 " at addr %lx '%s' %d\n", 557 fl_idx, bios_size, -bios_size, 558 bdrv_get_device_name(dinfo->bdrv), fl_sectors); 559 #endif 560 pflash_cfi02_register((uint32_t)(-bios_size), 561 NULL, "taihu_405ep.bios", bios_size, 562 dinfo->bdrv, 65536, fl_sectors, 1, 563 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 564 1); 565 fl_idx++; 566 } else 567 #endif 568 { 569 #ifdef DEBUG_BOARD_INIT 570 printf("Load BIOS from file\n"); 571 #endif 572 if (bios_name == NULL) 573 bios_name = BIOS_FILENAME; 574 bios = g_new(MemoryRegion, 1); 575 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE); 576 vmstate_register_ram_global(bios); 577 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 578 if (filename) { 579 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 580 g_free(filename); 581 if (bios_size < 0 || bios_size > BIOS_SIZE) { 582 error_report("Could not load PowerPC BIOS '%s'", bios_name); 583 exit(1); 584 } 585 bios_size = (bios_size + 0xfff) & ~0xfff; 586 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 587 } else if (!qtest_enabled()) { 588 error_report("Could not load PowerPC BIOS '%s'", bios_name); 589 exit(1); 590 } 591 memory_region_set_readonly(bios, true); 592 } 593 /* Register Linux flash */ 594 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 595 if (dinfo) { 596 bios_size = bdrv_getlength(dinfo->bdrv); 597 /* XXX: should check that size is 32MB */ 598 bios_size = 32 * 1024 * 1024; 599 fl_sectors = (bios_size + 65535) >> 16; 600 #ifdef DEBUG_BOARD_INIT 601 printf("Register parallel flash %d size %lx" 602 " at addr " TARGET_FMT_lx " '%s'\n", 603 fl_idx, bios_size, (target_ulong)0xfc000000, 604 bdrv_get_device_name(dinfo->bdrv)); 605 #endif 606 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 607 dinfo->bdrv, 65536, fl_sectors, 1, 608 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 609 1); 610 fl_idx++; 611 } 612 /* Register CLPD & LCD display */ 613 #ifdef DEBUG_BOARD_INIT 614 printf("%s: register CPLD\n", __func__); 615 #endif 616 taihu_cpld_init(sysmem, 0x50100000); 617 /* Load kernel */ 618 linux_boot = (kernel_filename != NULL); 619 if (linux_boot) { 620 #ifdef DEBUG_BOARD_INIT 621 printf("%s: load kernel\n", __func__); 622 #endif 623 kernel_base = KERNEL_LOAD_ADDR; 624 /* now we can load the kernel */ 625 kernel_size = load_image_targphys(kernel_filename, kernel_base, 626 ram_size - kernel_base); 627 if (kernel_size < 0) { 628 fprintf(stderr, "qemu: could not load kernel '%s'\n", 629 kernel_filename); 630 exit(1); 631 } 632 /* load initrd */ 633 if (initrd_filename) { 634 initrd_base = INITRD_LOAD_ADDR; 635 initrd_size = load_image_targphys(initrd_filename, initrd_base, 636 ram_size - initrd_base); 637 if (initrd_size < 0) { 638 fprintf(stderr, 639 "qemu: could not load initial ram disk '%s'\n", 640 initrd_filename); 641 exit(1); 642 } 643 } else { 644 initrd_base = 0; 645 initrd_size = 0; 646 } 647 } else { 648 kernel_base = 0; 649 kernel_size = 0; 650 initrd_base = 0; 651 initrd_size = 0; 652 } 653 #ifdef DEBUG_BOARD_INIT 654 printf("%s: Done\n", __func__); 655 #endif 656 } 657 658 static QEMUMachine taihu_machine = { 659 .name = "taihu", 660 .desc = "taihu", 661 .init = taihu_405ep_init, 662 }; 663 664 static void ppc405_machine_init(void) 665 { 666 qemu_register_machine(&ref405ep_machine); 667 qemu_register_machine(&taihu_machine); 668 } 669 670 machine_init(ppc405_machine_init); 671