1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "hw/irq.h" 33 #include "ppc405.h" 34 #include "hw/char/serial.h" 35 #include "qemu/timer.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/sysemu.h" 38 #include "exec/address-spaces.h" 39 #include "hw/intc/ppc-uic.h" 40 #include "hw/qdev-properties.h" 41 #include "qapi/error.h" 42 #include "trace.h" 43 44 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 45 uint32_t flags) 46 { 47 CPUState *cs = env_cpu(env); 48 ram_addr_t bdloc; 49 int i, n; 50 51 /* We put the bd structure at the top of memory */ 52 if (bd->bi_memsize >= 0x01000000UL) 53 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 54 else 55 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 56 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 57 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 58 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 59 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 60 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 61 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 62 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 63 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 64 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 65 for (i = 0; i < 6; i++) { 66 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 67 } 68 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 69 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 70 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 71 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 72 for (i = 0; i < 4; i++) { 73 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 74 } 75 for (i = 0; i < 32; i++) { 76 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 77 } 78 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 79 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 80 for (i = 0; i < 6; i++) { 81 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 82 } 83 n = 0x6A; 84 if (flags & 0x00000001) { 85 for (i = 0; i < 6; i++) 86 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 87 } 88 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 89 n += 4; 90 for (i = 0; i < 2; i++) { 91 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 92 n += 4; 93 } 94 95 return bdloc; 96 } 97 98 /*****************************************************************************/ 99 /* Shared peripherals */ 100 101 /*****************************************************************************/ 102 /* Peripheral local bus arbitrer */ 103 enum { 104 PLB3A0_ACR = 0x077, 105 PLB4A0_ACR = 0x081, 106 PLB0_BESR = 0x084, 107 PLB0_BEAR = 0x086, 108 PLB0_ACR = 0x087, 109 PLB4A1_ACR = 0x089, 110 }; 111 112 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 113 struct ppc4xx_plb_t { 114 uint32_t acr; 115 uint32_t bear; 116 uint32_t besr; 117 }; 118 119 static uint32_t dcr_read_plb (void *opaque, int dcrn) 120 { 121 ppc4xx_plb_t *plb; 122 uint32_t ret; 123 124 plb = opaque; 125 switch (dcrn) { 126 case PLB0_ACR: 127 ret = plb->acr; 128 break; 129 case PLB0_BEAR: 130 ret = plb->bear; 131 break; 132 case PLB0_BESR: 133 ret = plb->besr; 134 break; 135 default: 136 /* Avoid gcc warning */ 137 ret = 0; 138 break; 139 } 140 141 return ret; 142 } 143 144 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 145 { 146 ppc4xx_plb_t *plb; 147 148 plb = opaque; 149 switch (dcrn) { 150 case PLB0_ACR: 151 /* We don't care about the actual parameters written as 152 * we don't manage any priorities on the bus 153 */ 154 plb->acr = val & 0xF8000000; 155 break; 156 case PLB0_BEAR: 157 /* Read only */ 158 break; 159 case PLB0_BESR: 160 /* Write-clear */ 161 plb->besr &= ~val; 162 break; 163 } 164 } 165 166 static void ppc4xx_plb_reset (void *opaque) 167 { 168 ppc4xx_plb_t *plb; 169 170 plb = opaque; 171 plb->acr = 0x00000000; 172 plb->bear = 0x00000000; 173 plb->besr = 0x00000000; 174 } 175 176 void ppc4xx_plb_init(CPUPPCState *env) 177 { 178 ppc4xx_plb_t *plb; 179 180 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 181 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 182 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 183 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 184 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 185 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 186 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 187 qemu_register_reset(ppc4xx_plb_reset, plb); 188 } 189 190 /*****************************************************************************/ 191 /* PLB to OPB bridge */ 192 enum { 193 POB0_BESR0 = 0x0A0, 194 POB0_BESR1 = 0x0A2, 195 POB0_BEAR = 0x0A4, 196 }; 197 198 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 199 struct ppc4xx_pob_t { 200 uint32_t bear; 201 uint32_t besr0; 202 uint32_t besr1; 203 }; 204 205 static uint32_t dcr_read_pob (void *opaque, int dcrn) 206 { 207 ppc4xx_pob_t *pob; 208 uint32_t ret; 209 210 pob = opaque; 211 switch (dcrn) { 212 case POB0_BEAR: 213 ret = pob->bear; 214 break; 215 case POB0_BESR0: 216 ret = pob->besr0; 217 break; 218 case POB0_BESR1: 219 ret = pob->besr1; 220 break; 221 default: 222 /* Avoid gcc warning */ 223 ret = 0; 224 break; 225 } 226 227 return ret; 228 } 229 230 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 231 { 232 ppc4xx_pob_t *pob; 233 234 pob = opaque; 235 switch (dcrn) { 236 case POB0_BEAR: 237 /* Read only */ 238 break; 239 case POB0_BESR0: 240 /* Write-clear */ 241 pob->besr0 &= ~val; 242 break; 243 case POB0_BESR1: 244 /* Write-clear */ 245 pob->besr1 &= ~val; 246 break; 247 } 248 } 249 250 static void ppc4xx_pob_reset (void *opaque) 251 { 252 ppc4xx_pob_t *pob; 253 254 pob = opaque; 255 /* No error */ 256 pob->bear = 0x00000000; 257 pob->besr0 = 0x0000000; 258 pob->besr1 = 0x0000000; 259 } 260 261 static void ppc4xx_pob_init(CPUPPCState *env) 262 { 263 ppc4xx_pob_t *pob; 264 265 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 266 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 267 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 268 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 269 qemu_register_reset(ppc4xx_pob_reset, pob); 270 } 271 272 /*****************************************************************************/ 273 /* OPB arbitrer */ 274 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 275 struct ppc4xx_opba_t { 276 MemoryRegion io; 277 uint8_t cr; 278 uint8_t pr; 279 }; 280 281 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 282 { 283 ppc4xx_opba_t *opba = opaque; 284 uint32_t ret; 285 286 switch (addr) { 287 case 0x00: 288 ret = opba->cr; 289 break; 290 case 0x01: 291 ret = opba->pr; 292 break; 293 default: 294 ret = 0x00; 295 break; 296 } 297 298 trace_opba_readb(addr, ret); 299 return ret; 300 } 301 302 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 303 unsigned size) 304 { 305 ppc4xx_opba_t *opba = opaque; 306 307 trace_opba_writeb(addr, value); 308 309 switch (addr) { 310 case 0x00: 311 opba->cr = value & 0xF8; 312 break; 313 case 0x01: 314 opba->pr = value & 0xFF; 315 break; 316 default: 317 break; 318 } 319 } 320 static const MemoryRegionOps opba_ops = { 321 .read = opba_readb, 322 .write = opba_writeb, 323 .impl.min_access_size = 1, 324 .impl.max_access_size = 1, 325 .valid.min_access_size = 1, 326 .valid.max_access_size = 4, 327 .endianness = DEVICE_BIG_ENDIAN, 328 }; 329 330 static void ppc4xx_opba_reset (void *opaque) 331 { 332 ppc4xx_opba_t *opba; 333 334 opba = opaque; 335 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 336 opba->pr = 0x11; 337 } 338 339 static void ppc4xx_opba_init(hwaddr base) 340 { 341 ppc4xx_opba_t *opba; 342 343 trace_opba_init(base); 344 345 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 346 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 347 memory_region_add_subregion(get_system_memory(), base, &opba->io); 348 qemu_register_reset(ppc4xx_opba_reset, opba); 349 } 350 351 /*****************************************************************************/ 352 /* Code decompression controller */ 353 /* XXX: TODO */ 354 355 /*****************************************************************************/ 356 /* Peripheral controller */ 357 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 358 struct ppc4xx_ebc_t { 359 uint32_t addr; 360 uint32_t bcr[8]; 361 uint32_t bap[8]; 362 uint32_t bear; 363 uint32_t besr0; 364 uint32_t besr1; 365 uint32_t cfg; 366 }; 367 368 enum { 369 EBC0_CFGADDR = 0x012, 370 EBC0_CFGDATA = 0x013, 371 }; 372 373 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 374 { 375 ppc4xx_ebc_t *ebc; 376 uint32_t ret; 377 378 ebc = opaque; 379 switch (dcrn) { 380 case EBC0_CFGADDR: 381 ret = ebc->addr; 382 break; 383 case EBC0_CFGDATA: 384 switch (ebc->addr) { 385 case 0x00: /* B0CR */ 386 ret = ebc->bcr[0]; 387 break; 388 case 0x01: /* B1CR */ 389 ret = ebc->bcr[1]; 390 break; 391 case 0x02: /* B2CR */ 392 ret = ebc->bcr[2]; 393 break; 394 case 0x03: /* B3CR */ 395 ret = ebc->bcr[3]; 396 break; 397 case 0x04: /* B4CR */ 398 ret = ebc->bcr[4]; 399 break; 400 case 0x05: /* B5CR */ 401 ret = ebc->bcr[5]; 402 break; 403 case 0x06: /* B6CR */ 404 ret = ebc->bcr[6]; 405 break; 406 case 0x07: /* B7CR */ 407 ret = ebc->bcr[7]; 408 break; 409 case 0x10: /* B0AP */ 410 ret = ebc->bap[0]; 411 break; 412 case 0x11: /* B1AP */ 413 ret = ebc->bap[1]; 414 break; 415 case 0x12: /* B2AP */ 416 ret = ebc->bap[2]; 417 break; 418 case 0x13: /* B3AP */ 419 ret = ebc->bap[3]; 420 break; 421 case 0x14: /* B4AP */ 422 ret = ebc->bap[4]; 423 break; 424 case 0x15: /* B5AP */ 425 ret = ebc->bap[5]; 426 break; 427 case 0x16: /* B6AP */ 428 ret = ebc->bap[6]; 429 break; 430 case 0x17: /* B7AP */ 431 ret = ebc->bap[7]; 432 break; 433 case 0x20: /* BEAR */ 434 ret = ebc->bear; 435 break; 436 case 0x21: /* BESR0 */ 437 ret = ebc->besr0; 438 break; 439 case 0x22: /* BESR1 */ 440 ret = ebc->besr1; 441 break; 442 case 0x23: /* CFG */ 443 ret = ebc->cfg; 444 break; 445 default: 446 ret = 0x00000000; 447 break; 448 } 449 break; 450 default: 451 ret = 0x00000000; 452 break; 453 } 454 455 return ret; 456 } 457 458 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 459 { 460 ppc4xx_ebc_t *ebc; 461 462 ebc = opaque; 463 switch (dcrn) { 464 case EBC0_CFGADDR: 465 ebc->addr = val; 466 break; 467 case EBC0_CFGDATA: 468 switch (ebc->addr) { 469 case 0x00: /* B0CR */ 470 break; 471 case 0x01: /* B1CR */ 472 break; 473 case 0x02: /* B2CR */ 474 break; 475 case 0x03: /* B3CR */ 476 break; 477 case 0x04: /* B4CR */ 478 break; 479 case 0x05: /* B5CR */ 480 break; 481 case 0x06: /* B6CR */ 482 break; 483 case 0x07: /* B7CR */ 484 break; 485 case 0x10: /* B0AP */ 486 break; 487 case 0x11: /* B1AP */ 488 break; 489 case 0x12: /* B2AP */ 490 break; 491 case 0x13: /* B3AP */ 492 break; 493 case 0x14: /* B4AP */ 494 break; 495 case 0x15: /* B5AP */ 496 break; 497 case 0x16: /* B6AP */ 498 break; 499 case 0x17: /* B7AP */ 500 break; 501 case 0x20: /* BEAR */ 502 break; 503 case 0x21: /* BESR0 */ 504 break; 505 case 0x22: /* BESR1 */ 506 break; 507 case 0x23: /* CFG */ 508 break; 509 default: 510 break; 511 } 512 break; 513 default: 514 break; 515 } 516 } 517 518 static void ebc_reset (void *opaque) 519 { 520 ppc4xx_ebc_t *ebc; 521 int i; 522 523 ebc = opaque; 524 ebc->addr = 0x00000000; 525 ebc->bap[0] = 0x7F8FFE80; 526 ebc->bcr[0] = 0xFFE28000; 527 for (i = 0; i < 8; i++) { 528 ebc->bap[i] = 0x00000000; 529 ebc->bcr[i] = 0x00000000; 530 } 531 ebc->besr0 = 0x00000000; 532 ebc->besr1 = 0x00000000; 533 ebc->cfg = 0x80400000; 534 } 535 536 void ppc405_ebc_init(CPUPPCState *env) 537 { 538 ppc4xx_ebc_t *ebc; 539 540 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 541 qemu_register_reset(&ebc_reset, ebc); 542 ppc_dcr_register(env, EBC0_CFGADDR, 543 ebc, &dcr_read_ebc, &dcr_write_ebc); 544 ppc_dcr_register(env, EBC0_CFGDATA, 545 ebc, &dcr_read_ebc, &dcr_write_ebc); 546 } 547 548 /*****************************************************************************/ 549 /* DMA controller */ 550 enum { 551 DMA0_CR0 = 0x100, 552 DMA0_CT0 = 0x101, 553 DMA0_DA0 = 0x102, 554 DMA0_SA0 = 0x103, 555 DMA0_SG0 = 0x104, 556 DMA0_CR1 = 0x108, 557 DMA0_CT1 = 0x109, 558 DMA0_DA1 = 0x10A, 559 DMA0_SA1 = 0x10B, 560 DMA0_SG1 = 0x10C, 561 DMA0_CR2 = 0x110, 562 DMA0_CT2 = 0x111, 563 DMA0_DA2 = 0x112, 564 DMA0_SA2 = 0x113, 565 DMA0_SG2 = 0x114, 566 DMA0_CR3 = 0x118, 567 DMA0_CT3 = 0x119, 568 DMA0_DA3 = 0x11A, 569 DMA0_SA3 = 0x11B, 570 DMA0_SG3 = 0x11C, 571 DMA0_SR = 0x120, 572 DMA0_SGC = 0x123, 573 DMA0_SLP = 0x125, 574 DMA0_POL = 0x126, 575 }; 576 577 typedef struct ppc405_dma_t ppc405_dma_t; 578 struct ppc405_dma_t { 579 qemu_irq irqs[4]; 580 uint32_t cr[4]; 581 uint32_t ct[4]; 582 uint32_t da[4]; 583 uint32_t sa[4]; 584 uint32_t sg[4]; 585 uint32_t sr; 586 uint32_t sgc; 587 uint32_t slp; 588 uint32_t pol; 589 }; 590 591 static uint32_t dcr_read_dma (void *opaque, int dcrn) 592 { 593 return 0; 594 } 595 596 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 597 { 598 } 599 600 static void ppc405_dma_reset (void *opaque) 601 { 602 ppc405_dma_t *dma; 603 int i; 604 605 dma = opaque; 606 for (i = 0; i < 4; i++) { 607 dma->cr[i] = 0x00000000; 608 dma->ct[i] = 0x00000000; 609 dma->da[i] = 0x00000000; 610 dma->sa[i] = 0x00000000; 611 dma->sg[i] = 0x00000000; 612 } 613 dma->sr = 0x00000000; 614 dma->sgc = 0x00000000; 615 dma->slp = 0x7C000000; 616 dma->pol = 0x00000000; 617 } 618 619 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 620 { 621 ppc405_dma_t *dma; 622 623 dma = g_malloc0(sizeof(ppc405_dma_t)); 624 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 625 qemu_register_reset(&ppc405_dma_reset, dma); 626 ppc_dcr_register(env, DMA0_CR0, 627 dma, &dcr_read_dma, &dcr_write_dma); 628 ppc_dcr_register(env, DMA0_CT0, 629 dma, &dcr_read_dma, &dcr_write_dma); 630 ppc_dcr_register(env, DMA0_DA0, 631 dma, &dcr_read_dma, &dcr_write_dma); 632 ppc_dcr_register(env, DMA0_SA0, 633 dma, &dcr_read_dma, &dcr_write_dma); 634 ppc_dcr_register(env, DMA0_SG0, 635 dma, &dcr_read_dma, &dcr_write_dma); 636 ppc_dcr_register(env, DMA0_CR1, 637 dma, &dcr_read_dma, &dcr_write_dma); 638 ppc_dcr_register(env, DMA0_CT1, 639 dma, &dcr_read_dma, &dcr_write_dma); 640 ppc_dcr_register(env, DMA0_DA1, 641 dma, &dcr_read_dma, &dcr_write_dma); 642 ppc_dcr_register(env, DMA0_SA1, 643 dma, &dcr_read_dma, &dcr_write_dma); 644 ppc_dcr_register(env, DMA0_SG1, 645 dma, &dcr_read_dma, &dcr_write_dma); 646 ppc_dcr_register(env, DMA0_CR2, 647 dma, &dcr_read_dma, &dcr_write_dma); 648 ppc_dcr_register(env, DMA0_CT2, 649 dma, &dcr_read_dma, &dcr_write_dma); 650 ppc_dcr_register(env, DMA0_DA2, 651 dma, &dcr_read_dma, &dcr_write_dma); 652 ppc_dcr_register(env, DMA0_SA2, 653 dma, &dcr_read_dma, &dcr_write_dma); 654 ppc_dcr_register(env, DMA0_SG2, 655 dma, &dcr_read_dma, &dcr_write_dma); 656 ppc_dcr_register(env, DMA0_CR3, 657 dma, &dcr_read_dma, &dcr_write_dma); 658 ppc_dcr_register(env, DMA0_CT3, 659 dma, &dcr_read_dma, &dcr_write_dma); 660 ppc_dcr_register(env, DMA0_DA3, 661 dma, &dcr_read_dma, &dcr_write_dma); 662 ppc_dcr_register(env, DMA0_SA3, 663 dma, &dcr_read_dma, &dcr_write_dma); 664 ppc_dcr_register(env, DMA0_SG3, 665 dma, &dcr_read_dma, &dcr_write_dma); 666 ppc_dcr_register(env, DMA0_SR, 667 dma, &dcr_read_dma, &dcr_write_dma); 668 ppc_dcr_register(env, DMA0_SGC, 669 dma, &dcr_read_dma, &dcr_write_dma); 670 ppc_dcr_register(env, DMA0_SLP, 671 dma, &dcr_read_dma, &dcr_write_dma); 672 ppc_dcr_register(env, DMA0_POL, 673 dma, &dcr_read_dma, &dcr_write_dma); 674 } 675 676 /*****************************************************************************/ 677 /* GPIO */ 678 typedef struct ppc405_gpio_t ppc405_gpio_t; 679 struct ppc405_gpio_t { 680 MemoryRegion io; 681 uint32_t or; 682 uint32_t tcr; 683 uint32_t osrh; 684 uint32_t osrl; 685 uint32_t tsrh; 686 uint32_t tsrl; 687 uint32_t odr; 688 uint32_t ir; 689 uint32_t rr1; 690 uint32_t isr1h; 691 uint32_t isr1l; 692 }; 693 694 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 695 { 696 trace_ppc405_gpio_read(addr, size); 697 return 0; 698 } 699 700 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 701 unsigned size) 702 { 703 trace_ppc405_gpio_write(addr, size, value); 704 } 705 706 static const MemoryRegionOps ppc405_gpio_ops = { 707 .read = ppc405_gpio_read, 708 .write = ppc405_gpio_write, 709 .endianness = DEVICE_NATIVE_ENDIAN, 710 }; 711 712 static void ppc405_gpio_reset (void *opaque) 713 { 714 } 715 716 static void ppc405_gpio_init(hwaddr base) 717 { 718 ppc405_gpio_t *gpio; 719 720 trace_ppc405_gpio_init(base); 721 722 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 723 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 724 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 725 qemu_register_reset(&ppc405_gpio_reset, gpio); 726 } 727 728 /*****************************************************************************/ 729 /* On Chip Memory */ 730 enum { 731 OCM0_ISARC = 0x018, 732 OCM0_ISACNTL = 0x019, 733 OCM0_DSARC = 0x01A, 734 OCM0_DSACNTL = 0x01B, 735 }; 736 737 typedef struct ppc405_ocm_t ppc405_ocm_t; 738 struct ppc405_ocm_t { 739 MemoryRegion ram; 740 MemoryRegion isarc_ram; 741 MemoryRegion dsarc_ram; 742 uint32_t isarc; 743 uint32_t isacntl; 744 uint32_t dsarc; 745 uint32_t dsacntl; 746 }; 747 748 static void ocm_update_mappings (ppc405_ocm_t *ocm, 749 uint32_t isarc, uint32_t isacntl, 750 uint32_t dsarc, uint32_t dsacntl) 751 { 752 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, 753 ocm->isacntl, ocm->dsarc, ocm->dsacntl); 754 755 if (ocm->isarc != isarc || 756 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 757 if (ocm->isacntl & 0x80000000) { 758 /* Unmap previously assigned memory region */ 759 trace_ocm_unmap("ISA", ocm->isarc); 760 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 761 } 762 if (isacntl & 0x80000000) { 763 /* Map new instruction memory region */ 764 trace_ocm_map("ISA", isarc); 765 memory_region_add_subregion(get_system_memory(), isarc, 766 &ocm->isarc_ram); 767 } 768 } 769 if (ocm->dsarc != dsarc || 770 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 771 if (ocm->dsacntl & 0x80000000) { 772 /* Beware not to unmap the region we just mapped */ 773 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 774 /* Unmap previously assigned memory region */ 775 trace_ocm_unmap("DSA", ocm->dsarc); 776 memory_region_del_subregion(get_system_memory(), 777 &ocm->dsarc_ram); 778 } 779 } 780 if (dsacntl & 0x80000000) { 781 /* Beware not to remap the region we just mapped */ 782 if (!(isacntl & 0x80000000) || dsarc != isarc) { 783 /* Map new data memory region */ 784 trace_ocm_map("DSA", dsarc); 785 memory_region_add_subregion(get_system_memory(), dsarc, 786 &ocm->dsarc_ram); 787 } 788 } 789 } 790 } 791 792 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 793 { 794 ppc405_ocm_t *ocm; 795 uint32_t ret; 796 797 ocm = opaque; 798 switch (dcrn) { 799 case OCM0_ISARC: 800 ret = ocm->isarc; 801 break; 802 case OCM0_ISACNTL: 803 ret = ocm->isacntl; 804 break; 805 case OCM0_DSARC: 806 ret = ocm->dsarc; 807 break; 808 case OCM0_DSACNTL: 809 ret = ocm->dsacntl; 810 break; 811 default: 812 ret = 0; 813 break; 814 } 815 816 return ret; 817 } 818 819 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 820 { 821 ppc405_ocm_t *ocm; 822 uint32_t isarc, dsarc, isacntl, dsacntl; 823 824 ocm = opaque; 825 isarc = ocm->isarc; 826 dsarc = ocm->dsarc; 827 isacntl = ocm->isacntl; 828 dsacntl = ocm->dsacntl; 829 switch (dcrn) { 830 case OCM0_ISARC: 831 isarc = val & 0xFC000000; 832 break; 833 case OCM0_ISACNTL: 834 isacntl = val & 0xC0000000; 835 break; 836 case OCM0_DSARC: 837 isarc = val & 0xFC000000; 838 break; 839 case OCM0_DSACNTL: 840 isacntl = val & 0xC0000000; 841 break; 842 } 843 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 844 ocm->isarc = isarc; 845 ocm->dsarc = dsarc; 846 ocm->isacntl = isacntl; 847 ocm->dsacntl = dsacntl; 848 } 849 850 static void ocm_reset (void *opaque) 851 { 852 ppc405_ocm_t *ocm; 853 uint32_t isarc, dsarc, isacntl, dsacntl; 854 855 ocm = opaque; 856 isarc = 0x00000000; 857 isacntl = 0x00000000; 858 dsarc = 0x00000000; 859 dsacntl = 0x00000000; 860 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 861 ocm->isarc = isarc; 862 ocm->dsarc = dsarc; 863 ocm->isacntl = isacntl; 864 ocm->dsacntl = dsacntl; 865 } 866 867 static void ppc405_ocm_init(CPUPPCState *env) 868 { 869 ppc405_ocm_t *ocm; 870 871 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 872 /* XXX: Size is 4096 or 0x04000000 */ 873 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 874 &error_fatal); 875 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 876 &ocm->isarc_ram, 0, 4 * KiB); 877 qemu_register_reset(&ocm_reset, ocm); 878 ppc_dcr_register(env, OCM0_ISARC, 879 ocm, &dcr_read_ocm, &dcr_write_ocm); 880 ppc_dcr_register(env, OCM0_ISACNTL, 881 ocm, &dcr_read_ocm, &dcr_write_ocm); 882 ppc_dcr_register(env, OCM0_DSARC, 883 ocm, &dcr_read_ocm, &dcr_write_ocm); 884 ppc_dcr_register(env, OCM0_DSACNTL, 885 ocm, &dcr_read_ocm, &dcr_write_ocm); 886 } 887 888 /*****************************************************************************/ 889 /* General purpose timers */ 890 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 891 struct ppc4xx_gpt_t { 892 MemoryRegion iomem; 893 int64_t tb_offset; 894 uint32_t tb_freq; 895 QEMUTimer *timer; 896 qemu_irq irqs[5]; 897 uint32_t oe; 898 uint32_t ol; 899 uint32_t im; 900 uint32_t is; 901 uint32_t ie; 902 uint32_t comp[5]; 903 uint32_t mask[5]; 904 }; 905 906 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 907 { 908 /* XXX: TODO */ 909 return 0; 910 } 911 912 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 913 { 914 /* XXX: TODO */ 915 } 916 917 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 918 { 919 uint32_t mask; 920 int i; 921 922 mask = 0x80000000; 923 for (i = 0; i < 5; i++) { 924 if (gpt->oe & mask) { 925 /* Output is enabled */ 926 if (ppc4xx_gpt_compare(gpt, i)) { 927 /* Comparison is OK */ 928 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 929 } else { 930 /* Comparison is KO */ 931 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 932 } 933 } 934 mask = mask >> 1; 935 } 936 } 937 938 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 939 { 940 uint32_t mask; 941 int i; 942 943 mask = 0x00008000; 944 for (i = 0; i < 5; i++) { 945 if (gpt->is & gpt->im & mask) 946 qemu_irq_raise(gpt->irqs[i]); 947 else 948 qemu_irq_lower(gpt->irqs[i]); 949 mask = mask >> 1; 950 } 951 } 952 953 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 954 { 955 /* XXX: TODO */ 956 } 957 958 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 959 { 960 ppc4xx_gpt_t *gpt = opaque; 961 uint32_t ret; 962 int idx; 963 964 trace_ppc4xx_gpt_read(addr, size); 965 966 switch (addr) { 967 case 0x00: 968 /* Time base counter */ 969 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 970 gpt->tb_freq, NANOSECONDS_PER_SECOND); 971 break; 972 case 0x10: 973 /* Output enable */ 974 ret = gpt->oe; 975 break; 976 case 0x14: 977 /* Output level */ 978 ret = gpt->ol; 979 break; 980 case 0x18: 981 /* Interrupt mask */ 982 ret = gpt->im; 983 break; 984 case 0x1C: 985 case 0x20: 986 /* Interrupt status */ 987 ret = gpt->is; 988 break; 989 case 0x24: 990 /* Interrupt enable */ 991 ret = gpt->ie; 992 break; 993 case 0x80 ... 0x90: 994 /* Compare timer */ 995 idx = (addr - 0x80) >> 2; 996 ret = gpt->comp[idx]; 997 break; 998 case 0xC0 ... 0xD0: 999 /* Compare mask */ 1000 idx = (addr - 0xC0) >> 2; 1001 ret = gpt->mask[idx]; 1002 break; 1003 default: 1004 ret = -1; 1005 break; 1006 } 1007 1008 return ret; 1009 } 1010 1011 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1012 unsigned size) 1013 { 1014 ppc4xx_gpt_t *gpt = opaque; 1015 int idx; 1016 1017 trace_ppc4xx_gpt_write(addr, size, value); 1018 1019 switch (addr) { 1020 case 0x00: 1021 /* Time base counter */ 1022 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1023 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1024 ppc4xx_gpt_compute_timer(gpt); 1025 break; 1026 case 0x10: 1027 /* Output enable */ 1028 gpt->oe = value & 0xF8000000; 1029 ppc4xx_gpt_set_outputs(gpt); 1030 break; 1031 case 0x14: 1032 /* Output level */ 1033 gpt->ol = value & 0xF8000000; 1034 ppc4xx_gpt_set_outputs(gpt); 1035 break; 1036 case 0x18: 1037 /* Interrupt mask */ 1038 gpt->im = value & 0x0000F800; 1039 break; 1040 case 0x1C: 1041 /* Interrupt status set */ 1042 gpt->is |= value & 0x0000F800; 1043 ppc4xx_gpt_set_irqs(gpt); 1044 break; 1045 case 0x20: 1046 /* Interrupt status clear */ 1047 gpt->is &= ~(value & 0x0000F800); 1048 ppc4xx_gpt_set_irqs(gpt); 1049 break; 1050 case 0x24: 1051 /* Interrupt enable */ 1052 gpt->ie = value & 0x0000F800; 1053 ppc4xx_gpt_set_irqs(gpt); 1054 break; 1055 case 0x80 ... 0x90: 1056 /* Compare timer */ 1057 idx = (addr - 0x80) >> 2; 1058 gpt->comp[idx] = value & 0xF8000000; 1059 ppc4xx_gpt_compute_timer(gpt); 1060 break; 1061 case 0xC0 ... 0xD0: 1062 /* Compare mask */ 1063 idx = (addr - 0xC0) >> 2; 1064 gpt->mask[idx] = value & 0xF8000000; 1065 ppc4xx_gpt_compute_timer(gpt); 1066 break; 1067 } 1068 } 1069 1070 static const MemoryRegionOps gpt_ops = { 1071 .read = ppc4xx_gpt_read, 1072 .write = ppc4xx_gpt_write, 1073 .valid.min_access_size = 4, 1074 .valid.max_access_size = 4, 1075 .endianness = DEVICE_NATIVE_ENDIAN, 1076 }; 1077 1078 static void ppc4xx_gpt_cb (void *opaque) 1079 { 1080 ppc4xx_gpt_t *gpt; 1081 1082 gpt = opaque; 1083 ppc4xx_gpt_set_irqs(gpt); 1084 ppc4xx_gpt_set_outputs(gpt); 1085 ppc4xx_gpt_compute_timer(gpt); 1086 } 1087 1088 static void ppc4xx_gpt_reset (void *opaque) 1089 { 1090 ppc4xx_gpt_t *gpt; 1091 int i; 1092 1093 gpt = opaque; 1094 timer_del(gpt->timer); 1095 gpt->oe = 0x00000000; 1096 gpt->ol = 0x00000000; 1097 gpt->im = 0x00000000; 1098 gpt->is = 0x00000000; 1099 gpt->ie = 0x00000000; 1100 for (i = 0; i < 5; i++) { 1101 gpt->comp[i] = 0x00000000; 1102 gpt->mask[i] = 0x00000000; 1103 } 1104 } 1105 1106 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1107 { 1108 ppc4xx_gpt_t *gpt; 1109 int i; 1110 1111 trace_ppc4xx_gpt_init(base); 1112 1113 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1114 for (i = 0; i < 5; i++) { 1115 gpt->irqs[i] = irqs[i]; 1116 } 1117 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1118 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1119 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1120 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1121 } 1122 1123 /*****************************************************************************/ 1124 /* PowerPC 405EP */ 1125 /* CPU control */ 1126 enum { 1127 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1128 PPC405EP_CPC0_BOOT = 0x0F1, 1129 PPC405EP_CPC0_EPCTL = 0x0F3, 1130 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1131 PPC405EP_CPC0_UCR = 0x0F5, 1132 PPC405EP_CPC0_SRR = 0x0F6, 1133 PPC405EP_CPC0_JTAGID = 0x0F7, 1134 PPC405EP_CPC0_PCI = 0x0F9, 1135 #if 0 1136 PPC405EP_CPC0_ER = xxx, 1137 PPC405EP_CPC0_FR = xxx, 1138 PPC405EP_CPC0_SR = xxx, 1139 #endif 1140 }; 1141 1142 enum { 1143 PPC405EP_CPU_CLK = 0, 1144 PPC405EP_PLB_CLK = 1, 1145 PPC405EP_OPB_CLK = 2, 1146 PPC405EP_EBC_CLK = 3, 1147 PPC405EP_MAL_CLK = 4, 1148 PPC405EP_PCI_CLK = 5, 1149 PPC405EP_UART0_CLK = 6, 1150 PPC405EP_UART1_CLK = 7, 1151 PPC405EP_CLK_NB = 8, 1152 }; 1153 1154 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1155 struct ppc405ep_cpc_t { 1156 uint32_t sysclk; 1157 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1158 uint32_t boot; 1159 uint32_t epctl; 1160 uint32_t pllmr[2]; 1161 uint32_t ucr; 1162 uint32_t srr; 1163 uint32_t jtagid; 1164 uint32_t pci; 1165 /* Clock and power management */ 1166 uint32_t er; 1167 uint32_t fr; 1168 uint32_t sr; 1169 }; 1170 1171 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1172 { 1173 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1174 uint32_t UART0_clk, UART1_clk; 1175 uint64_t VCO_out, PLL_out; 1176 int M, D; 1177 1178 VCO_out = 0; 1179 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1180 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1181 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); 1182 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1183 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); 1184 VCO_out = (uint64_t)cpc->sysclk * M * D; 1185 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1186 /* Error - unlock the PLL */ 1187 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", 1188 VCO_out); 1189 #if 0 1190 cpc->pllmr[1] &= ~0x80000000; 1191 goto pll_bypass; 1192 #endif 1193 } 1194 PLL_out = VCO_out / D; 1195 /* Pretend the PLL is locked */ 1196 cpc->boot |= 0x00000001; 1197 } else { 1198 #if 0 1199 pll_bypass: 1200 #endif 1201 PLL_out = cpc->sysclk; 1202 if (cpc->pllmr[1] & 0x40000000) { 1203 /* Pretend the PLL is not locked */ 1204 cpc->boot &= ~0x00000001; 1205 } 1206 } 1207 /* Now, compute all other clocks */ 1208 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1209 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); 1210 CPU_clk = PLL_out / D; 1211 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1212 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); 1213 PLB_clk = CPU_clk / D; 1214 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1215 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); 1216 OPB_clk = PLB_clk / D; 1217 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1218 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); 1219 EBC_clk = PLB_clk / D; 1220 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1221 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); 1222 MAL_clk = PLB_clk / D; 1223 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1224 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); 1225 PCI_clk = PLB_clk / D; 1226 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1227 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); 1228 UART0_clk = PLL_out / D; 1229 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1230 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); 1231 UART1_clk = PLL_out / D; 1232 1233 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { 1234 g_autofree char *trace = g_strdup_printf( 1235 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1236 " PLL out %" PRIu64 " Hz\n" 1237 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1238 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1239 " UART1 %" PRIu32 "\n", 1240 cpc->sysclk, VCO_out, PLL_out, 1241 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1242 UART0_clk, UART1_clk); 1243 trace_ppc405ep_clocks_setup(trace); 1244 } 1245 1246 /* Setup CPU clocks */ 1247 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1248 /* Setup PLB clock */ 1249 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1250 /* Setup OPB clock */ 1251 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1252 /* Setup external clock */ 1253 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1254 /* Setup MAL clock */ 1255 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1256 /* Setup PCI clock */ 1257 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1258 /* Setup UART0 clock */ 1259 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1260 /* Setup UART1 clock */ 1261 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1262 } 1263 1264 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1265 { 1266 ppc405ep_cpc_t *cpc; 1267 uint32_t ret; 1268 1269 cpc = opaque; 1270 switch (dcrn) { 1271 case PPC405EP_CPC0_BOOT: 1272 ret = cpc->boot; 1273 break; 1274 case PPC405EP_CPC0_EPCTL: 1275 ret = cpc->epctl; 1276 break; 1277 case PPC405EP_CPC0_PLLMR0: 1278 ret = cpc->pllmr[0]; 1279 break; 1280 case PPC405EP_CPC0_PLLMR1: 1281 ret = cpc->pllmr[1]; 1282 break; 1283 case PPC405EP_CPC0_UCR: 1284 ret = cpc->ucr; 1285 break; 1286 case PPC405EP_CPC0_SRR: 1287 ret = cpc->srr; 1288 break; 1289 case PPC405EP_CPC0_JTAGID: 1290 ret = cpc->jtagid; 1291 break; 1292 case PPC405EP_CPC0_PCI: 1293 ret = cpc->pci; 1294 break; 1295 default: 1296 /* Avoid gcc warning */ 1297 ret = 0; 1298 break; 1299 } 1300 1301 return ret; 1302 } 1303 1304 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1305 { 1306 ppc405ep_cpc_t *cpc; 1307 1308 cpc = opaque; 1309 switch (dcrn) { 1310 case PPC405EP_CPC0_BOOT: 1311 /* Read-only register */ 1312 break; 1313 case PPC405EP_CPC0_EPCTL: 1314 /* Don't care for now */ 1315 cpc->epctl = val & 0xC00000F3; 1316 break; 1317 case PPC405EP_CPC0_PLLMR0: 1318 cpc->pllmr[0] = val & 0x00633333; 1319 ppc405ep_compute_clocks(cpc); 1320 break; 1321 case PPC405EP_CPC0_PLLMR1: 1322 cpc->pllmr[1] = val & 0xC0F73FFF; 1323 ppc405ep_compute_clocks(cpc); 1324 break; 1325 case PPC405EP_CPC0_UCR: 1326 /* UART control - don't care for now */ 1327 cpc->ucr = val & 0x003F7F7F; 1328 break; 1329 case PPC405EP_CPC0_SRR: 1330 cpc->srr = val; 1331 break; 1332 case PPC405EP_CPC0_JTAGID: 1333 /* Read-only */ 1334 break; 1335 case PPC405EP_CPC0_PCI: 1336 cpc->pci = val; 1337 break; 1338 } 1339 } 1340 1341 static void ppc405ep_cpc_reset (void *opaque) 1342 { 1343 ppc405ep_cpc_t *cpc = opaque; 1344 1345 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1346 cpc->epctl = 0x00000000; 1347 cpc->pllmr[0] = 0x00011010; 1348 cpc->pllmr[1] = 0x40000000; 1349 cpc->ucr = 0x00000000; 1350 cpc->srr = 0x00040000; 1351 cpc->pci = 0x00000000; 1352 cpc->er = 0x00000000; 1353 cpc->fr = 0x00000000; 1354 cpc->sr = 0x00000000; 1355 ppc405ep_compute_clocks(cpc); 1356 } 1357 1358 /* XXX: sysclk should be between 25 and 100 MHz */ 1359 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1360 uint32_t sysclk) 1361 { 1362 ppc405ep_cpc_t *cpc; 1363 1364 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1365 memcpy(cpc->clk_setup, clk_setup, 1366 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1367 cpc->jtagid = 0x20267049; 1368 cpc->sysclk = sysclk; 1369 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1370 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1371 &dcr_read_epcpc, &dcr_write_epcpc); 1372 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1373 &dcr_read_epcpc, &dcr_write_epcpc); 1374 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1375 &dcr_read_epcpc, &dcr_write_epcpc); 1376 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1377 &dcr_read_epcpc, &dcr_write_epcpc); 1378 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1379 &dcr_read_epcpc, &dcr_write_epcpc); 1380 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1381 &dcr_read_epcpc, &dcr_write_epcpc); 1382 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1383 &dcr_read_epcpc, &dcr_write_epcpc); 1384 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1385 &dcr_read_epcpc, &dcr_write_epcpc); 1386 #if 0 1387 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1388 &dcr_read_epcpc, &dcr_write_epcpc); 1389 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1390 &dcr_read_epcpc, &dcr_write_epcpc); 1391 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1392 &dcr_read_epcpc, &dcr_write_epcpc); 1393 #endif 1394 } 1395 1396 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1397 MemoryRegion ram_memories[2], 1398 hwaddr ram_bases[2], 1399 hwaddr ram_sizes[2], 1400 uint32_t sysclk, DeviceState **uicdevp, 1401 int do_init) 1402 { 1403 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1404 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1405 PowerPCCPU *cpu; 1406 CPUPPCState *env; 1407 DeviceState *uicdev; 1408 SysBusDevice *uicsbd; 1409 1410 memset(clk_setup, 0, sizeof(clk_setup)); 1411 /* init CPUs */ 1412 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1413 &clk_setup[PPC405EP_CPU_CLK], 1414 &tlb_clk_setup, sysclk); 1415 env = &cpu->env; 1416 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1417 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1418 /* Internal devices init */ 1419 /* Memory mapped devices registers */ 1420 /* PLB arbitrer */ 1421 ppc4xx_plb_init(env); 1422 /* PLB to OPB bridge */ 1423 ppc4xx_pob_init(env); 1424 /* OBP arbitrer */ 1425 ppc4xx_opba_init(0xef600600); 1426 /* Initialize timers */ 1427 ppc_booke_timers_init(cpu, sysclk, 0); 1428 /* Universal interrupt controller */ 1429 uicdev = qdev_new(TYPE_PPC_UIC); 1430 uicsbd = SYS_BUS_DEVICE(uicdev); 1431 1432 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 1433 &error_fatal); 1434 sysbus_realize_and_unref(uicsbd, &error_fatal); 1435 1436 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 1437 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 1438 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 1439 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 1440 1441 *uicdevp = uicdev; 1442 1443 /* SDRAM controller */ 1444 /* XXX 405EP has no ECC interrupt */ 1445 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, 1446 ram_bases, ram_sizes, do_init); 1447 /* External bus controller */ 1448 ppc405_ebc_init(env); 1449 /* DMA controller */ 1450 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); 1451 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); 1452 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); 1453 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); 1454 ppc405_dma_init(env, dma_irqs); 1455 /* IIC controller */ 1456 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1457 qdev_get_gpio_in(uicdev, 2)); 1458 /* GPIO */ 1459 ppc405_gpio_init(0xef600700); 1460 /* Serial ports */ 1461 if (serial_hd(0) != NULL) { 1462 serial_mm_init(address_space_mem, 0xef600300, 0, 1463 qdev_get_gpio_in(uicdev, 0), 1464 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1465 DEVICE_BIG_ENDIAN); 1466 } 1467 if (serial_hd(1) != NULL) { 1468 serial_mm_init(address_space_mem, 0xef600400, 0, 1469 qdev_get_gpio_in(uicdev, 1), 1470 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1471 DEVICE_BIG_ENDIAN); 1472 } 1473 /* OCM */ 1474 ppc405_ocm_init(env); 1475 /* GPT */ 1476 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); 1477 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); 1478 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); 1479 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); 1480 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); 1481 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1482 /* PCI */ 1483 /* Uses UIC IRQs 3, 16, 18 */ 1484 /* MAL */ 1485 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); 1486 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); 1487 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); 1488 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); 1489 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1490 /* Ethernet */ 1491 /* Uses UIC IRQs 9, 15, 17 */ 1492 /* CPU control */ 1493 ppc405ep_cpc_init(env, clk_setup, sysclk); 1494 1495 return env; 1496 } 1497