1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "ppc405.h" 35 #include "hw/char/serial.h" 36 #include "qemu/timer.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/address-spaces.h" 40 #include "hw/intc/ppc-uic.h" 41 #include "hw/qdev-properties.h" 42 #include "qapi/error.h" 43 #include "trace.h" 44 45 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, 46 ram_addr_t ram_size) 47 { 48 memset(bd, 0, sizeof(*bd)); 49 50 bd->bi_memstart = PPC405EP_SDRAM_BASE; 51 bd->bi_memsize = ram_size; 52 bd->bi_sramstart = PPC405EP_SRAM_BASE; 53 bd->bi_sramsize = PPC405EP_SRAM_SIZE; 54 bd->bi_bootflags = 0; 55 bd->bi_intfreq = 133333333; 56 bd->bi_busfreq = 33333333; 57 bd->bi_baudrate = 115200; 58 bd->bi_s_version[0] = 'Q'; 59 bd->bi_s_version[1] = 'M'; 60 bd->bi_s_version[2] = 'U'; 61 bd->bi_s_version[3] = '\0'; 62 bd->bi_r_version[0] = 'Q'; 63 bd->bi_r_version[1] = 'E'; 64 bd->bi_r_version[2] = 'M'; 65 bd->bi_r_version[3] = 'U'; 66 bd->bi_r_version[4] = '\0'; 67 bd->bi_procfreq = 133333333; 68 bd->bi_plb_busfreq = 33333333; 69 bd->bi_pci_busfreq = 33333333; 70 bd->bi_opbfreq = 33333333; 71 } 72 73 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) 74 { 75 CPUState *cs = env_cpu(env); 76 ram_addr_t bdloc; 77 int i, n; 78 79 /* We put the bd structure at the top of memory */ 80 if (bd->bi_memsize >= 0x01000000UL) 81 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 82 else 83 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 84 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 85 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 86 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 87 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 88 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 89 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 90 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 91 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 92 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 93 for (i = 0; i < 6; i++) { 94 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 95 } 96 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 97 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 98 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 99 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 100 for (i = 0; i < 4; i++) { 101 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 102 } 103 for (i = 0; i < 32; i++) { 104 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 105 } 106 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); 107 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); 108 stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); 109 for (i = 0; i < 6; i++) { 110 stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); 111 } 112 n = 0x70; /* includes 2 bytes hole */ 113 for (i = 0; i < 6; i++) { 114 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 115 } 116 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 117 n += 4; 118 for (i = 0; i < 2; i++) { 119 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 120 n += 4; 121 } 122 123 return bdloc; 124 } 125 126 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) 127 { 128 ppc4xx_bd_info_t bd; 129 130 memset(&bd, 0, sizeof(bd)); 131 132 ppc405_set_default_bootinfo(&bd, ram_size); 133 134 return __ppc405_set_bootinfo(env, &bd); 135 } 136 137 /*****************************************************************************/ 138 /* Shared peripherals */ 139 140 /*****************************************************************************/ 141 /* Peripheral local bus arbitrer */ 142 enum { 143 PLB3A0_ACR = 0x077, 144 PLB4A0_ACR = 0x081, 145 PLB0_BESR = 0x084, 146 PLB0_BEAR = 0x086, 147 PLB0_ACR = 0x087, 148 PLB4A1_ACR = 0x089, 149 }; 150 151 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 152 struct ppc4xx_plb_t { 153 uint32_t acr; 154 uint32_t bear; 155 uint32_t besr; 156 }; 157 158 static uint32_t dcr_read_plb (void *opaque, int dcrn) 159 { 160 ppc4xx_plb_t *plb; 161 uint32_t ret; 162 163 plb = opaque; 164 switch (dcrn) { 165 case PLB0_ACR: 166 ret = plb->acr; 167 break; 168 case PLB0_BEAR: 169 ret = plb->bear; 170 break; 171 case PLB0_BESR: 172 ret = plb->besr; 173 break; 174 default: 175 /* Avoid gcc warning */ 176 ret = 0; 177 break; 178 } 179 180 return ret; 181 } 182 183 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 184 { 185 ppc4xx_plb_t *plb; 186 187 plb = opaque; 188 switch (dcrn) { 189 case PLB0_ACR: 190 /* We don't care about the actual parameters written as 191 * we don't manage any priorities on the bus 192 */ 193 plb->acr = val & 0xF8000000; 194 break; 195 case PLB0_BEAR: 196 /* Read only */ 197 break; 198 case PLB0_BESR: 199 /* Write-clear */ 200 plb->besr &= ~val; 201 break; 202 } 203 } 204 205 static void ppc4xx_plb_reset (void *opaque) 206 { 207 ppc4xx_plb_t *plb; 208 209 plb = opaque; 210 plb->acr = 0x00000000; 211 plb->bear = 0x00000000; 212 plb->besr = 0x00000000; 213 } 214 215 void ppc4xx_plb_init(CPUPPCState *env) 216 { 217 ppc4xx_plb_t *plb; 218 219 plb = g_new0(ppc4xx_plb_t, 1); 220 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 221 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 222 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 223 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 224 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 225 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 226 qemu_register_reset(ppc4xx_plb_reset, plb); 227 } 228 229 /*****************************************************************************/ 230 /* PLB to OPB bridge */ 231 enum { 232 POB0_BESR0 = 0x0A0, 233 POB0_BESR1 = 0x0A2, 234 POB0_BEAR = 0x0A4, 235 }; 236 237 static uint32_t dcr_read_pob(void *opaque, int dcrn) 238 { 239 Ppc405PobState *pob = opaque; 240 uint32_t ret; 241 242 switch (dcrn) { 243 case POB0_BEAR: 244 ret = pob->bear; 245 break; 246 case POB0_BESR0: 247 ret = pob->besr0; 248 break; 249 case POB0_BESR1: 250 ret = pob->besr1; 251 break; 252 default: 253 /* Avoid gcc warning */ 254 ret = 0; 255 break; 256 } 257 258 return ret; 259 } 260 261 static void dcr_write_pob(void *opaque, int dcrn, uint32_t val) 262 { 263 Ppc405PobState *pob = opaque; 264 265 switch (dcrn) { 266 case POB0_BEAR: 267 /* Read only */ 268 break; 269 case POB0_BESR0: 270 /* Write-clear */ 271 pob->besr0 &= ~val; 272 break; 273 case POB0_BESR1: 274 /* Write-clear */ 275 pob->besr1 &= ~val; 276 break; 277 } 278 } 279 280 static void ppc405_pob_reset(DeviceState *dev) 281 { 282 Ppc405PobState *pob = PPC405_POB(dev); 283 284 /* No error */ 285 pob->bear = 0x00000000; 286 pob->besr0 = 0x0000000; 287 pob->besr1 = 0x0000000; 288 } 289 290 static void ppc405_pob_realize(DeviceState *dev, Error **errp) 291 { 292 Ppc405PobState *pob = PPC405_POB(dev); 293 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 294 295 ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 296 ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 297 ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 298 } 299 300 static void ppc405_pob_class_init(ObjectClass *oc, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(oc); 303 304 dc->realize = ppc405_pob_realize; 305 dc->reset = ppc405_pob_reset; 306 /* Reason: only works as function of a ppc4xx SoC */ 307 dc->user_creatable = false; 308 } 309 310 /*****************************************************************************/ 311 /* OPB arbitrer */ 312 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 313 { 314 Ppc405OpbaState *opba = opaque; 315 uint32_t ret; 316 317 switch (addr) { 318 case 0x00: 319 ret = opba->cr; 320 break; 321 case 0x01: 322 ret = opba->pr; 323 break; 324 default: 325 ret = 0x00; 326 break; 327 } 328 329 trace_opba_readb(addr, ret); 330 return ret; 331 } 332 333 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 334 unsigned size) 335 { 336 Ppc405OpbaState *opba = opaque; 337 338 trace_opba_writeb(addr, value); 339 340 switch (addr) { 341 case 0x00: 342 opba->cr = value & 0xF8; 343 break; 344 case 0x01: 345 opba->pr = value & 0xFF; 346 break; 347 default: 348 break; 349 } 350 } 351 static const MemoryRegionOps opba_ops = { 352 .read = opba_readb, 353 .write = opba_writeb, 354 .impl.min_access_size = 1, 355 .impl.max_access_size = 1, 356 .valid.min_access_size = 1, 357 .valid.max_access_size = 4, 358 .endianness = DEVICE_BIG_ENDIAN, 359 }; 360 361 static void ppc405_opba_reset(DeviceState *dev) 362 { 363 Ppc405OpbaState *opba = PPC405_OPBA(dev); 364 365 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 366 opba->pr = 0x11; 367 } 368 369 static void ppc405_opba_realize(DeviceState *dev, Error **errp) 370 { 371 Ppc405OpbaState *s = PPC405_OPBA(dev); 372 373 memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2); 374 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); 375 } 376 377 static void ppc405_opba_class_init(ObjectClass *oc, void *data) 378 { 379 DeviceClass *dc = DEVICE_CLASS(oc); 380 381 dc->realize = ppc405_opba_realize; 382 dc->reset = ppc405_opba_reset; 383 /* Reason: only works as function of a ppc4xx SoC */ 384 dc->user_creatable = false; 385 } 386 387 /*****************************************************************************/ 388 /* Code decompression controller */ 389 /* XXX: TODO */ 390 391 /*****************************************************************************/ 392 /* Peripheral controller */ 393 enum { 394 EBC0_CFGADDR = 0x012, 395 EBC0_CFGDATA = 0x013, 396 }; 397 398 static uint32_t dcr_read_ebc(void *opaque, int dcrn) 399 { 400 Ppc405EbcState *ebc = opaque; 401 uint32_t ret; 402 403 switch (dcrn) { 404 case EBC0_CFGADDR: 405 ret = ebc->addr; 406 break; 407 case EBC0_CFGDATA: 408 switch (ebc->addr) { 409 case 0x00: /* B0CR */ 410 ret = ebc->bcr[0]; 411 break; 412 case 0x01: /* B1CR */ 413 ret = ebc->bcr[1]; 414 break; 415 case 0x02: /* B2CR */ 416 ret = ebc->bcr[2]; 417 break; 418 case 0x03: /* B3CR */ 419 ret = ebc->bcr[3]; 420 break; 421 case 0x04: /* B4CR */ 422 ret = ebc->bcr[4]; 423 break; 424 case 0x05: /* B5CR */ 425 ret = ebc->bcr[5]; 426 break; 427 case 0x06: /* B6CR */ 428 ret = ebc->bcr[6]; 429 break; 430 case 0x07: /* B7CR */ 431 ret = ebc->bcr[7]; 432 break; 433 case 0x10: /* B0AP */ 434 ret = ebc->bap[0]; 435 break; 436 case 0x11: /* B1AP */ 437 ret = ebc->bap[1]; 438 break; 439 case 0x12: /* B2AP */ 440 ret = ebc->bap[2]; 441 break; 442 case 0x13: /* B3AP */ 443 ret = ebc->bap[3]; 444 break; 445 case 0x14: /* B4AP */ 446 ret = ebc->bap[4]; 447 break; 448 case 0x15: /* B5AP */ 449 ret = ebc->bap[5]; 450 break; 451 case 0x16: /* B6AP */ 452 ret = ebc->bap[6]; 453 break; 454 case 0x17: /* B7AP */ 455 ret = ebc->bap[7]; 456 break; 457 case 0x20: /* BEAR */ 458 ret = ebc->bear; 459 break; 460 case 0x21: /* BESR0 */ 461 ret = ebc->besr0; 462 break; 463 case 0x22: /* BESR1 */ 464 ret = ebc->besr1; 465 break; 466 case 0x23: /* CFG */ 467 ret = ebc->cfg; 468 break; 469 default: 470 ret = 0x00000000; 471 break; 472 } 473 break; 474 default: 475 ret = 0x00000000; 476 break; 477 } 478 479 return ret; 480 } 481 482 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) 483 { 484 Ppc405EbcState *ebc = opaque; 485 486 switch (dcrn) { 487 case EBC0_CFGADDR: 488 ebc->addr = val; 489 break; 490 case EBC0_CFGDATA: 491 switch (ebc->addr) { 492 case 0x00: /* B0CR */ 493 break; 494 case 0x01: /* B1CR */ 495 break; 496 case 0x02: /* B2CR */ 497 break; 498 case 0x03: /* B3CR */ 499 break; 500 case 0x04: /* B4CR */ 501 break; 502 case 0x05: /* B5CR */ 503 break; 504 case 0x06: /* B6CR */ 505 break; 506 case 0x07: /* B7CR */ 507 break; 508 case 0x10: /* B0AP */ 509 break; 510 case 0x11: /* B1AP */ 511 break; 512 case 0x12: /* B2AP */ 513 break; 514 case 0x13: /* B3AP */ 515 break; 516 case 0x14: /* B4AP */ 517 break; 518 case 0x15: /* B5AP */ 519 break; 520 case 0x16: /* B6AP */ 521 break; 522 case 0x17: /* B7AP */ 523 break; 524 case 0x20: /* BEAR */ 525 break; 526 case 0x21: /* BESR0 */ 527 break; 528 case 0x22: /* BESR1 */ 529 break; 530 case 0x23: /* CFG */ 531 break; 532 default: 533 break; 534 } 535 break; 536 default: 537 break; 538 } 539 } 540 541 static void ppc405_ebc_reset(DeviceState *dev) 542 { 543 Ppc405EbcState *ebc = PPC405_EBC(dev); 544 int i; 545 546 ebc->addr = 0x00000000; 547 ebc->bap[0] = 0x7F8FFE80; 548 ebc->bcr[0] = 0xFFE28000; 549 for (i = 0; i < 8; i++) { 550 ebc->bap[i] = 0x00000000; 551 ebc->bcr[i] = 0x00000000; 552 } 553 ebc->besr0 = 0x00000000; 554 ebc->besr1 = 0x00000000; 555 ebc->cfg = 0x80400000; 556 } 557 558 static void ppc405_ebc_realize(DeviceState *dev, Error **errp) 559 { 560 Ppc405EbcState *ebc = PPC405_EBC(dev); 561 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 562 563 ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); 564 ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); 565 } 566 567 static void ppc405_ebc_class_init(ObjectClass *oc, void *data) 568 { 569 DeviceClass *dc = DEVICE_CLASS(oc); 570 571 dc->realize = ppc405_ebc_realize; 572 dc->reset = ppc405_ebc_reset; 573 /* Reason: only works as function of a ppc4xx SoC */ 574 dc->user_creatable = false; 575 } 576 577 /*****************************************************************************/ 578 /* DMA controller */ 579 enum { 580 DMA0_CR0 = 0x100, 581 DMA0_CT0 = 0x101, 582 DMA0_DA0 = 0x102, 583 DMA0_SA0 = 0x103, 584 DMA0_SG0 = 0x104, 585 DMA0_CR1 = 0x108, 586 DMA0_CT1 = 0x109, 587 DMA0_DA1 = 0x10A, 588 DMA0_SA1 = 0x10B, 589 DMA0_SG1 = 0x10C, 590 DMA0_CR2 = 0x110, 591 DMA0_CT2 = 0x111, 592 DMA0_DA2 = 0x112, 593 DMA0_SA2 = 0x113, 594 DMA0_SG2 = 0x114, 595 DMA0_CR3 = 0x118, 596 DMA0_CT3 = 0x119, 597 DMA0_DA3 = 0x11A, 598 DMA0_SA3 = 0x11B, 599 DMA0_SG3 = 0x11C, 600 DMA0_SR = 0x120, 601 DMA0_SGC = 0x123, 602 DMA0_SLP = 0x125, 603 DMA0_POL = 0x126, 604 }; 605 606 static uint32_t dcr_read_dma(void *opaque, int dcrn) 607 { 608 return 0; 609 } 610 611 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 612 { 613 } 614 615 static void ppc405_dma_reset(DeviceState *dev) 616 { 617 Ppc405DmaState *dma = PPC405_DMA(dev); 618 int i; 619 620 for (i = 0; i < 4; i++) { 621 dma->cr[i] = 0x00000000; 622 dma->ct[i] = 0x00000000; 623 dma->da[i] = 0x00000000; 624 dma->sa[i] = 0x00000000; 625 dma->sg[i] = 0x00000000; 626 } 627 dma->sr = 0x00000000; 628 dma->sgc = 0x00000000; 629 dma->slp = 0x7C000000; 630 dma->pol = 0x00000000; 631 } 632 633 static void ppc405_dma_realize(DeviceState *dev, Error **errp) 634 { 635 Ppc405DmaState *dma = PPC405_DMA(dev); 636 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 637 int i; 638 639 for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) { 640 sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); 641 } 642 643 ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); 644 ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma); 645 ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma); 646 ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma); 647 ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma); 648 ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma); 649 ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma); 650 ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma); 651 ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma); 652 ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma); 653 ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma); 654 ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma); 655 ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma); 656 ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma); 657 ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma); 658 ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma); 659 ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma); 660 ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma); 661 ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma); 662 ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma); 663 ppc4xx_dcr_register(dcr, DMA0_SR, dma, &dcr_read_dma, &dcr_write_dma); 664 ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma); 665 ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma); 666 ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma); 667 } 668 669 static void ppc405_dma_class_init(ObjectClass *oc, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(oc); 672 673 dc->realize = ppc405_dma_realize; 674 dc->reset = ppc405_dma_reset; 675 /* Reason: only works as function of a ppc4xx SoC */ 676 dc->user_creatable = false; 677 } 678 679 /*****************************************************************************/ 680 /* GPIO */ 681 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 682 { 683 trace_ppc405_gpio_read(addr, size); 684 return 0; 685 } 686 687 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 688 unsigned size) 689 { 690 trace_ppc405_gpio_write(addr, size, value); 691 } 692 693 static const MemoryRegionOps ppc405_gpio_ops = { 694 .read = ppc405_gpio_read, 695 .write = ppc405_gpio_write, 696 .endianness = DEVICE_NATIVE_ENDIAN, 697 }; 698 699 static void ppc405_gpio_realize(DeviceState *dev, Error **errp) 700 { 701 Ppc405GpioState *s = PPC405_GPIO(dev); 702 703 memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio", 704 0x38); 705 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); 706 } 707 708 static void ppc405_gpio_class_init(ObjectClass *oc, void *data) 709 { 710 DeviceClass *dc = DEVICE_CLASS(oc); 711 712 dc->realize = ppc405_gpio_realize; 713 /* Reason: only works as function of a ppc4xx SoC */ 714 dc->user_creatable = false; 715 } 716 717 /*****************************************************************************/ 718 /* On Chip Memory */ 719 enum { 720 OCM0_ISARC = 0x018, 721 OCM0_ISACNTL = 0x019, 722 OCM0_DSARC = 0x01A, 723 OCM0_DSACNTL = 0x01B, 724 }; 725 726 static void ocm_update_mappings(Ppc405OcmState *ocm, 727 uint32_t isarc, uint32_t isacntl, 728 uint32_t dsarc, uint32_t dsacntl) 729 { 730 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, 731 ocm->isacntl, ocm->dsarc, ocm->dsacntl); 732 733 if (ocm->isarc != isarc || 734 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 735 if (ocm->isacntl & 0x80000000) { 736 /* Unmap previously assigned memory region */ 737 trace_ocm_unmap("ISA", ocm->isarc); 738 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 739 } 740 if (isacntl & 0x80000000) { 741 /* Map new instruction memory region */ 742 trace_ocm_map("ISA", isarc); 743 memory_region_add_subregion(get_system_memory(), isarc, 744 &ocm->isarc_ram); 745 } 746 } 747 if (ocm->dsarc != dsarc || 748 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 749 if (ocm->dsacntl & 0x80000000) { 750 /* Beware not to unmap the region we just mapped */ 751 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 752 /* Unmap previously assigned memory region */ 753 trace_ocm_unmap("DSA", ocm->dsarc); 754 memory_region_del_subregion(get_system_memory(), 755 &ocm->dsarc_ram); 756 } 757 } 758 if (dsacntl & 0x80000000) { 759 /* Beware not to remap the region we just mapped */ 760 if (!(isacntl & 0x80000000) || dsarc != isarc) { 761 /* Map new data memory region */ 762 trace_ocm_map("DSA", dsarc); 763 memory_region_add_subregion(get_system_memory(), dsarc, 764 &ocm->dsarc_ram); 765 } 766 } 767 } 768 } 769 770 static uint32_t dcr_read_ocm(void *opaque, int dcrn) 771 { 772 Ppc405OcmState *ocm = opaque; 773 uint32_t ret; 774 775 switch (dcrn) { 776 case OCM0_ISARC: 777 ret = ocm->isarc; 778 break; 779 case OCM0_ISACNTL: 780 ret = ocm->isacntl; 781 break; 782 case OCM0_DSARC: 783 ret = ocm->dsarc; 784 break; 785 case OCM0_DSACNTL: 786 ret = ocm->dsacntl; 787 break; 788 default: 789 ret = 0; 790 break; 791 } 792 793 return ret; 794 } 795 796 static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val) 797 { 798 Ppc405OcmState *ocm = opaque; 799 uint32_t isarc, dsarc, isacntl, dsacntl; 800 801 isarc = ocm->isarc; 802 dsarc = ocm->dsarc; 803 isacntl = ocm->isacntl; 804 dsacntl = ocm->dsacntl; 805 switch (dcrn) { 806 case OCM0_ISARC: 807 isarc = val & 0xFC000000; 808 break; 809 case OCM0_ISACNTL: 810 isacntl = val & 0xC0000000; 811 break; 812 case OCM0_DSARC: 813 isarc = val & 0xFC000000; 814 break; 815 case OCM0_DSACNTL: 816 isacntl = val & 0xC0000000; 817 break; 818 } 819 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 820 ocm->isarc = isarc; 821 ocm->dsarc = dsarc; 822 ocm->isacntl = isacntl; 823 ocm->dsacntl = dsacntl; 824 } 825 826 static void ppc405_ocm_reset(DeviceState *dev) 827 { 828 Ppc405OcmState *ocm = PPC405_OCM(dev); 829 uint32_t isarc, dsarc, isacntl, dsacntl; 830 831 isarc = 0x00000000; 832 isacntl = 0x00000000; 833 dsarc = 0x00000000; 834 dsacntl = 0x00000000; 835 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 836 ocm->isarc = isarc; 837 ocm->dsarc = dsarc; 838 ocm->isacntl = isacntl; 839 ocm->dsacntl = dsacntl; 840 } 841 842 static void ppc405_ocm_realize(DeviceState *dev, Error **errp) 843 { 844 Ppc405OcmState *ocm = PPC405_OCM(dev); 845 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 846 847 /* XXX: Size is 4096 or 0x04000000 */ 848 memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB, 849 &error_fatal); 850 memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc", 851 &ocm->isarc_ram, 0, 4 * KiB); 852 853 ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); 854 ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm); 855 ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm); 856 ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm); 857 } 858 859 static void ppc405_ocm_class_init(ObjectClass *oc, void *data) 860 { 861 DeviceClass *dc = DEVICE_CLASS(oc); 862 863 dc->realize = ppc405_ocm_realize; 864 dc->reset = ppc405_ocm_reset; 865 /* Reason: only works as function of a ppc4xx SoC */ 866 dc->user_creatable = false; 867 } 868 869 /*****************************************************************************/ 870 /* General purpose timers */ 871 static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n) 872 { 873 /* XXX: TODO */ 874 return 0; 875 } 876 877 static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level) 878 { 879 /* XXX: TODO */ 880 } 881 882 static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt) 883 { 884 uint32_t mask; 885 int i; 886 887 mask = 0x80000000; 888 for (i = 0; i < 5; i++) { 889 if (gpt->oe & mask) { 890 /* Output is enabled */ 891 if (ppc4xx_gpt_compare(gpt, i)) { 892 /* Comparison is OK */ 893 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 894 } else { 895 /* Comparison is KO */ 896 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 897 } 898 } 899 mask = mask >> 1; 900 } 901 } 902 903 static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) 904 { 905 uint32_t mask; 906 int i; 907 908 mask = 0x00008000; 909 for (i = 0; i < 5; i++) { 910 if (gpt->is & gpt->im & mask) 911 qemu_irq_raise(gpt->irqs[i]); 912 else 913 qemu_irq_lower(gpt->irqs[i]); 914 mask = mask >> 1; 915 } 916 } 917 918 static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt) 919 { 920 /* XXX: TODO */ 921 } 922 923 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 924 { 925 Ppc405GptState *gpt = opaque; 926 uint32_t ret; 927 int idx; 928 929 trace_ppc4xx_gpt_read(addr, size); 930 931 switch (addr) { 932 case 0x00: 933 /* Time base counter */ 934 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 935 gpt->tb_freq, NANOSECONDS_PER_SECOND); 936 break; 937 case 0x10: 938 /* Output enable */ 939 ret = gpt->oe; 940 break; 941 case 0x14: 942 /* Output level */ 943 ret = gpt->ol; 944 break; 945 case 0x18: 946 /* Interrupt mask */ 947 ret = gpt->im; 948 break; 949 case 0x1C: 950 case 0x20: 951 /* Interrupt status */ 952 ret = gpt->is; 953 break; 954 case 0x24: 955 /* Interrupt enable */ 956 ret = gpt->ie; 957 break; 958 case 0x80 ... 0x90: 959 /* Compare timer */ 960 idx = (addr - 0x80) >> 2; 961 ret = gpt->comp[idx]; 962 break; 963 case 0xC0 ... 0xD0: 964 /* Compare mask */ 965 idx = (addr - 0xC0) >> 2; 966 ret = gpt->mask[idx]; 967 break; 968 default: 969 ret = -1; 970 break; 971 } 972 973 return ret; 974 } 975 976 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 977 unsigned size) 978 { 979 Ppc405GptState *gpt = opaque; 980 int idx; 981 982 trace_ppc4xx_gpt_write(addr, size, value); 983 984 switch (addr) { 985 case 0x00: 986 /* Time base counter */ 987 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 988 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 989 ppc4xx_gpt_compute_timer(gpt); 990 break; 991 case 0x10: 992 /* Output enable */ 993 gpt->oe = value & 0xF8000000; 994 ppc4xx_gpt_set_outputs(gpt); 995 break; 996 case 0x14: 997 /* Output level */ 998 gpt->ol = value & 0xF8000000; 999 ppc4xx_gpt_set_outputs(gpt); 1000 break; 1001 case 0x18: 1002 /* Interrupt mask */ 1003 gpt->im = value & 0x0000F800; 1004 break; 1005 case 0x1C: 1006 /* Interrupt status set */ 1007 gpt->is |= value & 0x0000F800; 1008 ppc4xx_gpt_set_irqs(gpt); 1009 break; 1010 case 0x20: 1011 /* Interrupt status clear */ 1012 gpt->is &= ~(value & 0x0000F800); 1013 ppc4xx_gpt_set_irqs(gpt); 1014 break; 1015 case 0x24: 1016 /* Interrupt enable */ 1017 gpt->ie = value & 0x0000F800; 1018 ppc4xx_gpt_set_irqs(gpt); 1019 break; 1020 case 0x80 ... 0x90: 1021 /* Compare timer */ 1022 idx = (addr - 0x80) >> 2; 1023 gpt->comp[idx] = value & 0xF8000000; 1024 ppc4xx_gpt_compute_timer(gpt); 1025 break; 1026 case 0xC0 ... 0xD0: 1027 /* Compare mask */ 1028 idx = (addr - 0xC0) >> 2; 1029 gpt->mask[idx] = value & 0xF8000000; 1030 ppc4xx_gpt_compute_timer(gpt); 1031 break; 1032 } 1033 } 1034 1035 static const MemoryRegionOps gpt_ops = { 1036 .read = ppc4xx_gpt_read, 1037 .write = ppc4xx_gpt_write, 1038 .valid.min_access_size = 4, 1039 .valid.max_access_size = 4, 1040 .endianness = DEVICE_NATIVE_ENDIAN, 1041 }; 1042 1043 static void ppc4xx_gpt_cb(void *opaque) 1044 { 1045 Ppc405GptState *gpt = opaque; 1046 1047 ppc4xx_gpt_set_irqs(gpt); 1048 ppc4xx_gpt_set_outputs(gpt); 1049 ppc4xx_gpt_compute_timer(gpt); 1050 } 1051 1052 static void ppc405_gpt_reset(DeviceState *dev) 1053 { 1054 Ppc405GptState *gpt = PPC405_GPT(dev); 1055 int i; 1056 1057 timer_del(gpt->timer); 1058 gpt->oe = 0x00000000; 1059 gpt->ol = 0x00000000; 1060 gpt->im = 0x00000000; 1061 gpt->is = 0x00000000; 1062 gpt->ie = 0x00000000; 1063 for (i = 0; i < 5; i++) { 1064 gpt->comp[i] = 0x00000000; 1065 gpt->mask[i] = 0x00000000; 1066 } 1067 } 1068 1069 static void ppc405_gpt_realize(DeviceState *dev, Error **errp) 1070 { 1071 Ppc405GptState *s = PPC405_GPT(dev); 1072 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1073 int i; 1074 1075 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); 1076 memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4); 1077 sysbus_init_mmio(sbd, &s->iomem); 1078 1079 for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { 1080 sysbus_init_irq(sbd, &s->irqs[i]); 1081 } 1082 } 1083 1084 static void ppc405_gpt_finalize(Object *obj) 1085 { 1086 /* timer will be NULL if the GPT wasn't realized */ 1087 if (PPC405_GPT(obj)->timer) { 1088 timer_del(PPC405_GPT(obj)->timer); 1089 } 1090 } 1091 1092 static void ppc405_gpt_class_init(ObjectClass *oc, void *data) 1093 { 1094 DeviceClass *dc = DEVICE_CLASS(oc); 1095 1096 dc->realize = ppc405_gpt_realize; 1097 dc->reset = ppc405_gpt_reset; 1098 /* Reason: only works as function of a ppc4xx SoC */ 1099 dc->user_creatable = false; 1100 } 1101 1102 /*****************************************************************************/ 1103 /* PowerPC 405EP */ 1104 /* CPU control */ 1105 enum { 1106 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1107 PPC405EP_CPC0_BOOT = 0x0F1, 1108 PPC405EP_CPC0_EPCTL = 0x0F3, 1109 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1110 PPC405EP_CPC0_UCR = 0x0F5, 1111 PPC405EP_CPC0_SRR = 0x0F6, 1112 PPC405EP_CPC0_JTAGID = 0x0F7, 1113 PPC405EP_CPC0_PCI = 0x0F9, 1114 #if 0 1115 PPC405EP_CPC0_ER = xxx, 1116 PPC405EP_CPC0_FR = xxx, 1117 PPC405EP_CPC0_SR = xxx, 1118 #endif 1119 }; 1120 1121 static void ppc405ep_compute_clocks(Ppc405CpcState *cpc) 1122 { 1123 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1124 uint32_t UART0_clk, UART1_clk; 1125 uint64_t VCO_out, PLL_out; 1126 int M, D; 1127 1128 VCO_out = 0; 1129 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1130 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1131 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); 1132 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1133 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); 1134 VCO_out = (uint64_t)cpc->sysclk * M * D; 1135 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1136 /* Error - unlock the PLL */ 1137 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", 1138 VCO_out); 1139 #if 0 1140 cpc->pllmr[1] &= ~0x80000000; 1141 goto pll_bypass; 1142 #endif 1143 } 1144 PLL_out = VCO_out / D; 1145 /* Pretend the PLL is locked */ 1146 cpc->boot |= 0x00000001; 1147 } else { 1148 #if 0 1149 pll_bypass: 1150 #endif 1151 PLL_out = cpc->sysclk; 1152 if (cpc->pllmr[1] & 0x40000000) { 1153 /* Pretend the PLL is not locked */ 1154 cpc->boot &= ~0x00000001; 1155 } 1156 } 1157 /* Now, compute all other clocks */ 1158 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1159 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); 1160 CPU_clk = PLL_out / D; 1161 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1162 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); 1163 PLB_clk = CPU_clk / D; 1164 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1165 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); 1166 OPB_clk = PLB_clk / D; 1167 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1168 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); 1169 EBC_clk = PLB_clk / D; 1170 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1171 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); 1172 MAL_clk = PLB_clk / D; 1173 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1174 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); 1175 PCI_clk = PLB_clk / D; 1176 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1177 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); 1178 UART0_clk = PLL_out / D; 1179 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1180 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); 1181 UART1_clk = PLL_out / D; 1182 1183 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { 1184 g_autofree char *trace = g_strdup_printf( 1185 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1186 " PLL out %" PRIu64 " Hz\n" 1187 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1188 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1189 " UART1 %" PRIu32 "\n", 1190 cpc->sysclk, VCO_out, PLL_out, 1191 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1192 UART0_clk, UART1_clk); 1193 trace_ppc405ep_clocks_setup(trace); 1194 } 1195 1196 /* Setup CPU clocks */ 1197 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1198 /* Setup PLB clock */ 1199 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1200 /* Setup OPB clock */ 1201 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1202 /* Setup external clock */ 1203 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1204 /* Setup MAL clock */ 1205 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1206 /* Setup PCI clock */ 1207 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1208 /* Setup UART0 clock */ 1209 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1210 /* Setup UART1 clock */ 1211 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1212 } 1213 1214 static uint32_t dcr_read_epcpc(void *opaque, int dcrn) 1215 { 1216 Ppc405CpcState *cpc = opaque; 1217 uint32_t ret; 1218 1219 switch (dcrn) { 1220 case PPC405EP_CPC0_BOOT: 1221 ret = cpc->boot; 1222 break; 1223 case PPC405EP_CPC0_EPCTL: 1224 ret = cpc->epctl; 1225 break; 1226 case PPC405EP_CPC0_PLLMR0: 1227 ret = cpc->pllmr[0]; 1228 break; 1229 case PPC405EP_CPC0_PLLMR1: 1230 ret = cpc->pllmr[1]; 1231 break; 1232 case PPC405EP_CPC0_UCR: 1233 ret = cpc->ucr; 1234 break; 1235 case PPC405EP_CPC0_SRR: 1236 ret = cpc->srr; 1237 break; 1238 case PPC405EP_CPC0_JTAGID: 1239 ret = cpc->jtagid; 1240 break; 1241 case PPC405EP_CPC0_PCI: 1242 ret = cpc->pci; 1243 break; 1244 default: 1245 /* Avoid gcc warning */ 1246 ret = 0; 1247 break; 1248 } 1249 1250 return ret; 1251 } 1252 1253 static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val) 1254 { 1255 Ppc405CpcState *cpc = opaque; 1256 1257 switch (dcrn) { 1258 case PPC405EP_CPC0_BOOT: 1259 /* Read-only register */ 1260 break; 1261 case PPC405EP_CPC0_EPCTL: 1262 /* Don't care for now */ 1263 cpc->epctl = val & 0xC00000F3; 1264 break; 1265 case PPC405EP_CPC0_PLLMR0: 1266 cpc->pllmr[0] = val & 0x00633333; 1267 ppc405ep_compute_clocks(cpc); 1268 break; 1269 case PPC405EP_CPC0_PLLMR1: 1270 cpc->pllmr[1] = val & 0xC0F73FFF; 1271 ppc405ep_compute_clocks(cpc); 1272 break; 1273 case PPC405EP_CPC0_UCR: 1274 /* UART control - don't care for now */ 1275 cpc->ucr = val & 0x003F7F7F; 1276 break; 1277 case PPC405EP_CPC0_SRR: 1278 cpc->srr = val; 1279 break; 1280 case PPC405EP_CPC0_JTAGID: 1281 /* Read-only */ 1282 break; 1283 case PPC405EP_CPC0_PCI: 1284 cpc->pci = val; 1285 break; 1286 } 1287 } 1288 1289 static void ppc405_cpc_reset(DeviceState *dev) 1290 { 1291 Ppc405CpcState *cpc = PPC405_CPC(dev); 1292 1293 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1294 cpc->epctl = 0x00000000; 1295 cpc->pllmr[0] = 0x00021002; 1296 cpc->pllmr[1] = 0x80a552be; 1297 cpc->ucr = 0x00004646; 1298 cpc->srr = 0x00040000; 1299 cpc->pci = 0x00000000; 1300 cpc->er = 0x00000000; 1301 cpc->fr = 0x00000000; 1302 cpc->sr = 0x00000000; 1303 cpc->jtagid = 0x20267049; 1304 ppc405ep_compute_clocks(cpc); 1305 } 1306 1307 /* XXX: sysclk should be between 25 and 100 MHz */ 1308 static void ppc405_cpc_realize(DeviceState *dev, Error **errp) 1309 { 1310 Ppc405CpcState *cpc = PPC405_CPC(dev); 1311 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 1312 1313 assert(dcr->cpu); 1314 cpc->clk_setup[PPC405EP_CPU_CLK].cb = 1315 ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT); 1316 cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env; 1317 1318 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc, 1319 &dcr_read_epcpc, &dcr_write_epcpc); 1320 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc, 1321 &dcr_read_epcpc, &dcr_write_epcpc); 1322 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc, 1323 &dcr_read_epcpc, &dcr_write_epcpc); 1324 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc, 1325 &dcr_read_epcpc, &dcr_write_epcpc); 1326 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc, 1327 &dcr_read_epcpc, &dcr_write_epcpc); 1328 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc, 1329 &dcr_read_epcpc, &dcr_write_epcpc); 1330 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc, 1331 &dcr_read_epcpc, &dcr_write_epcpc); 1332 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc, 1333 &dcr_read_epcpc, &dcr_write_epcpc); 1334 } 1335 1336 static Property ppc405_cpc_properties[] = { 1337 DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0), 1338 DEFINE_PROP_END_OF_LIST(), 1339 }; 1340 1341 static void ppc405_cpc_class_init(ObjectClass *oc, void *data) 1342 { 1343 DeviceClass *dc = DEVICE_CLASS(oc); 1344 1345 dc->realize = ppc405_cpc_realize; 1346 dc->reset = ppc405_cpc_reset; 1347 /* Reason: only works as function of a ppc4xx SoC */ 1348 dc->user_creatable = false; 1349 device_class_set_props(dc, ppc405_cpc_properties); 1350 } 1351 1352 /* PPC405_SOC */ 1353 1354 static void ppc405_soc_instance_init(Object *obj) 1355 { 1356 Ppc405SoCState *s = PPC405_SOC(obj); 1357 1358 object_initialize_child(obj, "cpu", &s->cpu, 1359 POWERPC_CPU_TYPE_NAME("405ep")); 1360 1361 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); 1362 object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); 1363 1364 object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); 1365 1366 object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); 1367 1368 object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); 1369 1370 object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); 1371 1372 object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); 1373 1374 object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); 1375 1376 object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); 1377 } 1378 1379 static void ppc405_reset(void *opaque) 1380 { 1381 cpu_reset(CPU(opaque)); 1382 } 1383 1384 static void ppc405_soc_realize(DeviceState *dev, Error **errp) 1385 { 1386 Ppc405SoCState *s = PPC405_SOC(dev); 1387 qemu_irq mal_irqs[4]; 1388 CPUPPCState *env; 1389 SysBusDevice *sbd; 1390 int i; 1391 1392 /* init CPUs */ 1393 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { 1394 return; 1395 } 1396 qemu_register_reset(ppc405_reset, &s->cpu); 1397 1398 env = &s->cpu.env; 1399 1400 ppc_dcr_init(env, NULL, NULL); 1401 1402 /* CPU control */ 1403 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) { 1404 return; 1405 } 1406 1407 /* PLB arbitrer */ 1408 ppc4xx_plb_init(env); 1409 1410 /* PLB to OPB bridge */ 1411 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) { 1412 return; 1413 } 1414 1415 /* OBP arbitrer */ 1416 sbd = SYS_BUS_DEVICE(&s->opba); 1417 if (!sysbus_realize(sbd, errp)) { 1418 return; 1419 } 1420 sysbus_mmio_map(sbd, 0, 0xef600600); 1421 1422 /* Universal interrupt controller */ 1423 s->uic = qdev_new(TYPE_PPC_UIC); 1424 1425 object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu), 1426 &error_fatal); 1427 if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { 1428 return; 1429 } 1430 1431 sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT, 1432 qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)); 1433 sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, 1434 qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT)); 1435 1436 /* SDRAM controller */ 1437 /* XXX 405EP has no ECC interrupt */ 1438 s->ram_bases[0] = 0; 1439 s->ram_sizes[0] = s->ram_size; 1440 memory_region_init_alias(&s->ram_banks[0], OBJECT(s), 1441 "ppc405.sdram0", s->dram_mr, 1442 s->ram_bases[0], s->ram_sizes[0]); 1443 1444 ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1, 1445 s->ram_banks, s->ram_bases, s->ram_sizes, 1446 s->do_dram_init); 1447 1448 /* External bus controller */ 1449 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { 1450 return; 1451 } 1452 1453 /* DMA controller */ 1454 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) { 1455 return; 1456 } 1457 sbd = SYS_BUS_DEVICE(&s->dma); 1458 for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) { 1459 sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i)); 1460 } 1461 1462 /* I2C controller */ 1463 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1464 qdev_get_gpio_in(s->uic, 2)); 1465 1466 /* GPIO */ 1467 sbd = SYS_BUS_DEVICE(&s->gpio); 1468 if (!sysbus_realize(sbd, errp)) { 1469 return; 1470 } 1471 sysbus_mmio_map(sbd, 0, 0xef600700); 1472 1473 /* Serial ports */ 1474 if (serial_hd(0) != NULL) { 1475 serial_mm_init(get_system_memory(), 0xef600300, 0, 1476 qdev_get_gpio_in(s->uic, 0), 1477 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1478 DEVICE_BIG_ENDIAN); 1479 } 1480 if (serial_hd(1) != NULL) { 1481 serial_mm_init(get_system_memory(), 0xef600400, 0, 1482 qdev_get_gpio_in(s->uic, 1), 1483 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1484 DEVICE_BIG_ENDIAN); 1485 } 1486 1487 /* OCM */ 1488 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) { 1489 return; 1490 } 1491 1492 /* GPT */ 1493 sbd = SYS_BUS_DEVICE(&s->gpt); 1494 if (!sysbus_realize(sbd, errp)) { 1495 return; 1496 } 1497 sysbus_mmio_map(sbd, 0, 0xef600000); 1498 for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { 1499 sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i)); 1500 } 1501 1502 /* MAL */ 1503 mal_irqs[0] = qdev_get_gpio_in(s->uic, 11); 1504 mal_irqs[1] = qdev_get_gpio_in(s->uic, 12); 1505 mal_irqs[2] = qdev_get_gpio_in(s->uic, 13); 1506 mal_irqs[3] = qdev_get_gpio_in(s->uic, 14); 1507 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1508 1509 /* Ethernet */ 1510 /* Uses UIC IRQs 9, 15, 17 */ 1511 } 1512 1513 static Property ppc405_soc_properties[] = { 1514 DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, 1515 MemoryRegion *), 1516 DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0), 1517 DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), 1518 DEFINE_PROP_END_OF_LIST(), 1519 }; 1520 1521 static void ppc405_soc_class_init(ObjectClass *oc, void *data) 1522 { 1523 DeviceClass *dc = DEVICE_CLASS(oc); 1524 1525 dc->realize = ppc405_soc_realize; 1526 /* Reason: only works as part of a ppc405 board/machine */ 1527 dc->user_creatable = false; 1528 device_class_set_props(dc, ppc405_soc_properties); 1529 } 1530 1531 static const TypeInfo ppc405_types[] = { 1532 { 1533 .name = TYPE_PPC405_POB, 1534 .parent = TYPE_PPC4xx_DCR_DEVICE, 1535 .instance_size = sizeof(Ppc405PobState), 1536 .class_init = ppc405_pob_class_init, 1537 }, { 1538 .name = TYPE_PPC405_OPBA, 1539 .parent = TYPE_SYS_BUS_DEVICE, 1540 .instance_size = sizeof(Ppc405OpbaState), 1541 .class_init = ppc405_opba_class_init, 1542 }, { 1543 .name = TYPE_PPC405_EBC, 1544 .parent = TYPE_PPC4xx_DCR_DEVICE, 1545 .instance_size = sizeof(Ppc405EbcState), 1546 .class_init = ppc405_ebc_class_init, 1547 }, { 1548 .name = TYPE_PPC405_DMA, 1549 .parent = TYPE_PPC4xx_DCR_DEVICE, 1550 .instance_size = sizeof(Ppc405DmaState), 1551 .class_init = ppc405_dma_class_init, 1552 }, { 1553 .name = TYPE_PPC405_GPIO, 1554 .parent = TYPE_SYS_BUS_DEVICE, 1555 .instance_size = sizeof(Ppc405GpioState), 1556 .class_init = ppc405_gpio_class_init, 1557 }, { 1558 .name = TYPE_PPC405_OCM, 1559 .parent = TYPE_PPC4xx_DCR_DEVICE, 1560 .instance_size = sizeof(Ppc405OcmState), 1561 .class_init = ppc405_ocm_class_init, 1562 }, { 1563 .name = TYPE_PPC405_GPT, 1564 .parent = TYPE_SYS_BUS_DEVICE, 1565 .instance_size = sizeof(Ppc405GptState), 1566 .instance_finalize = ppc405_gpt_finalize, 1567 .class_init = ppc405_gpt_class_init, 1568 }, { 1569 .name = TYPE_PPC405_CPC, 1570 .parent = TYPE_PPC4xx_DCR_DEVICE, 1571 .instance_size = sizeof(Ppc405CpcState), 1572 .class_init = ppc405_cpc_class_init, 1573 }, { 1574 .name = TYPE_PPC405_SOC, 1575 .parent = TYPE_DEVICE, 1576 .instance_size = sizeof(Ppc405SoCState), 1577 .instance_init = ppc405_soc_instance_init, 1578 .class_init = ppc405_soc_class_init, 1579 } 1580 }; 1581 1582 DEFINE_TYPES(ppc405_types) 1583