1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "ppc405.h" 35 #include "hw/char/serial.h" 36 #include "qemu/timer.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/address-spaces.h" 40 #include "hw/intc/ppc-uic.h" 41 #include "hw/qdev-properties.h" 42 #include "qapi/error.h" 43 #include "trace.h" 44 45 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, 46 ram_addr_t ram_size) 47 { 48 memset(bd, 0, sizeof(*bd)); 49 50 bd->bi_memstart = PPC405EP_SDRAM_BASE; 51 bd->bi_memsize = ram_size; 52 bd->bi_sramstart = PPC405EP_SRAM_BASE; 53 bd->bi_sramsize = PPC405EP_SRAM_SIZE; 54 bd->bi_bootflags = 0; 55 bd->bi_intfreq = 133333333; 56 bd->bi_busfreq = 33333333; 57 bd->bi_baudrate = 115200; 58 bd->bi_s_version[0] = 'Q'; 59 bd->bi_s_version[1] = 'M'; 60 bd->bi_s_version[2] = 'U'; 61 bd->bi_s_version[3] = '\0'; 62 bd->bi_r_version[0] = 'Q'; 63 bd->bi_r_version[1] = 'E'; 64 bd->bi_r_version[2] = 'M'; 65 bd->bi_r_version[3] = 'U'; 66 bd->bi_r_version[4] = '\0'; 67 bd->bi_procfreq = 133333333; 68 bd->bi_plb_busfreq = 33333333; 69 bd->bi_pci_busfreq = 33333333; 70 bd->bi_opbfreq = 33333333; 71 } 72 73 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) 74 { 75 CPUState *cs = env_cpu(env); 76 ram_addr_t bdloc; 77 int i, n; 78 79 /* We put the bd structure at the top of memory */ 80 if (bd->bi_memsize >= 0x01000000UL) 81 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 82 else 83 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 84 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 85 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 86 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 87 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 88 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 89 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 90 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 91 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 92 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 93 for (i = 0; i < 6; i++) { 94 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 95 } 96 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 97 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 98 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 99 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 100 for (i = 0; i < 4; i++) { 101 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 102 } 103 for (i = 0; i < 32; i++) { 104 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 105 } 106 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); 107 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); 108 stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); 109 for (i = 0; i < 6; i++) { 110 stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); 111 } 112 n = 0x70; /* includes 2 bytes hole */ 113 for (i = 0; i < 6; i++) { 114 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 115 } 116 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 117 n += 4; 118 for (i = 0; i < 2; i++) { 119 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 120 n += 4; 121 } 122 123 return bdloc; 124 } 125 126 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) 127 { 128 ppc4xx_bd_info_t bd; 129 130 memset(&bd, 0, sizeof(bd)); 131 132 ppc405_set_default_bootinfo(&bd, ram_size); 133 134 return __ppc405_set_bootinfo(env, &bd); 135 } 136 137 /*****************************************************************************/ 138 /* Shared peripherals */ 139 140 /*****************************************************************************/ 141 /* Peripheral local bus arbitrer */ 142 enum { 143 PLB3A0_ACR = 0x077, 144 PLB4A0_ACR = 0x081, 145 PLB0_BESR = 0x084, 146 PLB0_BEAR = 0x086, 147 PLB0_ACR = 0x087, 148 PLB4A1_ACR = 0x089, 149 }; 150 151 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 152 struct ppc4xx_plb_t { 153 uint32_t acr; 154 uint32_t bear; 155 uint32_t besr; 156 }; 157 158 static uint32_t dcr_read_plb (void *opaque, int dcrn) 159 { 160 ppc4xx_plb_t *plb; 161 uint32_t ret; 162 163 plb = opaque; 164 switch (dcrn) { 165 case PLB0_ACR: 166 ret = plb->acr; 167 break; 168 case PLB0_BEAR: 169 ret = plb->bear; 170 break; 171 case PLB0_BESR: 172 ret = plb->besr; 173 break; 174 default: 175 /* Avoid gcc warning */ 176 ret = 0; 177 break; 178 } 179 180 return ret; 181 } 182 183 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 184 { 185 ppc4xx_plb_t *plb; 186 187 plb = opaque; 188 switch (dcrn) { 189 case PLB0_ACR: 190 /* We don't care about the actual parameters written as 191 * we don't manage any priorities on the bus 192 */ 193 plb->acr = val & 0xF8000000; 194 break; 195 case PLB0_BEAR: 196 /* Read only */ 197 break; 198 case PLB0_BESR: 199 /* Write-clear */ 200 plb->besr &= ~val; 201 break; 202 } 203 } 204 205 static void ppc4xx_plb_reset (void *opaque) 206 { 207 ppc4xx_plb_t *plb; 208 209 plb = opaque; 210 plb->acr = 0x00000000; 211 plb->bear = 0x00000000; 212 plb->besr = 0x00000000; 213 } 214 215 void ppc4xx_plb_init(CPUPPCState *env) 216 { 217 ppc4xx_plb_t *plb; 218 219 plb = g_new0(ppc4xx_plb_t, 1); 220 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 221 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 222 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 223 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 224 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 225 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 226 qemu_register_reset(ppc4xx_plb_reset, plb); 227 } 228 229 /*****************************************************************************/ 230 /* PLB to OPB bridge */ 231 enum { 232 POB0_BESR0 = 0x0A0, 233 POB0_BESR1 = 0x0A2, 234 POB0_BEAR = 0x0A4, 235 }; 236 237 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 238 struct ppc4xx_pob_t { 239 uint32_t bear; 240 uint32_t besr0; 241 uint32_t besr1; 242 }; 243 244 static uint32_t dcr_read_pob (void *opaque, int dcrn) 245 { 246 ppc4xx_pob_t *pob; 247 uint32_t ret; 248 249 pob = opaque; 250 switch (dcrn) { 251 case POB0_BEAR: 252 ret = pob->bear; 253 break; 254 case POB0_BESR0: 255 ret = pob->besr0; 256 break; 257 case POB0_BESR1: 258 ret = pob->besr1; 259 break; 260 default: 261 /* Avoid gcc warning */ 262 ret = 0; 263 break; 264 } 265 266 return ret; 267 } 268 269 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 270 { 271 ppc4xx_pob_t *pob; 272 273 pob = opaque; 274 switch (dcrn) { 275 case POB0_BEAR: 276 /* Read only */ 277 break; 278 case POB0_BESR0: 279 /* Write-clear */ 280 pob->besr0 &= ~val; 281 break; 282 case POB0_BESR1: 283 /* Write-clear */ 284 pob->besr1 &= ~val; 285 break; 286 } 287 } 288 289 static void ppc4xx_pob_reset (void *opaque) 290 { 291 ppc4xx_pob_t *pob; 292 293 pob = opaque; 294 /* No error */ 295 pob->bear = 0x00000000; 296 pob->besr0 = 0x0000000; 297 pob->besr1 = 0x0000000; 298 } 299 300 static void ppc4xx_pob_init(CPUPPCState *env) 301 { 302 ppc4xx_pob_t *pob; 303 304 pob = g_new0(ppc4xx_pob_t, 1); 305 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 306 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 307 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 308 qemu_register_reset(ppc4xx_pob_reset, pob); 309 } 310 311 /*****************************************************************************/ 312 /* OPB arbitrer */ 313 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 314 struct ppc4xx_opba_t { 315 MemoryRegion io; 316 uint8_t cr; 317 uint8_t pr; 318 }; 319 320 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 321 { 322 ppc4xx_opba_t *opba = opaque; 323 uint32_t ret; 324 325 switch (addr) { 326 case 0x00: 327 ret = opba->cr; 328 break; 329 case 0x01: 330 ret = opba->pr; 331 break; 332 default: 333 ret = 0x00; 334 break; 335 } 336 337 trace_opba_readb(addr, ret); 338 return ret; 339 } 340 341 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 342 unsigned size) 343 { 344 ppc4xx_opba_t *opba = opaque; 345 346 trace_opba_writeb(addr, value); 347 348 switch (addr) { 349 case 0x00: 350 opba->cr = value & 0xF8; 351 break; 352 case 0x01: 353 opba->pr = value & 0xFF; 354 break; 355 default: 356 break; 357 } 358 } 359 static const MemoryRegionOps opba_ops = { 360 .read = opba_readb, 361 .write = opba_writeb, 362 .impl.min_access_size = 1, 363 .impl.max_access_size = 1, 364 .valid.min_access_size = 1, 365 .valid.max_access_size = 4, 366 .endianness = DEVICE_BIG_ENDIAN, 367 }; 368 369 static void ppc4xx_opba_reset (void *opaque) 370 { 371 ppc4xx_opba_t *opba; 372 373 opba = opaque; 374 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 375 opba->pr = 0x11; 376 } 377 378 static void ppc4xx_opba_init(hwaddr base) 379 { 380 ppc4xx_opba_t *opba; 381 382 trace_opba_init(base); 383 384 opba = g_new0(ppc4xx_opba_t, 1); 385 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 386 memory_region_add_subregion(get_system_memory(), base, &opba->io); 387 qemu_register_reset(ppc4xx_opba_reset, opba); 388 } 389 390 /*****************************************************************************/ 391 /* Code decompression controller */ 392 /* XXX: TODO */ 393 394 /*****************************************************************************/ 395 /* Peripheral controller */ 396 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 397 struct ppc4xx_ebc_t { 398 uint32_t addr; 399 uint32_t bcr[8]; 400 uint32_t bap[8]; 401 uint32_t bear; 402 uint32_t besr0; 403 uint32_t besr1; 404 uint32_t cfg; 405 }; 406 407 enum { 408 EBC0_CFGADDR = 0x012, 409 EBC0_CFGDATA = 0x013, 410 }; 411 412 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 413 { 414 ppc4xx_ebc_t *ebc; 415 uint32_t ret; 416 417 ebc = opaque; 418 switch (dcrn) { 419 case EBC0_CFGADDR: 420 ret = ebc->addr; 421 break; 422 case EBC0_CFGDATA: 423 switch (ebc->addr) { 424 case 0x00: /* B0CR */ 425 ret = ebc->bcr[0]; 426 break; 427 case 0x01: /* B1CR */ 428 ret = ebc->bcr[1]; 429 break; 430 case 0x02: /* B2CR */ 431 ret = ebc->bcr[2]; 432 break; 433 case 0x03: /* B3CR */ 434 ret = ebc->bcr[3]; 435 break; 436 case 0x04: /* B4CR */ 437 ret = ebc->bcr[4]; 438 break; 439 case 0x05: /* B5CR */ 440 ret = ebc->bcr[5]; 441 break; 442 case 0x06: /* B6CR */ 443 ret = ebc->bcr[6]; 444 break; 445 case 0x07: /* B7CR */ 446 ret = ebc->bcr[7]; 447 break; 448 case 0x10: /* B0AP */ 449 ret = ebc->bap[0]; 450 break; 451 case 0x11: /* B1AP */ 452 ret = ebc->bap[1]; 453 break; 454 case 0x12: /* B2AP */ 455 ret = ebc->bap[2]; 456 break; 457 case 0x13: /* B3AP */ 458 ret = ebc->bap[3]; 459 break; 460 case 0x14: /* B4AP */ 461 ret = ebc->bap[4]; 462 break; 463 case 0x15: /* B5AP */ 464 ret = ebc->bap[5]; 465 break; 466 case 0x16: /* B6AP */ 467 ret = ebc->bap[6]; 468 break; 469 case 0x17: /* B7AP */ 470 ret = ebc->bap[7]; 471 break; 472 case 0x20: /* BEAR */ 473 ret = ebc->bear; 474 break; 475 case 0x21: /* BESR0 */ 476 ret = ebc->besr0; 477 break; 478 case 0x22: /* BESR1 */ 479 ret = ebc->besr1; 480 break; 481 case 0x23: /* CFG */ 482 ret = ebc->cfg; 483 break; 484 default: 485 ret = 0x00000000; 486 break; 487 } 488 break; 489 default: 490 ret = 0x00000000; 491 break; 492 } 493 494 return ret; 495 } 496 497 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 498 { 499 ppc4xx_ebc_t *ebc; 500 501 ebc = opaque; 502 switch (dcrn) { 503 case EBC0_CFGADDR: 504 ebc->addr = val; 505 break; 506 case EBC0_CFGDATA: 507 switch (ebc->addr) { 508 case 0x00: /* B0CR */ 509 break; 510 case 0x01: /* B1CR */ 511 break; 512 case 0x02: /* B2CR */ 513 break; 514 case 0x03: /* B3CR */ 515 break; 516 case 0x04: /* B4CR */ 517 break; 518 case 0x05: /* B5CR */ 519 break; 520 case 0x06: /* B6CR */ 521 break; 522 case 0x07: /* B7CR */ 523 break; 524 case 0x10: /* B0AP */ 525 break; 526 case 0x11: /* B1AP */ 527 break; 528 case 0x12: /* B2AP */ 529 break; 530 case 0x13: /* B3AP */ 531 break; 532 case 0x14: /* B4AP */ 533 break; 534 case 0x15: /* B5AP */ 535 break; 536 case 0x16: /* B6AP */ 537 break; 538 case 0x17: /* B7AP */ 539 break; 540 case 0x20: /* BEAR */ 541 break; 542 case 0x21: /* BESR0 */ 543 break; 544 case 0x22: /* BESR1 */ 545 break; 546 case 0x23: /* CFG */ 547 break; 548 default: 549 break; 550 } 551 break; 552 default: 553 break; 554 } 555 } 556 557 static void ebc_reset (void *opaque) 558 { 559 ppc4xx_ebc_t *ebc; 560 int i; 561 562 ebc = opaque; 563 ebc->addr = 0x00000000; 564 ebc->bap[0] = 0x7F8FFE80; 565 ebc->bcr[0] = 0xFFE28000; 566 for (i = 0; i < 8; i++) { 567 ebc->bap[i] = 0x00000000; 568 ebc->bcr[i] = 0x00000000; 569 } 570 ebc->besr0 = 0x00000000; 571 ebc->besr1 = 0x00000000; 572 ebc->cfg = 0x80400000; 573 } 574 575 void ppc405_ebc_init(CPUPPCState *env) 576 { 577 ppc4xx_ebc_t *ebc; 578 579 ebc = g_new0(ppc4xx_ebc_t, 1); 580 qemu_register_reset(&ebc_reset, ebc); 581 ppc_dcr_register(env, EBC0_CFGADDR, 582 ebc, &dcr_read_ebc, &dcr_write_ebc); 583 ppc_dcr_register(env, EBC0_CFGDATA, 584 ebc, &dcr_read_ebc, &dcr_write_ebc); 585 } 586 587 /*****************************************************************************/ 588 /* DMA controller */ 589 enum { 590 DMA0_CR0 = 0x100, 591 DMA0_CT0 = 0x101, 592 DMA0_DA0 = 0x102, 593 DMA0_SA0 = 0x103, 594 DMA0_SG0 = 0x104, 595 DMA0_CR1 = 0x108, 596 DMA0_CT1 = 0x109, 597 DMA0_DA1 = 0x10A, 598 DMA0_SA1 = 0x10B, 599 DMA0_SG1 = 0x10C, 600 DMA0_CR2 = 0x110, 601 DMA0_CT2 = 0x111, 602 DMA0_DA2 = 0x112, 603 DMA0_SA2 = 0x113, 604 DMA0_SG2 = 0x114, 605 DMA0_CR3 = 0x118, 606 DMA0_CT3 = 0x119, 607 DMA0_DA3 = 0x11A, 608 DMA0_SA3 = 0x11B, 609 DMA0_SG3 = 0x11C, 610 DMA0_SR = 0x120, 611 DMA0_SGC = 0x123, 612 DMA0_SLP = 0x125, 613 DMA0_POL = 0x126, 614 }; 615 616 typedef struct ppc405_dma_t ppc405_dma_t; 617 struct ppc405_dma_t { 618 qemu_irq irqs[4]; 619 uint32_t cr[4]; 620 uint32_t ct[4]; 621 uint32_t da[4]; 622 uint32_t sa[4]; 623 uint32_t sg[4]; 624 uint32_t sr; 625 uint32_t sgc; 626 uint32_t slp; 627 uint32_t pol; 628 }; 629 630 static uint32_t dcr_read_dma (void *opaque, int dcrn) 631 { 632 return 0; 633 } 634 635 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 636 { 637 } 638 639 static void ppc405_dma_reset (void *opaque) 640 { 641 ppc405_dma_t *dma; 642 int i; 643 644 dma = opaque; 645 for (i = 0; i < 4; i++) { 646 dma->cr[i] = 0x00000000; 647 dma->ct[i] = 0x00000000; 648 dma->da[i] = 0x00000000; 649 dma->sa[i] = 0x00000000; 650 dma->sg[i] = 0x00000000; 651 } 652 dma->sr = 0x00000000; 653 dma->sgc = 0x00000000; 654 dma->slp = 0x7C000000; 655 dma->pol = 0x00000000; 656 } 657 658 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 659 { 660 ppc405_dma_t *dma; 661 662 dma = g_new0(ppc405_dma_t, 1); 663 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 664 qemu_register_reset(&ppc405_dma_reset, dma); 665 ppc_dcr_register(env, DMA0_CR0, 666 dma, &dcr_read_dma, &dcr_write_dma); 667 ppc_dcr_register(env, DMA0_CT0, 668 dma, &dcr_read_dma, &dcr_write_dma); 669 ppc_dcr_register(env, DMA0_DA0, 670 dma, &dcr_read_dma, &dcr_write_dma); 671 ppc_dcr_register(env, DMA0_SA0, 672 dma, &dcr_read_dma, &dcr_write_dma); 673 ppc_dcr_register(env, DMA0_SG0, 674 dma, &dcr_read_dma, &dcr_write_dma); 675 ppc_dcr_register(env, DMA0_CR1, 676 dma, &dcr_read_dma, &dcr_write_dma); 677 ppc_dcr_register(env, DMA0_CT1, 678 dma, &dcr_read_dma, &dcr_write_dma); 679 ppc_dcr_register(env, DMA0_DA1, 680 dma, &dcr_read_dma, &dcr_write_dma); 681 ppc_dcr_register(env, DMA0_SA1, 682 dma, &dcr_read_dma, &dcr_write_dma); 683 ppc_dcr_register(env, DMA0_SG1, 684 dma, &dcr_read_dma, &dcr_write_dma); 685 ppc_dcr_register(env, DMA0_CR2, 686 dma, &dcr_read_dma, &dcr_write_dma); 687 ppc_dcr_register(env, DMA0_CT2, 688 dma, &dcr_read_dma, &dcr_write_dma); 689 ppc_dcr_register(env, DMA0_DA2, 690 dma, &dcr_read_dma, &dcr_write_dma); 691 ppc_dcr_register(env, DMA0_SA2, 692 dma, &dcr_read_dma, &dcr_write_dma); 693 ppc_dcr_register(env, DMA0_SG2, 694 dma, &dcr_read_dma, &dcr_write_dma); 695 ppc_dcr_register(env, DMA0_CR3, 696 dma, &dcr_read_dma, &dcr_write_dma); 697 ppc_dcr_register(env, DMA0_CT3, 698 dma, &dcr_read_dma, &dcr_write_dma); 699 ppc_dcr_register(env, DMA0_DA3, 700 dma, &dcr_read_dma, &dcr_write_dma); 701 ppc_dcr_register(env, DMA0_SA3, 702 dma, &dcr_read_dma, &dcr_write_dma); 703 ppc_dcr_register(env, DMA0_SG3, 704 dma, &dcr_read_dma, &dcr_write_dma); 705 ppc_dcr_register(env, DMA0_SR, 706 dma, &dcr_read_dma, &dcr_write_dma); 707 ppc_dcr_register(env, DMA0_SGC, 708 dma, &dcr_read_dma, &dcr_write_dma); 709 ppc_dcr_register(env, DMA0_SLP, 710 dma, &dcr_read_dma, &dcr_write_dma); 711 ppc_dcr_register(env, DMA0_POL, 712 dma, &dcr_read_dma, &dcr_write_dma); 713 } 714 715 /*****************************************************************************/ 716 /* GPIO */ 717 typedef struct ppc405_gpio_t ppc405_gpio_t; 718 struct ppc405_gpio_t { 719 MemoryRegion io; 720 uint32_t or; 721 uint32_t tcr; 722 uint32_t osrh; 723 uint32_t osrl; 724 uint32_t tsrh; 725 uint32_t tsrl; 726 uint32_t odr; 727 uint32_t ir; 728 uint32_t rr1; 729 uint32_t isr1h; 730 uint32_t isr1l; 731 }; 732 733 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 734 { 735 trace_ppc405_gpio_read(addr, size); 736 return 0; 737 } 738 739 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 740 unsigned size) 741 { 742 trace_ppc405_gpio_write(addr, size, value); 743 } 744 745 static const MemoryRegionOps ppc405_gpio_ops = { 746 .read = ppc405_gpio_read, 747 .write = ppc405_gpio_write, 748 .endianness = DEVICE_NATIVE_ENDIAN, 749 }; 750 751 static void ppc405_gpio_reset (void *opaque) 752 { 753 } 754 755 static void ppc405_gpio_init(hwaddr base) 756 { 757 ppc405_gpio_t *gpio; 758 759 trace_ppc405_gpio_init(base); 760 761 gpio = g_new0(ppc405_gpio_t, 1); 762 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 763 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 764 qemu_register_reset(&ppc405_gpio_reset, gpio); 765 } 766 767 /*****************************************************************************/ 768 /* On Chip Memory */ 769 enum { 770 OCM0_ISARC = 0x018, 771 OCM0_ISACNTL = 0x019, 772 OCM0_DSARC = 0x01A, 773 OCM0_DSACNTL = 0x01B, 774 }; 775 776 typedef struct ppc405_ocm_t ppc405_ocm_t; 777 struct ppc405_ocm_t { 778 MemoryRegion ram; 779 MemoryRegion isarc_ram; 780 MemoryRegion dsarc_ram; 781 uint32_t isarc; 782 uint32_t isacntl; 783 uint32_t dsarc; 784 uint32_t dsacntl; 785 }; 786 787 static void ocm_update_mappings (ppc405_ocm_t *ocm, 788 uint32_t isarc, uint32_t isacntl, 789 uint32_t dsarc, uint32_t dsacntl) 790 { 791 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, 792 ocm->isacntl, ocm->dsarc, ocm->dsacntl); 793 794 if (ocm->isarc != isarc || 795 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 796 if (ocm->isacntl & 0x80000000) { 797 /* Unmap previously assigned memory region */ 798 trace_ocm_unmap("ISA", ocm->isarc); 799 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 800 } 801 if (isacntl & 0x80000000) { 802 /* Map new instruction memory region */ 803 trace_ocm_map("ISA", isarc); 804 memory_region_add_subregion(get_system_memory(), isarc, 805 &ocm->isarc_ram); 806 } 807 } 808 if (ocm->dsarc != dsarc || 809 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 810 if (ocm->dsacntl & 0x80000000) { 811 /* Beware not to unmap the region we just mapped */ 812 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 813 /* Unmap previously assigned memory region */ 814 trace_ocm_unmap("DSA", ocm->dsarc); 815 memory_region_del_subregion(get_system_memory(), 816 &ocm->dsarc_ram); 817 } 818 } 819 if (dsacntl & 0x80000000) { 820 /* Beware not to remap the region we just mapped */ 821 if (!(isacntl & 0x80000000) || dsarc != isarc) { 822 /* Map new data memory region */ 823 trace_ocm_map("DSA", dsarc); 824 memory_region_add_subregion(get_system_memory(), dsarc, 825 &ocm->dsarc_ram); 826 } 827 } 828 } 829 } 830 831 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 832 { 833 ppc405_ocm_t *ocm; 834 uint32_t ret; 835 836 ocm = opaque; 837 switch (dcrn) { 838 case OCM0_ISARC: 839 ret = ocm->isarc; 840 break; 841 case OCM0_ISACNTL: 842 ret = ocm->isacntl; 843 break; 844 case OCM0_DSARC: 845 ret = ocm->dsarc; 846 break; 847 case OCM0_DSACNTL: 848 ret = ocm->dsacntl; 849 break; 850 default: 851 ret = 0; 852 break; 853 } 854 855 return ret; 856 } 857 858 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 859 { 860 ppc405_ocm_t *ocm; 861 uint32_t isarc, dsarc, isacntl, dsacntl; 862 863 ocm = opaque; 864 isarc = ocm->isarc; 865 dsarc = ocm->dsarc; 866 isacntl = ocm->isacntl; 867 dsacntl = ocm->dsacntl; 868 switch (dcrn) { 869 case OCM0_ISARC: 870 isarc = val & 0xFC000000; 871 break; 872 case OCM0_ISACNTL: 873 isacntl = val & 0xC0000000; 874 break; 875 case OCM0_DSARC: 876 isarc = val & 0xFC000000; 877 break; 878 case OCM0_DSACNTL: 879 isacntl = val & 0xC0000000; 880 break; 881 } 882 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 883 ocm->isarc = isarc; 884 ocm->dsarc = dsarc; 885 ocm->isacntl = isacntl; 886 ocm->dsacntl = dsacntl; 887 } 888 889 static void ocm_reset (void *opaque) 890 { 891 ppc405_ocm_t *ocm; 892 uint32_t isarc, dsarc, isacntl, dsacntl; 893 894 ocm = opaque; 895 isarc = 0x00000000; 896 isacntl = 0x00000000; 897 dsarc = 0x00000000; 898 dsacntl = 0x00000000; 899 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 900 ocm->isarc = isarc; 901 ocm->dsarc = dsarc; 902 ocm->isacntl = isacntl; 903 ocm->dsacntl = dsacntl; 904 } 905 906 static void ppc405_ocm_init(CPUPPCState *env) 907 { 908 ppc405_ocm_t *ocm; 909 910 ocm = g_new0(ppc405_ocm_t, 1); 911 /* XXX: Size is 4096 or 0x04000000 */ 912 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 913 &error_fatal); 914 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 915 &ocm->isarc_ram, 0, 4 * KiB); 916 qemu_register_reset(&ocm_reset, ocm); 917 ppc_dcr_register(env, OCM0_ISARC, 918 ocm, &dcr_read_ocm, &dcr_write_ocm); 919 ppc_dcr_register(env, OCM0_ISACNTL, 920 ocm, &dcr_read_ocm, &dcr_write_ocm); 921 ppc_dcr_register(env, OCM0_DSARC, 922 ocm, &dcr_read_ocm, &dcr_write_ocm); 923 ppc_dcr_register(env, OCM0_DSACNTL, 924 ocm, &dcr_read_ocm, &dcr_write_ocm); 925 } 926 927 /*****************************************************************************/ 928 /* General purpose timers */ 929 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 930 struct ppc4xx_gpt_t { 931 MemoryRegion iomem; 932 int64_t tb_offset; 933 uint32_t tb_freq; 934 QEMUTimer *timer; 935 qemu_irq irqs[5]; 936 uint32_t oe; 937 uint32_t ol; 938 uint32_t im; 939 uint32_t is; 940 uint32_t ie; 941 uint32_t comp[5]; 942 uint32_t mask[5]; 943 }; 944 945 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 946 { 947 /* XXX: TODO */ 948 return 0; 949 } 950 951 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 952 { 953 /* XXX: TODO */ 954 } 955 956 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 957 { 958 uint32_t mask; 959 int i; 960 961 mask = 0x80000000; 962 for (i = 0; i < 5; i++) { 963 if (gpt->oe & mask) { 964 /* Output is enabled */ 965 if (ppc4xx_gpt_compare(gpt, i)) { 966 /* Comparison is OK */ 967 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 968 } else { 969 /* Comparison is KO */ 970 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 971 } 972 } 973 mask = mask >> 1; 974 } 975 } 976 977 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 978 { 979 uint32_t mask; 980 int i; 981 982 mask = 0x00008000; 983 for (i = 0; i < 5; i++) { 984 if (gpt->is & gpt->im & mask) 985 qemu_irq_raise(gpt->irqs[i]); 986 else 987 qemu_irq_lower(gpt->irqs[i]); 988 mask = mask >> 1; 989 } 990 } 991 992 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 993 { 994 /* XXX: TODO */ 995 } 996 997 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 998 { 999 ppc4xx_gpt_t *gpt = opaque; 1000 uint32_t ret; 1001 int idx; 1002 1003 trace_ppc4xx_gpt_read(addr, size); 1004 1005 switch (addr) { 1006 case 0x00: 1007 /* Time base counter */ 1008 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1009 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1010 break; 1011 case 0x10: 1012 /* Output enable */ 1013 ret = gpt->oe; 1014 break; 1015 case 0x14: 1016 /* Output level */ 1017 ret = gpt->ol; 1018 break; 1019 case 0x18: 1020 /* Interrupt mask */ 1021 ret = gpt->im; 1022 break; 1023 case 0x1C: 1024 case 0x20: 1025 /* Interrupt status */ 1026 ret = gpt->is; 1027 break; 1028 case 0x24: 1029 /* Interrupt enable */ 1030 ret = gpt->ie; 1031 break; 1032 case 0x80 ... 0x90: 1033 /* Compare timer */ 1034 idx = (addr - 0x80) >> 2; 1035 ret = gpt->comp[idx]; 1036 break; 1037 case 0xC0 ... 0xD0: 1038 /* Compare mask */ 1039 idx = (addr - 0xC0) >> 2; 1040 ret = gpt->mask[idx]; 1041 break; 1042 default: 1043 ret = -1; 1044 break; 1045 } 1046 1047 return ret; 1048 } 1049 1050 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1051 unsigned size) 1052 { 1053 ppc4xx_gpt_t *gpt = opaque; 1054 int idx; 1055 1056 trace_ppc4xx_gpt_write(addr, size, value); 1057 1058 switch (addr) { 1059 case 0x00: 1060 /* Time base counter */ 1061 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1062 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1063 ppc4xx_gpt_compute_timer(gpt); 1064 break; 1065 case 0x10: 1066 /* Output enable */ 1067 gpt->oe = value & 0xF8000000; 1068 ppc4xx_gpt_set_outputs(gpt); 1069 break; 1070 case 0x14: 1071 /* Output level */ 1072 gpt->ol = value & 0xF8000000; 1073 ppc4xx_gpt_set_outputs(gpt); 1074 break; 1075 case 0x18: 1076 /* Interrupt mask */ 1077 gpt->im = value & 0x0000F800; 1078 break; 1079 case 0x1C: 1080 /* Interrupt status set */ 1081 gpt->is |= value & 0x0000F800; 1082 ppc4xx_gpt_set_irqs(gpt); 1083 break; 1084 case 0x20: 1085 /* Interrupt status clear */ 1086 gpt->is &= ~(value & 0x0000F800); 1087 ppc4xx_gpt_set_irqs(gpt); 1088 break; 1089 case 0x24: 1090 /* Interrupt enable */ 1091 gpt->ie = value & 0x0000F800; 1092 ppc4xx_gpt_set_irqs(gpt); 1093 break; 1094 case 0x80 ... 0x90: 1095 /* Compare timer */ 1096 idx = (addr - 0x80) >> 2; 1097 gpt->comp[idx] = value & 0xF8000000; 1098 ppc4xx_gpt_compute_timer(gpt); 1099 break; 1100 case 0xC0 ... 0xD0: 1101 /* Compare mask */ 1102 idx = (addr - 0xC0) >> 2; 1103 gpt->mask[idx] = value & 0xF8000000; 1104 ppc4xx_gpt_compute_timer(gpt); 1105 break; 1106 } 1107 } 1108 1109 static const MemoryRegionOps gpt_ops = { 1110 .read = ppc4xx_gpt_read, 1111 .write = ppc4xx_gpt_write, 1112 .valid.min_access_size = 4, 1113 .valid.max_access_size = 4, 1114 .endianness = DEVICE_NATIVE_ENDIAN, 1115 }; 1116 1117 static void ppc4xx_gpt_cb (void *opaque) 1118 { 1119 ppc4xx_gpt_t *gpt; 1120 1121 gpt = opaque; 1122 ppc4xx_gpt_set_irqs(gpt); 1123 ppc4xx_gpt_set_outputs(gpt); 1124 ppc4xx_gpt_compute_timer(gpt); 1125 } 1126 1127 static void ppc4xx_gpt_reset (void *opaque) 1128 { 1129 ppc4xx_gpt_t *gpt; 1130 int i; 1131 1132 gpt = opaque; 1133 timer_del(gpt->timer); 1134 gpt->oe = 0x00000000; 1135 gpt->ol = 0x00000000; 1136 gpt->im = 0x00000000; 1137 gpt->is = 0x00000000; 1138 gpt->ie = 0x00000000; 1139 for (i = 0; i < 5; i++) { 1140 gpt->comp[i] = 0x00000000; 1141 gpt->mask[i] = 0x00000000; 1142 } 1143 } 1144 1145 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1146 { 1147 ppc4xx_gpt_t *gpt; 1148 int i; 1149 1150 trace_ppc4xx_gpt_init(base); 1151 1152 gpt = g_new0(ppc4xx_gpt_t, 1); 1153 for (i = 0; i < 5; i++) { 1154 gpt->irqs[i] = irqs[i]; 1155 } 1156 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1157 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1158 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1159 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1160 } 1161 1162 /*****************************************************************************/ 1163 /* PowerPC 405EP */ 1164 /* CPU control */ 1165 enum { 1166 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1167 PPC405EP_CPC0_BOOT = 0x0F1, 1168 PPC405EP_CPC0_EPCTL = 0x0F3, 1169 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1170 PPC405EP_CPC0_UCR = 0x0F5, 1171 PPC405EP_CPC0_SRR = 0x0F6, 1172 PPC405EP_CPC0_JTAGID = 0x0F7, 1173 PPC405EP_CPC0_PCI = 0x0F9, 1174 #if 0 1175 PPC405EP_CPC0_ER = xxx, 1176 PPC405EP_CPC0_FR = xxx, 1177 PPC405EP_CPC0_SR = xxx, 1178 #endif 1179 }; 1180 1181 enum { 1182 PPC405EP_CPU_CLK = 0, 1183 PPC405EP_PLB_CLK = 1, 1184 PPC405EP_OPB_CLK = 2, 1185 PPC405EP_EBC_CLK = 3, 1186 PPC405EP_MAL_CLK = 4, 1187 PPC405EP_PCI_CLK = 5, 1188 PPC405EP_UART0_CLK = 6, 1189 PPC405EP_UART1_CLK = 7, 1190 PPC405EP_CLK_NB = 8, 1191 }; 1192 1193 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1194 struct ppc405ep_cpc_t { 1195 uint32_t sysclk; 1196 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1197 uint32_t boot; 1198 uint32_t epctl; 1199 uint32_t pllmr[2]; 1200 uint32_t ucr; 1201 uint32_t srr; 1202 uint32_t jtagid; 1203 uint32_t pci; 1204 /* Clock and power management */ 1205 uint32_t er; 1206 uint32_t fr; 1207 uint32_t sr; 1208 }; 1209 1210 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1211 { 1212 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1213 uint32_t UART0_clk, UART1_clk; 1214 uint64_t VCO_out, PLL_out; 1215 int M, D; 1216 1217 VCO_out = 0; 1218 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1219 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1220 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); 1221 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1222 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); 1223 VCO_out = (uint64_t)cpc->sysclk * M * D; 1224 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1225 /* Error - unlock the PLL */ 1226 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", 1227 VCO_out); 1228 #if 0 1229 cpc->pllmr[1] &= ~0x80000000; 1230 goto pll_bypass; 1231 #endif 1232 } 1233 PLL_out = VCO_out / D; 1234 /* Pretend the PLL is locked */ 1235 cpc->boot |= 0x00000001; 1236 } else { 1237 #if 0 1238 pll_bypass: 1239 #endif 1240 PLL_out = cpc->sysclk; 1241 if (cpc->pllmr[1] & 0x40000000) { 1242 /* Pretend the PLL is not locked */ 1243 cpc->boot &= ~0x00000001; 1244 } 1245 } 1246 /* Now, compute all other clocks */ 1247 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1248 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); 1249 CPU_clk = PLL_out / D; 1250 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1251 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); 1252 PLB_clk = CPU_clk / D; 1253 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1254 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); 1255 OPB_clk = PLB_clk / D; 1256 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1257 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); 1258 EBC_clk = PLB_clk / D; 1259 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1260 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); 1261 MAL_clk = PLB_clk / D; 1262 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1263 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); 1264 PCI_clk = PLB_clk / D; 1265 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1266 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); 1267 UART0_clk = PLL_out / D; 1268 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1269 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); 1270 UART1_clk = PLL_out / D; 1271 1272 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { 1273 g_autofree char *trace = g_strdup_printf( 1274 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1275 " PLL out %" PRIu64 " Hz\n" 1276 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1277 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1278 " UART1 %" PRIu32 "\n", 1279 cpc->sysclk, VCO_out, PLL_out, 1280 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1281 UART0_clk, UART1_clk); 1282 trace_ppc405ep_clocks_setup(trace); 1283 } 1284 1285 /* Setup CPU clocks */ 1286 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1287 /* Setup PLB clock */ 1288 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1289 /* Setup OPB clock */ 1290 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1291 /* Setup external clock */ 1292 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1293 /* Setup MAL clock */ 1294 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1295 /* Setup PCI clock */ 1296 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1297 /* Setup UART0 clock */ 1298 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1299 /* Setup UART1 clock */ 1300 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1301 } 1302 1303 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1304 { 1305 ppc405ep_cpc_t *cpc; 1306 uint32_t ret; 1307 1308 cpc = opaque; 1309 switch (dcrn) { 1310 case PPC405EP_CPC0_BOOT: 1311 ret = cpc->boot; 1312 break; 1313 case PPC405EP_CPC0_EPCTL: 1314 ret = cpc->epctl; 1315 break; 1316 case PPC405EP_CPC0_PLLMR0: 1317 ret = cpc->pllmr[0]; 1318 break; 1319 case PPC405EP_CPC0_PLLMR1: 1320 ret = cpc->pllmr[1]; 1321 break; 1322 case PPC405EP_CPC0_UCR: 1323 ret = cpc->ucr; 1324 break; 1325 case PPC405EP_CPC0_SRR: 1326 ret = cpc->srr; 1327 break; 1328 case PPC405EP_CPC0_JTAGID: 1329 ret = cpc->jtagid; 1330 break; 1331 case PPC405EP_CPC0_PCI: 1332 ret = cpc->pci; 1333 break; 1334 default: 1335 /* Avoid gcc warning */ 1336 ret = 0; 1337 break; 1338 } 1339 1340 return ret; 1341 } 1342 1343 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1344 { 1345 ppc405ep_cpc_t *cpc; 1346 1347 cpc = opaque; 1348 switch (dcrn) { 1349 case PPC405EP_CPC0_BOOT: 1350 /* Read-only register */ 1351 break; 1352 case PPC405EP_CPC0_EPCTL: 1353 /* Don't care for now */ 1354 cpc->epctl = val & 0xC00000F3; 1355 break; 1356 case PPC405EP_CPC0_PLLMR0: 1357 cpc->pllmr[0] = val & 0x00633333; 1358 ppc405ep_compute_clocks(cpc); 1359 break; 1360 case PPC405EP_CPC0_PLLMR1: 1361 cpc->pllmr[1] = val & 0xC0F73FFF; 1362 ppc405ep_compute_clocks(cpc); 1363 break; 1364 case PPC405EP_CPC0_UCR: 1365 /* UART control - don't care for now */ 1366 cpc->ucr = val & 0x003F7F7F; 1367 break; 1368 case PPC405EP_CPC0_SRR: 1369 cpc->srr = val; 1370 break; 1371 case PPC405EP_CPC0_JTAGID: 1372 /* Read-only */ 1373 break; 1374 case PPC405EP_CPC0_PCI: 1375 cpc->pci = val; 1376 break; 1377 } 1378 } 1379 1380 static void ppc405ep_cpc_reset (void *opaque) 1381 { 1382 ppc405ep_cpc_t *cpc = opaque; 1383 1384 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1385 cpc->epctl = 0x00000000; 1386 cpc->pllmr[0] = 0x00021002; 1387 cpc->pllmr[1] = 0x80a552be; 1388 cpc->ucr = 0x00004646; 1389 cpc->srr = 0x00040000; 1390 cpc->pci = 0x00000000; 1391 cpc->er = 0x00000000; 1392 cpc->fr = 0x00000000; 1393 cpc->sr = 0x00000000; 1394 ppc405ep_compute_clocks(cpc); 1395 } 1396 1397 /* XXX: sysclk should be between 25 and 100 MHz */ 1398 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1399 uint32_t sysclk) 1400 { 1401 ppc405ep_cpc_t *cpc; 1402 1403 cpc = g_new0(ppc405ep_cpc_t, 1); 1404 memcpy(cpc->clk_setup, clk_setup, 1405 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1406 cpc->jtagid = 0x20267049; 1407 cpc->sysclk = sysclk; 1408 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1409 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1410 &dcr_read_epcpc, &dcr_write_epcpc); 1411 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1412 &dcr_read_epcpc, &dcr_write_epcpc); 1413 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1414 &dcr_read_epcpc, &dcr_write_epcpc); 1415 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1416 &dcr_read_epcpc, &dcr_write_epcpc); 1417 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1418 &dcr_read_epcpc, &dcr_write_epcpc); 1419 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1420 &dcr_read_epcpc, &dcr_write_epcpc); 1421 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1422 &dcr_read_epcpc, &dcr_write_epcpc); 1423 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1424 &dcr_read_epcpc, &dcr_write_epcpc); 1425 #if 0 1426 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1427 &dcr_read_epcpc, &dcr_write_epcpc); 1428 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1429 &dcr_read_epcpc, &dcr_write_epcpc); 1430 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1431 &dcr_read_epcpc, &dcr_write_epcpc); 1432 #endif 1433 } 1434 1435 PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, 1436 MemoryRegion ram_memories[2], 1437 hwaddr ram_bases[2], 1438 hwaddr ram_sizes[2], 1439 uint32_t sysclk, DeviceState **uicdevp, 1440 int do_init) 1441 { 1442 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1443 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1444 PowerPCCPU *cpu; 1445 CPUPPCState *env; 1446 DeviceState *uicdev; 1447 SysBusDevice *uicsbd; 1448 1449 memset(clk_setup, 0, sizeof(clk_setup)); 1450 /* init CPUs */ 1451 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1452 &clk_setup[PPC405EP_CPU_CLK], 1453 &tlb_clk_setup, sysclk); 1454 env = &cpu->env; 1455 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1456 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1457 /* Internal devices init */ 1458 /* Memory mapped devices registers */ 1459 /* PLB arbitrer */ 1460 ppc4xx_plb_init(env); 1461 /* PLB to OPB bridge */ 1462 ppc4xx_pob_init(env); 1463 /* OBP arbitrer */ 1464 ppc4xx_opba_init(0xef600600); 1465 /* Universal interrupt controller */ 1466 uicdev = qdev_new(TYPE_PPC_UIC); 1467 uicsbd = SYS_BUS_DEVICE(uicdev); 1468 1469 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 1470 &error_fatal); 1471 sysbus_realize_and_unref(uicsbd, &error_fatal); 1472 1473 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 1474 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 1475 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 1476 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 1477 1478 *uicdevp = uicdev; 1479 1480 /* SDRAM controller */ 1481 /* XXX 405EP has no ECC interrupt */ 1482 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, 1483 ram_bases, ram_sizes, do_init); 1484 /* External bus controller */ 1485 ppc405_ebc_init(env); 1486 /* DMA controller */ 1487 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); 1488 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); 1489 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); 1490 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); 1491 ppc405_dma_init(env, dma_irqs); 1492 /* IIC controller */ 1493 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1494 qdev_get_gpio_in(uicdev, 2)); 1495 /* GPIO */ 1496 ppc405_gpio_init(0xef600700); 1497 /* Serial ports */ 1498 if (serial_hd(0) != NULL) { 1499 serial_mm_init(address_space_mem, 0xef600300, 0, 1500 qdev_get_gpio_in(uicdev, 0), 1501 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1502 DEVICE_BIG_ENDIAN); 1503 } 1504 if (serial_hd(1) != NULL) { 1505 serial_mm_init(address_space_mem, 0xef600400, 0, 1506 qdev_get_gpio_in(uicdev, 1), 1507 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1508 DEVICE_BIG_ENDIAN); 1509 } 1510 /* OCM */ 1511 ppc405_ocm_init(env); 1512 /* GPT */ 1513 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); 1514 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); 1515 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); 1516 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); 1517 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); 1518 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1519 /* PCI */ 1520 /* Uses UIC IRQs 3, 16, 18 */ 1521 /* MAL */ 1522 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); 1523 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); 1524 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); 1525 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); 1526 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1527 /* Ethernet */ 1528 /* Uses UIC IRQs 9, 15, 17 */ 1529 /* CPU control */ 1530 ppc405ep_cpc_init(env, clk_setup, sysclk); 1531 1532 return cpu; 1533 } 1534 1535 static void ppc405_soc_realize(DeviceState *dev, Error **errp) 1536 { 1537 Ppc405SoCState *s = PPC405_SOC(dev); 1538 1539 /* Initialize only one bank */ 1540 s->ram_bases[0] = 0; 1541 s->ram_sizes[0] = s->ram_size; 1542 memory_region_init_alias(&s->ram_banks[0], OBJECT(s), 1543 "ppc405.sdram0", s->dram_mr, 1544 s->ram_bases[0], s->ram_sizes[0]); 1545 } 1546 1547 static Property ppc405_soc_properties[] = { 1548 DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, 1549 MemoryRegion *), 1550 DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), 1551 DEFINE_PROP_END_OF_LIST(), 1552 }; 1553 1554 static void ppc405_soc_class_init(ObjectClass *oc, void *data) 1555 { 1556 DeviceClass *dc = DEVICE_CLASS(oc); 1557 1558 dc->realize = ppc405_soc_realize; 1559 dc->user_creatable = false; 1560 device_class_set_props(dc, ppc405_soc_properties); 1561 } 1562 1563 static const TypeInfo ppc405_types[] = { 1564 { 1565 .name = TYPE_PPC405_SOC, 1566 .parent = TYPE_DEVICE, 1567 .instance_size = sizeof(Ppc405SoCState), 1568 .class_init = ppc405_soc_class_init, 1569 } 1570 }; 1571 1572 DEFINE_TYPES(ppc405_types) 1573