1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/boards.h" 32 #include "hw/i2c/ppc4xx_i2c.h" 33 #include "ppc405.h" 34 #include "hw/char/serial.h" 35 #include "qemu/timer.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/sysemu.h" 38 #include "qemu/log.h" 39 #include "exec/address-spaces.h" 40 41 //#define DEBUG_OPBA 42 //#define DEBUG_SDRAM 43 //#define DEBUG_GPIO 44 //#define DEBUG_SERIAL 45 //#define DEBUG_OCM 46 //#define DEBUG_GPT 47 //#define DEBUG_CLOCKS 48 //#define DEBUG_CLOCKS_LL 49 50 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 51 uint32_t flags) 52 { 53 CPUState *cs = env_cpu(env); 54 ram_addr_t bdloc; 55 int i, n; 56 57 /* We put the bd structure at the top of memory */ 58 if (bd->bi_memsize >= 0x01000000UL) 59 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 60 else 61 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 62 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 63 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 64 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 65 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 66 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 67 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 68 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 69 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 70 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 71 for (i = 0; i < 6; i++) { 72 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 73 } 74 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 75 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 76 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 77 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 78 for (i = 0; i < 4; i++) { 79 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 80 } 81 for (i = 0; i < 32; i++) { 82 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 83 } 84 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 85 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 86 for (i = 0; i < 6; i++) { 87 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 88 } 89 n = 0x6A; 90 if (flags & 0x00000001) { 91 for (i = 0; i < 6; i++) 92 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 93 } 94 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 95 n += 4; 96 for (i = 0; i < 2; i++) { 97 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 98 n += 4; 99 } 100 101 return bdloc; 102 } 103 104 /*****************************************************************************/ 105 /* Shared peripherals */ 106 107 /*****************************************************************************/ 108 /* Peripheral local bus arbitrer */ 109 enum { 110 PLB3A0_ACR = 0x077, 111 PLB4A0_ACR = 0x081, 112 PLB0_BESR = 0x084, 113 PLB0_BEAR = 0x086, 114 PLB0_ACR = 0x087, 115 PLB4A1_ACR = 0x089, 116 }; 117 118 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 119 struct ppc4xx_plb_t { 120 uint32_t acr; 121 uint32_t bear; 122 uint32_t besr; 123 }; 124 125 static uint32_t dcr_read_plb (void *opaque, int dcrn) 126 { 127 ppc4xx_plb_t *plb; 128 uint32_t ret; 129 130 plb = opaque; 131 switch (dcrn) { 132 case PLB0_ACR: 133 ret = plb->acr; 134 break; 135 case PLB0_BEAR: 136 ret = plb->bear; 137 break; 138 case PLB0_BESR: 139 ret = plb->besr; 140 break; 141 default: 142 /* Avoid gcc warning */ 143 ret = 0; 144 break; 145 } 146 147 return ret; 148 } 149 150 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 151 { 152 ppc4xx_plb_t *plb; 153 154 plb = opaque; 155 switch (dcrn) { 156 case PLB0_ACR: 157 /* We don't care about the actual parameters written as 158 * we don't manage any priorities on the bus 159 */ 160 plb->acr = val & 0xF8000000; 161 break; 162 case PLB0_BEAR: 163 /* Read only */ 164 break; 165 case PLB0_BESR: 166 /* Write-clear */ 167 plb->besr &= ~val; 168 break; 169 } 170 } 171 172 static void ppc4xx_plb_reset (void *opaque) 173 { 174 ppc4xx_plb_t *plb; 175 176 plb = opaque; 177 plb->acr = 0x00000000; 178 plb->bear = 0x00000000; 179 plb->besr = 0x00000000; 180 } 181 182 void ppc4xx_plb_init(CPUPPCState *env) 183 { 184 ppc4xx_plb_t *plb; 185 186 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 187 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 188 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 189 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 191 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 192 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 193 qemu_register_reset(ppc4xx_plb_reset, plb); 194 } 195 196 /*****************************************************************************/ 197 /* PLB to OPB bridge */ 198 enum { 199 POB0_BESR0 = 0x0A0, 200 POB0_BESR1 = 0x0A2, 201 POB0_BEAR = 0x0A4, 202 }; 203 204 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 205 struct ppc4xx_pob_t { 206 uint32_t bear; 207 uint32_t besr0; 208 uint32_t besr1; 209 }; 210 211 static uint32_t dcr_read_pob (void *opaque, int dcrn) 212 { 213 ppc4xx_pob_t *pob; 214 uint32_t ret; 215 216 pob = opaque; 217 switch (dcrn) { 218 case POB0_BEAR: 219 ret = pob->bear; 220 break; 221 case POB0_BESR0: 222 ret = pob->besr0; 223 break; 224 case POB0_BESR1: 225 ret = pob->besr1; 226 break; 227 default: 228 /* Avoid gcc warning */ 229 ret = 0; 230 break; 231 } 232 233 return ret; 234 } 235 236 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 237 { 238 ppc4xx_pob_t *pob; 239 240 pob = opaque; 241 switch (dcrn) { 242 case POB0_BEAR: 243 /* Read only */ 244 break; 245 case POB0_BESR0: 246 /* Write-clear */ 247 pob->besr0 &= ~val; 248 break; 249 case POB0_BESR1: 250 /* Write-clear */ 251 pob->besr1 &= ~val; 252 break; 253 } 254 } 255 256 static void ppc4xx_pob_reset (void *opaque) 257 { 258 ppc4xx_pob_t *pob; 259 260 pob = opaque; 261 /* No error */ 262 pob->bear = 0x00000000; 263 pob->besr0 = 0x0000000; 264 pob->besr1 = 0x0000000; 265 } 266 267 static void ppc4xx_pob_init(CPUPPCState *env) 268 { 269 ppc4xx_pob_t *pob; 270 271 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 272 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 273 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 274 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 275 qemu_register_reset(ppc4xx_pob_reset, pob); 276 } 277 278 /*****************************************************************************/ 279 /* OPB arbitrer */ 280 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 281 struct ppc4xx_opba_t { 282 MemoryRegion io; 283 uint8_t cr; 284 uint8_t pr; 285 }; 286 287 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 288 { 289 ppc4xx_opba_t *opba; 290 uint32_t ret; 291 292 #ifdef DEBUG_OPBA 293 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 294 #endif 295 opba = opaque; 296 switch (addr) { 297 case 0x00: 298 ret = opba->cr; 299 break; 300 case 0x01: 301 ret = opba->pr; 302 break; 303 default: 304 ret = 0x00; 305 break; 306 } 307 308 return ret; 309 } 310 311 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 312 unsigned size) 313 { 314 ppc4xx_opba_t *opba; 315 316 #ifdef DEBUG_OPBA 317 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 318 value); 319 #endif 320 opba = opaque; 321 switch (addr) { 322 case 0x00: 323 opba->cr = value & 0xF8; 324 break; 325 case 0x01: 326 opba->pr = value & 0xFF; 327 break; 328 default: 329 break; 330 } 331 } 332 static const MemoryRegionOps opba_ops = { 333 .read = opba_readb, 334 .write = opba_writeb, 335 .impl.min_access_size = 1, 336 .impl.max_access_size = 1, 337 .valid.min_access_size = 1, 338 .valid.max_access_size = 4, 339 .endianness = DEVICE_BIG_ENDIAN, 340 }; 341 342 static void ppc4xx_opba_reset (void *opaque) 343 { 344 ppc4xx_opba_t *opba; 345 346 opba = opaque; 347 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 348 opba->pr = 0x11; 349 } 350 351 static void ppc4xx_opba_init(hwaddr base) 352 { 353 ppc4xx_opba_t *opba; 354 355 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 356 #ifdef DEBUG_OPBA 357 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 358 #endif 359 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 360 memory_region_add_subregion(get_system_memory(), base, &opba->io); 361 qemu_register_reset(ppc4xx_opba_reset, opba); 362 } 363 364 /*****************************************************************************/ 365 /* Code decompression controller */ 366 /* XXX: TODO */ 367 368 /*****************************************************************************/ 369 /* Peripheral controller */ 370 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 371 struct ppc4xx_ebc_t { 372 uint32_t addr; 373 uint32_t bcr[8]; 374 uint32_t bap[8]; 375 uint32_t bear; 376 uint32_t besr0; 377 uint32_t besr1; 378 uint32_t cfg; 379 }; 380 381 enum { 382 EBC0_CFGADDR = 0x012, 383 EBC0_CFGDATA = 0x013, 384 }; 385 386 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 387 { 388 ppc4xx_ebc_t *ebc; 389 uint32_t ret; 390 391 ebc = opaque; 392 switch (dcrn) { 393 case EBC0_CFGADDR: 394 ret = ebc->addr; 395 break; 396 case EBC0_CFGDATA: 397 switch (ebc->addr) { 398 case 0x00: /* B0CR */ 399 ret = ebc->bcr[0]; 400 break; 401 case 0x01: /* B1CR */ 402 ret = ebc->bcr[1]; 403 break; 404 case 0x02: /* B2CR */ 405 ret = ebc->bcr[2]; 406 break; 407 case 0x03: /* B3CR */ 408 ret = ebc->bcr[3]; 409 break; 410 case 0x04: /* B4CR */ 411 ret = ebc->bcr[4]; 412 break; 413 case 0x05: /* B5CR */ 414 ret = ebc->bcr[5]; 415 break; 416 case 0x06: /* B6CR */ 417 ret = ebc->bcr[6]; 418 break; 419 case 0x07: /* B7CR */ 420 ret = ebc->bcr[7]; 421 break; 422 case 0x10: /* B0AP */ 423 ret = ebc->bap[0]; 424 break; 425 case 0x11: /* B1AP */ 426 ret = ebc->bap[1]; 427 break; 428 case 0x12: /* B2AP */ 429 ret = ebc->bap[2]; 430 break; 431 case 0x13: /* B3AP */ 432 ret = ebc->bap[3]; 433 break; 434 case 0x14: /* B4AP */ 435 ret = ebc->bap[4]; 436 break; 437 case 0x15: /* B5AP */ 438 ret = ebc->bap[5]; 439 break; 440 case 0x16: /* B6AP */ 441 ret = ebc->bap[6]; 442 break; 443 case 0x17: /* B7AP */ 444 ret = ebc->bap[7]; 445 break; 446 case 0x20: /* BEAR */ 447 ret = ebc->bear; 448 break; 449 case 0x21: /* BESR0 */ 450 ret = ebc->besr0; 451 break; 452 case 0x22: /* BESR1 */ 453 ret = ebc->besr1; 454 break; 455 case 0x23: /* CFG */ 456 ret = ebc->cfg; 457 break; 458 default: 459 ret = 0x00000000; 460 break; 461 } 462 break; 463 default: 464 ret = 0x00000000; 465 break; 466 } 467 468 return ret; 469 } 470 471 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 472 { 473 ppc4xx_ebc_t *ebc; 474 475 ebc = opaque; 476 switch (dcrn) { 477 case EBC0_CFGADDR: 478 ebc->addr = val; 479 break; 480 case EBC0_CFGDATA: 481 switch (ebc->addr) { 482 case 0x00: /* B0CR */ 483 break; 484 case 0x01: /* B1CR */ 485 break; 486 case 0x02: /* B2CR */ 487 break; 488 case 0x03: /* B3CR */ 489 break; 490 case 0x04: /* B4CR */ 491 break; 492 case 0x05: /* B5CR */ 493 break; 494 case 0x06: /* B6CR */ 495 break; 496 case 0x07: /* B7CR */ 497 break; 498 case 0x10: /* B0AP */ 499 break; 500 case 0x11: /* B1AP */ 501 break; 502 case 0x12: /* B2AP */ 503 break; 504 case 0x13: /* B3AP */ 505 break; 506 case 0x14: /* B4AP */ 507 break; 508 case 0x15: /* B5AP */ 509 break; 510 case 0x16: /* B6AP */ 511 break; 512 case 0x17: /* B7AP */ 513 break; 514 case 0x20: /* BEAR */ 515 break; 516 case 0x21: /* BESR0 */ 517 break; 518 case 0x22: /* BESR1 */ 519 break; 520 case 0x23: /* CFG */ 521 break; 522 default: 523 break; 524 } 525 break; 526 default: 527 break; 528 } 529 } 530 531 static void ebc_reset (void *opaque) 532 { 533 ppc4xx_ebc_t *ebc; 534 int i; 535 536 ebc = opaque; 537 ebc->addr = 0x00000000; 538 ebc->bap[0] = 0x7F8FFE80; 539 ebc->bcr[0] = 0xFFE28000; 540 for (i = 0; i < 8; i++) { 541 ebc->bap[i] = 0x00000000; 542 ebc->bcr[i] = 0x00000000; 543 } 544 ebc->besr0 = 0x00000000; 545 ebc->besr1 = 0x00000000; 546 ebc->cfg = 0x80400000; 547 } 548 549 void ppc405_ebc_init(CPUPPCState *env) 550 { 551 ppc4xx_ebc_t *ebc; 552 553 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 554 qemu_register_reset(&ebc_reset, ebc); 555 ppc_dcr_register(env, EBC0_CFGADDR, 556 ebc, &dcr_read_ebc, &dcr_write_ebc); 557 ppc_dcr_register(env, EBC0_CFGDATA, 558 ebc, &dcr_read_ebc, &dcr_write_ebc); 559 } 560 561 /*****************************************************************************/ 562 /* DMA controller */ 563 enum { 564 DMA0_CR0 = 0x100, 565 DMA0_CT0 = 0x101, 566 DMA0_DA0 = 0x102, 567 DMA0_SA0 = 0x103, 568 DMA0_SG0 = 0x104, 569 DMA0_CR1 = 0x108, 570 DMA0_CT1 = 0x109, 571 DMA0_DA1 = 0x10A, 572 DMA0_SA1 = 0x10B, 573 DMA0_SG1 = 0x10C, 574 DMA0_CR2 = 0x110, 575 DMA0_CT2 = 0x111, 576 DMA0_DA2 = 0x112, 577 DMA0_SA2 = 0x113, 578 DMA0_SG2 = 0x114, 579 DMA0_CR3 = 0x118, 580 DMA0_CT3 = 0x119, 581 DMA0_DA3 = 0x11A, 582 DMA0_SA3 = 0x11B, 583 DMA0_SG3 = 0x11C, 584 DMA0_SR = 0x120, 585 DMA0_SGC = 0x123, 586 DMA0_SLP = 0x125, 587 DMA0_POL = 0x126, 588 }; 589 590 typedef struct ppc405_dma_t ppc405_dma_t; 591 struct ppc405_dma_t { 592 qemu_irq irqs[4]; 593 uint32_t cr[4]; 594 uint32_t ct[4]; 595 uint32_t da[4]; 596 uint32_t sa[4]; 597 uint32_t sg[4]; 598 uint32_t sr; 599 uint32_t sgc; 600 uint32_t slp; 601 uint32_t pol; 602 }; 603 604 static uint32_t dcr_read_dma (void *opaque, int dcrn) 605 { 606 return 0; 607 } 608 609 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 610 { 611 } 612 613 static void ppc405_dma_reset (void *opaque) 614 { 615 ppc405_dma_t *dma; 616 int i; 617 618 dma = opaque; 619 for (i = 0; i < 4; i++) { 620 dma->cr[i] = 0x00000000; 621 dma->ct[i] = 0x00000000; 622 dma->da[i] = 0x00000000; 623 dma->sa[i] = 0x00000000; 624 dma->sg[i] = 0x00000000; 625 } 626 dma->sr = 0x00000000; 627 dma->sgc = 0x00000000; 628 dma->slp = 0x7C000000; 629 dma->pol = 0x00000000; 630 } 631 632 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 633 { 634 ppc405_dma_t *dma; 635 636 dma = g_malloc0(sizeof(ppc405_dma_t)); 637 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 638 qemu_register_reset(&ppc405_dma_reset, dma); 639 ppc_dcr_register(env, DMA0_CR0, 640 dma, &dcr_read_dma, &dcr_write_dma); 641 ppc_dcr_register(env, DMA0_CT0, 642 dma, &dcr_read_dma, &dcr_write_dma); 643 ppc_dcr_register(env, DMA0_DA0, 644 dma, &dcr_read_dma, &dcr_write_dma); 645 ppc_dcr_register(env, DMA0_SA0, 646 dma, &dcr_read_dma, &dcr_write_dma); 647 ppc_dcr_register(env, DMA0_SG0, 648 dma, &dcr_read_dma, &dcr_write_dma); 649 ppc_dcr_register(env, DMA0_CR1, 650 dma, &dcr_read_dma, &dcr_write_dma); 651 ppc_dcr_register(env, DMA0_CT1, 652 dma, &dcr_read_dma, &dcr_write_dma); 653 ppc_dcr_register(env, DMA0_DA1, 654 dma, &dcr_read_dma, &dcr_write_dma); 655 ppc_dcr_register(env, DMA0_SA1, 656 dma, &dcr_read_dma, &dcr_write_dma); 657 ppc_dcr_register(env, DMA0_SG1, 658 dma, &dcr_read_dma, &dcr_write_dma); 659 ppc_dcr_register(env, DMA0_CR2, 660 dma, &dcr_read_dma, &dcr_write_dma); 661 ppc_dcr_register(env, DMA0_CT2, 662 dma, &dcr_read_dma, &dcr_write_dma); 663 ppc_dcr_register(env, DMA0_DA2, 664 dma, &dcr_read_dma, &dcr_write_dma); 665 ppc_dcr_register(env, DMA0_SA2, 666 dma, &dcr_read_dma, &dcr_write_dma); 667 ppc_dcr_register(env, DMA0_SG2, 668 dma, &dcr_read_dma, &dcr_write_dma); 669 ppc_dcr_register(env, DMA0_CR3, 670 dma, &dcr_read_dma, &dcr_write_dma); 671 ppc_dcr_register(env, DMA0_CT3, 672 dma, &dcr_read_dma, &dcr_write_dma); 673 ppc_dcr_register(env, DMA0_DA3, 674 dma, &dcr_read_dma, &dcr_write_dma); 675 ppc_dcr_register(env, DMA0_SA3, 676 dma, &dcr_read_dma, &dcr_write_dma); 677 ppc_dcr_register(env, DMA0_SG3, 678 dma, &dcr_read_dma, &dcr_write_dma); 679 ppc_dcr_register(env, DMA0_SR, 680 dma, &dcr_read_dma, &dcr_write_dma); 681 ppc_dcr_register(env, DMA0_SGC, 682 dma, &dcr_read_dma, &dcr_write_dma); 683 ppc_dcr_register(env, DMA0_SLP, 684 dma, &dcr_read_dma, &dcr_write_dma); 685 ppc_dcr_register(env, DMA0_POL, 686 dma, &dcr_read_dma, &dcr_write_dma); 687 } 688 689 /*****************************************************************************/ 690 /* GPIO */ 691 typedef struct ppc405_gpio_t ppc405_gpio_t; 692 struct ppc405_gpio_t { 693 MemoryRegion io; 694 uint32_t or; 695 uint32_t tcr; 696 uint32_t osrh; 697 uint32_t osrl; 698 uint32_t tsrh; 699 uint32_t tsrl; 700 uint32_t odr; 701 uint32_t ir; 702 uint32_t rr1; 703 uint32_t isr1h; 704 uint32_t isr1l; 705 }; 706 707 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 708 { 709 #ifdef DEBUG_GPIO 710 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); 711 #endif 712 713 return 0; 714 } 715 716 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 717 unsigned size) 718 { 719 #ifdef DEBUG_GPIO 720 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", 721 __func__, addr, size, value); 722 #endif 723 } 724 725 static const MemoryRegionOps ppc405_gpio_ops = { 726 .read = ppc405_gpio_read, 727 .write = ppc405_gpio_write, 728 .endianness = DEVICE_NATIVE_ENDIAN, 729 }; 730 731 static void ppc405_gpio_reset (void *opaque) 732 { 733 } 734 735 static void ppc405_gpio_init(hwaddr base) 736 { 737 ppc405_gpio_t *gpio; 738 739 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 740 #ifdef DEBUG_GPIO 741 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 742 #endif 743 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 744 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 745 qemu_register_reset(&ppc405_gpio_reset, gpio); 746 } 747 748 /*****************************************************************************/ 749 /* On Chip Memory */ 750 enum { 751 OCM0_ISARC = 0x018, 752 OCM0_ISACNTL = 0x019, 753 OCM0_DSARC = 0x01A, 754 OCM0_DSACNTL = 0x01B, 755 }; 756 757 typedef struct ppc405_ocm_t ppc405_ocm_t; 758 struct ppc405_ocm_t { 759 MemoryRegion ram; 760 MemoryRegion isarc_ram; 761 MemoryRegion dsarc_ram; 762 uint32_t isarc; 763 uint32_t isacntl; 764 uint32_t dsarc; 765 uint32_t dsacntl; 766 }; 767 768 static void ocm_update_mappings (ppc405_ocm_t *ocm, 769 uint32_t isarc, uint32_t isacntl, 770 uint32_t dsarc, uint32_t dsacntl) 771 { 772 #ifdef DEBUG_OCM 773 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 774 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 775 " (%08" PRIx32 " %08" PRIx32 ")\n", 776 isarc, isacntl, dsarc, dsacntl, 777 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 778 #endif 779 if (ocm->isarc != isarc || 780 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 781 if (ocm->isacntl & 0x80000000) { 782 /* Unmap previously assigned memory region */ 783 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 784 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 785 } 786 if (isacntl & 0x80000000) { 787 /* Map new instruction memory region */ 788 #ifdef DEBUG_OCM 789 printf("OCM map ISA %08" PRIx32 "\n", isarc); 790 #endif 791 memory_region_add_subregion(get_system_memory(), isarc, 792 &ocm->isarc_ram); 793 } 794 } 795 if (ocm->dsarc != dsarc || 796 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 797 if (ocm->dsacntl & 0x80000000) { 798 /* Beware not to unmap the region we just mapped */ 799 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 800 /* Unmap previously assigned memory region */ 801 #ifdef DEBUG_OCM 802 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 803 #endif 804 memory_region_del_subregion(get_system_memory(), 805 &ocm->dsarc_ram); 806 } 807 } 808 if (dsacntl & 0x80000000) { 809 /* Beware not to remap the region we just mapped */ 810 if (!(isacntl & 0x80000000) || dsarc != isarc) { 811 /* Map new data memory region */ 812 #ifdef DEBUG_OCM 813 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 814 #endif 815 memory_region_add_subregion(get_system_memory(), dsarc, 816 &ocm->dsarc_ram); 817 } 818 } 819 } 820 } 821 822 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 823 { 824 ppc405_ocm_t *ocm; 825 uint32_t ret; 826 827 ocm = opaque; 828 switch (dcrn) { 829 case OCM0_ISARC: 830 ret = ocm->isarc; 831 break; 832 case OCM0_ISACNTL: 833 ret = ocm->isacntl; 834 break; 835 case OCM0_DSARC: 836 ret = ocm->dsarc; 837 break; 838 case OCM0_DSACNTL: 839 ret = ocm->dsacntl; 840 break; 841 default: 842 ret = 0; 843 break; 844 } 845 846 return ret; 847 } 848 849 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 850 { 851 ppc405_ocm_t *ocm; 852 uint32_t isarc, dsarc, isacntl, dsacntl; 853 854 ocm = opaque; 855 isarc = ocm->isarc; 856 dsarc = ocm->dsarc; 857 isacntl = ocm->isacntl; 858 dsacntl = ocm->dsacntl; 859 switch (dcrn) { 860 case OCM0_ISARC: 861 isarc = val & 0xFC000000; 862 break; 863 case OCM0_ISACNTL: 864 isacntl = val & 0xC0000000; 865 break; 866 case OCM0_DSARC: 867 isarc = val & 0xFC000000; 868 break; 869 case OCM0_DSACNTL: 870 isacntl = val & 0xC0000000; 871 break; 872 } 873 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 874 ocm->isarc = isarc; 875 ocm->dsarc = dsarc; 876 ocm->isacntl = isacntl; 877 ocm->dsacntl = dsacntl; 878 } 879 880 static void ocm_reset (void *opaque) 881 { 882 ppc405_ocm_t *ocm; 883 uint32_t isarc, dsarc, isacntl, dsacntl; 884 885 ocm = opaque; 886 isarc = 0x00000000; 887 isacntl = 0x00000000; 888 dsarc = 0x00000000; 889 dsacntl = 0x00000000; 890 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 891 ocm->isarc = isarc; 892 ocm->dsarc = dsarc; 893 ocm->isacntl = isacntl; 894 ocm->dsacntl = dsacntl; 895 } 896 897 static void ppc405_ocm_init(CPUPPCState *env) 898 { 899 ppc405_ocm_t *ocm; 900 901 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 902 /* XXX: Size is 4096 or 0x04000000 */ 903 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 904 &error_fatal); 905 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 906 &ocm->isarc_ram, 0, 4 * KiB); 907 qemu_register_reset(&ocm_reset, ocm); 908 ppc_dcr_register(env, OCM0_ISARC, 909 ocm, &dcr_read_ocm, &dcr_write_ocm); 910 ppc_dcr_register(env, OCM0_ISACNTL, 911 ocm, &dcr_read_ocm, &dcr_write_ocm); 912 ppc_dcr_register(env, OCM0_DSARC, 913 ocm, &dcr_read_ocm, &dcr_write_ocm); 914 ppc_dcr_register(env, OCM0_DSACNTL, 915 ocm, &dcr_read_ocm, &dcr_write_ocm); 916 } 917 918 /*****************************************************************************/ 919 /* General purpose timers */ 920 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 921 struct ppc4xx_gpt_t { 922 MemoryRegion iomem; 923 int64_t tb_offset; 924 uint32_t tb_freq; 925 QEMUTimer *timer; 926 qemu_irq irqs[5]; 927 uint32_t oe; 928 uint32_t ol; 929 uint32_t im; 930 uint32_t is; 931 uint32_t ie; 932 uint32_t comp[5]; 933 uint32_t mask[5]; 934 }; 935 936 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 937 { 938 /* XXX: TODO */ 939 return 0; 940 } 941 942 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 943 { 944 /* XXX: TODO */ 945 } 946 947 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 948 { 949 uint32_t mask; 950 int i; 951 952 mask = 0x80000000; 953 for (i = 0; i < 5; i++) { 954 if (gpt->oe & mask) { 955 /* Output is enabled */ 956 if (ppc4xx_gpt_compare(gpt, i)) { 957 /* Comparison is OK */ 958 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 959 } else { 960 /* Comparison is KO */ 961 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 962 } 963 } 964 mask = mask >> 1; 965 } 966 } 967 968 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 969 { 970 uint32_t mask; 971 int i; 972 973 mask = 0x00008000; 974 for (i = 0; i < 5; i++) { 975 if (gpt->is & gpt->im & mask) 976 qemu_irq_raise(gpt->irqs[i]); 977 else 978 qemu_irq_lower(gpt->irqs[i]); 979 mask = mask >> 1; 980 } 981 } 982 983 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 984 { 985 /* XXX: TODO */ 986 } 987 988 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 989 { 990 ppc4xx_gpt_t *gpt; 991 uint32_t ret; 992 int idx; 993 994 #ifdef DEBUG_GPT 995 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 996 #endif 997 gpt = opaque; 998 switch (addr) { 999 case 0x00: 1000 /* Time base counter */ 1001 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1002 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1003 break; 1004 case 0x10: 1005 /* Output enable */ 1006 ret = gpt->oe; 1007 break; 1008 case 0x14: 1009 /* Output level */ 1010 ret = gpt->ol; 1011 break; 1012 case 0x18: 1013 /* Interrupt mask */ 1014 ret = gpt->im; 1015 break; 1016 case 0x1C: 1017 case 0x20: 1018 /* Interrupt status */ 1019 ret = gpt->is; 1020 break; 1021 case 0x24: 1022 /* Interrupt enable */ 1023 ret = gpt->ie; 1024 break; 1025 case 0x80 ... 0x90: 1026 /* Compare timer */ 1027 idx = (addr - 0x80) >> 2; 1028 ret = gpt->comp[idx]; 1029 break; 1030 case 0xC0 ... 0xD0: 1031 /* Compare mask */ 1032 idx = (addr - 0xC0) >> 2; 1033 ret = gpt->mask[idx]; 1034 break; 1035 default: 1036 ret = -1; 1037 break; 1038 } 1039 1040 return ret; 1041 } 1042 1043 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1044 unsigned size) 1045 { 1046 ppc4xx_gpt_t *gpt; 1047 int idx; 1048 1049 #ifdef DEBUG_I2C 1050 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1051 value); 1052 #endif 1053 gpt = opaque; 1054 switch (addr) { 1055 case 0x00: 1056 /* Time base counter */ 1057 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1058 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1059 ppc4xx_gpt_compute_timer(gpt); 1060 break; 1061 case 0x10: 1062 /* Output enable */ 1063 gpt->oe = value & 0xF8000000; 1064 ppc4xx_gpt_set_outputs(gpt); 1065 break; 1066 case 0x14: 1067 /* Output level */ 1068 gpt->ol = value & 0xF8000000; 1069 ppc4xx_gpt_set_outputs(gpt); 1070 break; 1071 case 0x18: 1072 /* Interrupt mask */ 1073 gpt->im = value & 0x0000F800; 1074 break; 1075 case 0x1C: 1076 /* Interrupt status set */ 1077 gpt->is |= value & 0x0000F800; 1078 ppc4xx_gpt_set_irqs(gpt); 1079 break; 1080 case 0x20: 1081 /* Interrupt status clear */ 1082 gpt->is &= ~(value & 0x0000F800); 1083 ppc4xx_gpt_set_irqs(gpt); 1084 break; 1085 case 0x24: 1086 /* Interrupt enable */ 1087 gpt->ie = value & 0x0000F800; 1088 ppc4xx_gpt_set_irqs(gpt); 1089 break; 1090 case 0x80 ... 0x90: 1091 /* Compare timer */ 1092 idx = (addr - 0x80) >> 2; 1093 gpt->comp[idx] = value & 0xF8000000; 1094 ppc4xx_gpt_compute_timer(gpt); 1095 break; 1096 case 0xC0 ... 0xD0: 1097 /* Compare mask */ 1098 idx = (addr - 0xC0) >> 2; 1099 gpt->mask[idx] = value & 0xF8000000; 1100 ppc4xx_gpt_compute_timer(gpt); 1101 break; 1102 } 1103 } 1104 1105 static const MemoryRegionOps gpt_ops = { 1106 .read = ppc4xx_gpt_read, 1107 .write = ppc4xx_gpt_write, 1108 .valid.min_access_size = 4, 1109 .valid.max_access_size = 4, 1110 .endianness = DEVICE_NATIVE_ENDIAN, 1111 }; 1112 1113 static void ppc4xx_gpt_cb (void *opaque) 1114 { 1115 ppc4xx_gpt_t *gpt; 1116 1117 gpt = opaque; 1118 ppc4xx_gpt_set_irqs(gpt); 1119 ppc4xx_gpt_set_outputs(gpt); 1120 ppc4xx_gpt_compute_timer(gpt); 1121 } 1122 1123 static void ppc4xx_gpt_reset (void *opaque) 1124 { 1125 ppc4xx_gpt_t *gpt; 1126 int i; 1127 1128 gpt = opaque; 1129 timer_del(gpt->timer); 1130 gpt->oe = 0x00000000; 1131 gpt->ol = 0x00000000; 1132 gpt->im = 0x00000000; 1133 gpt->is = 0x00000000; 1134 gpt->ie = 0x00000000; 1135 for (i = 0; i < 5; i++) { 1136 gpt->comp[i] = 0x00000000; 1137 gpt->mask[i] = 0x00000000; 1138 } 1139 } 1140 1141 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1142 { 1143 ppc4xx_gpt_t *gpt; 1144 int i; 1145 1146 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1147 for (i = 0; i < 5; i++) { 1148 gpt->irqs[i] = irqs[i]; 1149 } 1150 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1151 #ifdef DEBUG_GPT 1152 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1153 #endif 1154 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1155 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1156 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1157 } 1158 1159 /*****************************************************************************/ 1160 /* PowerPC 405CR */ 1161 enum { 1162 PPC405CR_CPC0_PLLMR = 0x0B0, 1163 PPC405CR_CPC0_CR0 = 0x0B1, 1164 PPC405CR_CPC0_CR1 = 0x0B2, 1165 PPC405CR_CPC0_PSR = 0x0B4, 1166 PPC405CR_CPC0_JTAGID = 0x0B5, 1167 PPC405CR_CPC0_ER = 0x0B9, 1168 PPC405CR_CPC0_FR = 0x0BA, 1169 PPC405CR_CPC0_SR = 0x0BB, 1170 }; 1171 1172 enum { 1173 PPC405CR_CPU_CLK = 0, 1174 PPC405CR_TMR_CLK = 1, 1175 PPC405CR_PLB_CLK = 2, 1176 PPC405CR_SDRAM_CLK = 3, 1177 PPC405CR_OPB_CLK = 4, 1178 PPC405CR_EXT_CLK = 5, 1179 PPC405CR_UART_CLK = 6, 1180 PPC405CR_CLK_NB = 7, 1181 }; 1182 1183 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; 1184 struct ppc405cr_cpc_t { 1185 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1186 uint32_t sysclk; 1187 uint32_t psr; 1188 uint32_t cr0; 1189 uint32_t cr1; 1190 uint32_t jtagid; 1191 uint32_t pllmr; 1192 uint32_t er; 1193 uint32_t fr; 1194 }; 1195 1196 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) 1197 { 1198 uint64_t VCO_out, PLL_out; 1199 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; 1200 int M, D0, D1, D2; 1201 1202 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ 1203 if (cpc->pllmr & 0x80000000) { 1204 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ 1205 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ 1206 M = D0 * D1 * D2; 1207 VCO_out = (uint64_t)cpc->sysclk * M; 1208 if (VCO_out < 400000000 || VCO_out > 800000000) { 1209 /* PLL cannot lock */ 1210 cpc->pllmr &= ~0x80000000; 1211 goto bypass_pll; 1212 } 1213 PLL_out = VCO_out / D2; 1214 } else { 1215 /* Bypass PLL */ 1216 bypass_pll: 1217 M = D0; 1218 PLL_out = (uint64_t)cpc->sysclk * M; 1219 } 1220 CPU_clk = PLL_out; 1221 if (cpc->cr1 & 0x00800000) 1222 TMR_clk = cpc->sysclk; /* Should have a separate clock */ 1223 else 1224 TMR_clk = CPU_clk; 1225 PLB_clk = CPU_clk / D0; 1226 SDRAM_clk = PLB_clk; 1227 D0 = ((cpc->pllmr >> 10) & 0x3) + 1; 1228 OPB_clk = PLB_clk / D0; 1229 D0 = ((cpc->pllmr >> 24) & 0x3) + 2; 1230 EXT_clk = PLB_clk / D0; 1231 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; 1232 UART_clk = CPU_clk / D0; 1233 /* Setup CPU clocks */ 1234 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); 1235 /* Setup time-base clock */ 1236 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); 1237 /* Setup PLB clock */ 1238 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); 1239 /* Setup SDRAM clock */ 1240 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); 1241 /* Setup OPB clock */ 1242 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); 1243 /* Setup external clock */ 1244 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); 1245 /* Setup UART clock */ 1246 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); 1247 } 1248 1249 static uint32_t dcr_read_crcpc (void *opaque, int dcrn) 1250 { 1251 ppc405cr_cpc_t *cpc; 1252 uint32_t ret; 1253 1254 cpc = opaque; 1255 switch (dcrn) { 1256 case PPC405CR_CPC0_PLLMR: 1257 ret = cpc->pllmr; 1258 break; 1259 case PPC405CR_CPC0_CR0: 1260 ret = cpc->cr0; 1261 break; 1262 case PPC405CR_CPC0_CR1: 1263 ret = cpc->cr1; 1264 break; 1265 case PPC405CR_CPC0_PSR: 1266 ret = cpc->psr; 1267 break; 1268 case PPC405CR_CPC0_JTAGID: 1269 ret = cpc->jtagid; 1270 break; 1271 case PPC405CR_CPC0_ER: 1272 ret = cpc->er; 1273 break; 1274 case PPC405CR_CPC0_FR: 1275 ret = cpc->fr; 1276 break; 1277 case PPC405CR_CPC0_SR: 1278 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; 1279 break; 1280 default: 1281 /* Avoid gcc warning */ 1282 ret = 0; 1283 break; 1284 } 1285 1286 return ret; 1287 } 1288 1289 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) 1290 { 1291 ppc405cr_cpc_t *cpc; 1292 1293 cpc = opaque; 1294 switch (dcrn) { 1295 case PPC405CR_CPC0_PLLMR: 1296 cpc->pllmr = val & 0xFFF77C3F; 1297 break; 1298 case PPC405CR_CPC0_CR0: 1299 cpc->cr0 = val & 0x0FFFFFFE; 1300 break; 1301 case PPC405CR_CPC0_CR1: 1302 cpc->cr1 = val & 0x00800000; 1303 break; 1304 case PPC405CR_CPC0_PSR: 1305 /* Read-only */ 1306 break; 1307 case PPC405CR_CPC0_JTAGID: 1308 /* Read-only */ 1309 break; 1310 case PPC405CR_CPC0_ER: 1311 cpc->er = val & 0xBFFC0000; 1312 break; 1313 case PPC405CR_CPC0_FR: 1314 cpc->fr = val & 0xBFFC0000; 1315 break; 1316 case PPC405CR_CPC0_SR: 1317 /* Read-only */ 1318 break; 1319 } 1320 } 1321 1322 static void ppc405cr_cpc_reset (void *opaque) 1323 { 1324 ppc405cr_cpc_t *cpc; 1325 int D; 1326 1327 cpc = opaque; 1328 /* Compute PLLMR value from PSR settings */ 1329 cpc->pllmr = 0x80000000; 1330 /* PFWD */ 1331 switch ((cpc->psr >> 30) & 3) { 1332 case 0: 1333 /* Bypass */ 1334 cpc->pllmr &= ~0x80000000; 1335 break; 1336 case 1: 1337 /* Divide by 3 */ 1338 cpc->pllmr |= 5 << 16; 1339 break; 1340 case 2: 1341 /* Divide by 4 */ 1342 cpc->pllmr |= 4 << 16; 1343 break; 1344 case 3: 1345 /* Divide by 6 */ 1346 cpc->pllmr |= 2 << 16; 1347 break; 1348 } 1349 /* PFBD */ 1350 D = (cpc->psr >> 28) & 3; 1351 cpc->pllmr |= (D + 1) << 20; 1352 /* PT */ 1353 D = (cpc->psr >> 25) & 7; 1354 switch (D) { 1355 case 0x2: 1356 cpc->pllmr |= 0x13; 1357 break; 1358 case 0x4: 1359 cpc->pllmr |= 0x15; 1360 break; 1361 case 0x5: 1362 cpc->pllmr |= 0x16; 1363 break; 1364 default: 1365 break; 1366 } 1367 /* PDC */ 1368 D = (cpc->psr >> 23) & 3; 1369 cpc->pllmr |= D << 26; 1370 /* ODP */ 1371 D = (cpc->psr >> 21) & 3; 1372 cpc->pllmr |= D << 10; 1373 /* EBPD */ 1374 D = (cpc->psr >> 17) & 3; 1375 cpc->pllmr |= D << 24; 1376 cpc->cr0 = 0x0000003C; 1377 cpc->cr1 = 0x2B0D8800; 1378 cpc->er = 0x00000000; 1379 cpc->fr = 0x00000000; 1380 ppc405cr_clk_setup(cpc); 1381 } 1382 1383 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) 1384 { 1385 int D; 1386 1387 /* XXX: this should be read from IO pins */ 1388 cpc->psr = 0x00000000; /* 8 bits ROM */ 1389 /* PFWD */ 1390 D = 0x2; /* Divide by 4 */ 1391 cpc->psr |= D << 30; 1392 /* PFBD */ 1393 D = 0x1; /* Divide by 2 */ 1394 cpc->psr |= D << 28; 1395 /* PDC */ 1396 D = 0x1; /* Divide by 2 */ 1397 cpc->psr |= D << 23; 1398 /* PT */ 1399 D = 0x5; /* M = 16 */ 1400 cpc->psr |= D << 25; 1401 /* ODP */ 1402 D = 0x1; /* Divide by 2 */ 1403 cpc->psr |= D << 21; 1404 /* EBDP */ 1405 D = 0x2; /* Divide by 4 */ 1406 cpc->psr |= D << 17; 1407 } 1408 1409 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], 1410 uint32_t sysclk) 1411 { 1412 ppc405cr_cpc_t *cpc; 1413 1414 cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); 1415 memcpy(cpc->clk_setup, clk_setup, 1416 PPC405CR_CLK_NB * sizeof(clk_setup_t)); 1417 cpc->sysclk = sysclk; 1418 cpc->jtagid = 0x42051049; 1419 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, 1420 &dcr_read_crcpc, &dcr_write_crcpc); 1421 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, 1422 &dcr_read_crcpc, &dcr_write_crcpc); 1423 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, 1424 &dcr_read_crcpc, &dcr_write_crcpc); 1425 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, 1426 &dcr_read_crcpc, &dcr_write_crcpc); 1427 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, 1428 &dcr_read_crcpc, &dcr_write_crcpc); 1429 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, 1430 &dcr_read_crcpc, &dcr_write_crcpc); 1431 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, 1432 &dcr_read_crcpc, &dcr_write_crcpc); 1433 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, 1434 &dcr_read_crcpc, &dcr_write_crcpc); 1435 ppc405cr_clk_init(cpc); 1436 qemu_register_reset(ppc405cr_cpc_reset, cpc); 1437 } 1438 1439 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, 1440 MemoryRegion ram_memories[4], 1441 hwaddr ram_bases[4], 1442 hwaddr ram_sizes[4], 1443 uint32_t sysclk, qemu_irq **picp, 1444 int do_init) 1445 { 1446 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1447 qemu_irq dma_irqs[4]; 1448 PowerPCCPU *cpu; 1449 CPUPPCState *env; 1450 qemu_irq *pic, *irqs; 1451 1452 memset(clk_setup, 0, sizeof(clk_setup)); 1453 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), 1454 &clk_setup[PPC405CR_CPU_CLK], 1455 &clk_setup[PPC405CR_TMR_CLK], sysclk); 1456 env = &cpu->env; 1457 /* Memory mapped devices registers */ 1458 /* PLB arbitrer */ 1459 ppc4xx_plb_init(env); 1460 /* PLB to OPB bridge */ 1461 ppc4xx_pob_init(env); 1462 /* OBP arbitrer */ 1463 ppc4xx_opba_init(0xef600600); 1464 /* Universal interrupt controller */ 1465 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 1466 irqs[PPCUIC_OUTPUT_INT] = 1467 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1468 irqs[PPCUIC_OUTPUT_CINT] = 1469 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1470 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1471 *picp = pic; 1472 /* SDRAM controller */ 1473 ppc4xx_sdram_init(env, pic[14], 1, ram_memories, 1474 ram_bases, ram_sizes, do_init); 1475 /* External bus controller */ 1476 ppc405_ebc_init(env); 1477 /* DMA controller */ 1478 dma_irqs[0] = pic[26]; 1479 dma_irqs[1] = pic[25]; 1480 dma_irqs[2] = pic[24]; 1481 dma_irqs[3] = pic[23]; 1482 ppc405_dma_init(env, dma_irqs); 1483 /* Serial ports */ 1484 if (serial_hd(0) != NULL) { 1485 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1486 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1487 DEVICE_BIG_ENDIAN); 1488 } 1489 if (serial_hd(1) != NULL) { 1490 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1491 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1492 DEVICE_BIG_ENDIAN); 1493 } 1494 /* IIC controller */ 1495 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1496 /* GPIO */ 1497 ppc405_gpio_init(0xef600700); 1498 /* CPU control */ 1499 ppc405cr_cpc_init(env, clk_setup, sysclk); 1500 1501 return env; 1502 } 1503 1504 /*****************************************************************************/ 1505 /* PowerPC 405EP */ 1506 /* CPU control */ 1507 enum { 1508 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1509 PPC405EP_CPC0_BOOT = 0x0F1, 1510 PPC405EP_CPC0_EPCTL = 0x0F3, 1511 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1512 PPC405EP_CPC0_UCR = 0x0F5, 1513 PPC405EP_CPC0_SRR = 0x0F6, 1514 PPC405EP_CPC0_JTAGID = 0x0F7, 1515 PPC405EP_CPC0_PCI = 0x0F9, 1516 #if 0 1517 PPC405EP_CPC0_ER = xxx, 1518 PPC405EP_CPC0_FR = xxx, 1519 PPC405EP_CPC0_SR = xxx, 1520 #endif 1521 }; 1522 1523 enum { 1524 PPC405EP_CPU_CLK = 0, 1525 PPC405EP_PLB_CLK = 1, 1526 PPC405EP_OPB_CLK = 2, 1527 PPC405EP_EBC_CLK = 3, 1528 PPC405EP_MAL_CLK = 4, 1529 PPC405EP_PCI_CLK = 5, 1530 PPC405EP_UART0_CLK = 6, 1531 PPC405EP_UART1_CLK = 7, 1532 PPC405EP_CLK_NB = 8, 1533 }; 1534 1535 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1536 struct ppc405ep_cpc_t { 1537 uint32_t sysclk; 1538 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1539 uint32_t boot; 1540 uint32_t epctl; 1541 uint32_t pllmr[2]; 1542 uint32_t ucr; 1543 uint32_t srr; 1544 uint32_t jtagid; 1545 uint32_t pci; 1546 /* Clock and power management */ 1547 uint32_t er; 1548 uint32_t fr; 1549 uint32_t sr; 1550 }; 1551 1552 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1553 { 1554 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1555 uint32_t UART0_clk, UART1_clk; 1556 uint64_t VCO_out, PLL_out; 1557 int M, D; 1558 1559 VCO_out = 0; 1560 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1561 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1562 #ifdef DEBUG_CLOCKS_LL 1563 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1564 #endif 1565 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1566 #ifdef DEBUG_CLOCKS_LL 1567 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1568 #endif 1569 VCO_out = (uint64_t)cpc->sysclk * M * D; 1570 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1571 /* Error - unlock the PLL */ 1572 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1573 #if 0 1574 cpc->pllmr[1] &= ~0x80000000; 1575 goto pll_bypass; 1576 #endif 1577 } 1578 PLL_out = VCO_out / D; 1579 /* Pretend the PLL is locked */ 1580 cpc->boot |= 0x00000001; 1581 } else { 1582 #if 0 1583 pll_bypass: 1584 #endif 1585 PLL_out = cpc->sysclk; 1586 if (cpc->pllmr[1] & 0x40000000) { 1587 /* Pretend the PLL is not locked */ 1588 cpc->boot &= ~0x00000001; 1589 } 1590 } 1591 /* Now, compute all other clocks */ 1592 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1593 #ifdef DEBUG_CLOCKS_LL 1594 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1595 #endif 1596 CPU_clk = PLL_out / D; 1597 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1598 #ifdef DEBUG_CLOCKS_LL 1599 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1600 #endif 1601 PLB_clk = CPU_clk / D; 1602 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1603 #ifdef DEBUG_CLOCKS_LL 1604 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1605 #endif 1606 OPB_clk = PLB_clk / D; 1607 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1608 #ifdef DEBUG_CLOCKS_LL 1609 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1610 #endif 1611 EBC_clk = PLB_clk / D; 1612 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1613 #ifdef DEBUG_CLOCKS_LL 1614 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1615 #endif 1616 MAL_clk = PLB_clk / D; 1617 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1618 #ifdef DEBUG_CLOCKS_LL 1619 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1620 #endif 1621 PCI_clk = PLB_clk / D; 1622 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1623 #ifdef DEBUG_CLOCKS_LL 1624 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1625 #endif 1626 UART0_clk = PLL_out / D; 1627 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1628 #ifdef DEBUG_CLOCKS_LL 1629 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1630 #endif 1631 UART1_clk = PLL_out / D; 1632 #ifdef DEBUG_CLOCKS 1633 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1634 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1635 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1636 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1637 " UART1 %" PRIu32 "\n", 1638 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1639 UART0_clk, UART1_clk); 1640 #endif 1641 /* Setup CPU clocks */ 1642 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1643 /* Setup PLB clock */ 1644 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1645 /* Setup OPB clock */ 1646 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1647 /* Setup external clock */ 1648 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1649 /* Setup MAL clock */ 1650 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1651 /* Setup PCI clock */ 1652 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1653 /* Setup UART0 clock */ 1654 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1655 /* Setup UART1 clock */ 1656 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1657 } 1658 1659 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1660 { 1661 ppc405ep_cpc_t *cpc; 1662 uint32_t ret; 1663 1664 cpc = opaque; 1665 switch (dcrn) { 1666 case PPC405EP_CPC0_BOOT: 1667 ret = cpc->boot; 1668 break; 1669 case PPC405EP_CPC0_EPCTL: 1670 ret = cpc->epctl; 1671 break; 1672 case PPC405EP_CPC0_PLLMR0: 1673 ret = cpc->pllmr[0]; 1674 break; 1675 case PPC405EP_CPC0_PLLMR1: 1676 ret = cpc->pllmr[1]; 1677 break; 1678 case PPC405EP_CPC0_UCR: 1679 ret = cpc->ucr; 1680 break; 1681 case PPC405EP_CPC0_SRR: 1682 ret = cpc->srr; 1683 break; 1684 case PPC405EP_CPC0_JTAGID: 1685 ret = cpc->jtagid; 1686 break; 1687 case PPC405EP_CPC0_PCI: 1688 ret = cpc->pci; 1689 break; 1690 default: 1691 /* Avoid gcc warning */ 1692 ret = 0; 1693 break; 1694 } 1695 1696 return ret; 1697 } 1698 1699 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1700 { 1701 ppc405ep_cpc_t *cpc; 1702 1703 cpc = opaque; 1704 switch (dcrn) { 1705 case PPC405EP_CPC0_BOOT: 1706 /* Read-only register */ 1707 break; 1708 case PPC405EP_CPC0_EPCTL: 1709 /* Don't care for now */ 1710 cpc->epctl = val & 0xC00000F3; 1711 break; 1712 case PPC405EP_CPC0_PLLMR0: 1713 cpc->pllmr[0] = val & 0x00633333; 1714 ppc405ep_compute_clocks(cpc); 1715 break; 1716 case PPC405EP_CPC0_PLLMR1: 1717 cpc->pllmr[1] = val & 0xC0F73FFF; 1718 ppc405ep_compute_clocks(cpc); 1719 break; 1720 case PPC405EP_CPC0_UCR: 1721 /* UART control - don't care for now */ 1722 cpc->ucr = val & 0x003F7F7F; 1723 break; 1724 case PPC405EP_CPC0_SRR: 1725 cpc->srr = val; 1726 break; 1727 case PPC405EP_CPC0_JTAGID: 1728 /* Read-only */ 1729 break; 1730 case PPC405EP_CPC0_PCI: 1731 cpc->pci = val; 1732 break; 1733 } 1734 } 1735 1736 static void ppc405ep_cpc_reset (void *opaque) 1737 { 1738 ppc405ep_cpc_t *cpc = opaque; 1739 1740 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1741 cpc->epctl = 0x00000000; 1742 cpc->pllmr[0] = 0x00011010; 1743 cpc->pllmr[1] = 0x40000000; 1744 cpc->ucr = 0x00000000; 1745 cpc->srr = 0x00040000; 1746 cpc->pci = 0x00000000; 1747 cpc->er = 0x00000000; 1748 cpc->fr = 0x00000000; 1749 cpc->sr = 0x00000000; 1750 ppc405ep_compute_clocks(cpc); 1751 } 1752 1753 /* XXX: sysclk should be between 25 and 100 MHz */ 1754 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1755 uint32_t sysclk) 1756 { 1757 ppc405ep_cpc_t *cpc; 1758 1759 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1760 memcpy(cpc->clk_setup, clk_setup, 1761 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1762 cpc->jtagid = 0x20267049; 1763 cpc->sysclk = sysclk; 1764 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1765 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1766 &dcr_read_epcpc, &dcr_write_epcpc); 1767 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1768 &dcr_read_epcpc, &dcr_write_epcpc); 1769 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1770 &dcr_read_epcpc, &dcr_write_epcpc); 1771 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1772 &dcr_read_epcpc, &dcr_write_epcpc); 1773 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1774 &dcr_read_epcpc, &dcr_write_epcpc); 1775 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1776 &dcr_read_epcpc, &dcr_write_epcpc); 1777 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1778 &dcr_read_epcpc, &dcr_write_epcpc); 1779 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1780 &dcr_read_epcpc, &dcr_write_epcpc); 1781 #if 0 1782 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1783 &dcr_read_epcpc, &dcr_write_epcpc); 1784 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1785 &dcr_read_epcpc, &dcr_write_epcpc); 1786 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1787 &dcr_read_epcpc, &dcr_write_epcpc); 1788 #endif 1789 } 1790 1791 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1792 MemoryRegion ram_memories[2], 1793 hwaddr ram_bases[2], 1794 hwaddr ram_sizes[2], 1795 uint32_t sysclk, qemu_irq **picp, 1796 int do_init) 1797 { 1798 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1799 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1800 PowerPCCPU *cpu; 1801 CPUPPCState *env; 1802 qemu_irq *pic, *irqs; 1803 1804 memset(clk_setup, 0, sizeof(clk_setup)); 1805 /* init CPUs */ 1806 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1807 &clk_setup[PPC405EP_CPU_CLK], 1808 &tlb_clk_setup, sysclk); 1809 env = &cpu->env; 1810 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1811 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1812 /* Internal devices init */ 1813 /* Memory mapped devices registers */ 1814 /* PLB arbitrer */ 1815 ppc4xx_plb_init(env); 1816 /* PLB to OPB bridge */ 1817 ppc4xx_pob_init(env); 1818 /* OBP arbitrer */ 1819 ppc4xx_opba_init(0xef600600); 1820 /* Initialize timers */ 1821 ppc_booke_timers_init(cpu, sysclk, 0); 1822 /* Universal interrupt controller */ 1823 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 1824 irqs[PPCUIC_OUTPUT_INT] = 1825 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1826 irqs[PPCUIC_OUTPUT_CINT] = 1827 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1828 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1829 *picp = pic; 1830 /* SDRAM controller */ 1831 /* XXX 405EP has no ECC interrupt */ 1832 ppc4xx_sdram_init(env, pic[17], 2, ram_memories, 1833 ram_bases, ram_sizes, do_init); 1834 /* External bus controller */ 1835 ppc405_ebc_init(env); 1836 /* DMA controller */ 1837 dma_irqs[0] = pic[5]; 1838 dma_irqs[1] = pic[6]; 1839 dma_irqs[2] = pic[7]; 1840 dma_irqs[3] = pic[8]; 1841 ppc405_dma_init(env, dma_irqs); 1842 /* IIC controller */ 1843 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1844 /* GPIO */ 1845 ppc405_gpio_init(0xef600700); 1846 /* Serial ports */ 1847 if (serial_hd(0) != NULL) { 1848 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1849 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1850 DEVICE_BIG_ENDIAN); 1851 } 1852 if (serial_hd(1) != NULL) { 1853 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1854 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1855 DEVICE_BIG_ENDIAN); 1856 } 1857 /* OCM */ 1858 ppc405_ocm_init(env); 1859 /* GPT */ 1860 gpt_irqs[0] = pic[19]; 1861 gpt_irqs[1] = pic[20]; 1862 gpt_irqs[2] = pic[21]; 1863 gpt_irqs[3] = pic[22]; 1864 gpt_irqs[4] = pic[23]; 1865 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1866 /* PCI */ 1867 /* Uses pic[3], pic[16], pic[18] */ 1868 /* MAL */ 1869 mal_irqs[0] = pic[11]; 1870 mal_irqs[1] = pic[12]; 1871 mal_irqs[2] = pic[13]; 1872 mal_irqs[3] = pic[14]; 1873 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1874 /* Ethernet */ 1875 /* Uses pic[9], pic[15], pic[17] */ 1876 /* CPU control */ 1877 ppc405ep_cpc_init(env, clk_setup, sysclk); 1878 1879 return env; 1880 } 1881